| b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 1 | From f5f011742b6ec9ad1db54de9e8296f1d5a3ede8a Mon Sep 17 00:00:00 2001 |
| 2 | From: Claudiu Manoil <claudiu.manoil@nxp.com> |
| 3 | Date: Fri, 14 Jun 2019 19:24:27 +0300 |
| 4 | Subject: [PATCH] arm64: dts: fsl: ls1028a: Add Felix switch port DT node |
| 5 | |
| 6 | Add the switch device node, available on PF5, so that the |
| 7 | switch port sub-nodes (net devices) can be linked to |
| 8 | corresponding board specific phy nodes (external ports) or |
| 9 | have their link mode defined (internal ports). |
| 10 | The switch device features 6 ports, 4 with external links |
| 11 | and 2 internally facing to the ls1028a SoC and connected via |
| 12 | fixed links to 2 internal enetc ethernet contoller ports. |
| 13 | Add the corresponding enetc internal port device nodes, |
| 14 | mapped to PF2 and PF6 PCIe functions. |
| 15 | And don't forget to enable the 4MB BAR4 in the root complex |
| 16 | ECAM space, where the switch registers are mapped. |
| 17 | |
| 18 | Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com> |
| 19 | --- |
| 20 | arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 58 +++++++++++++++++++++++++- |
| 21 | 1 file changed, 57 insertions(+), 1 deletion(-) |
| 22 | |
| 23 | --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi |
| 24 | +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi |
| 25 | @@ -748,7 +748,9 @@ |
| 26 | /* PF1: VF0-1 BAR0 - non-prefetchable memory */ |
| 27 | 0x82000000 0x0 0x00000000 0x1 0xf8210000 0x0 0x020000 |
| 28 | /* PF1: VF0-1 BAR2 - prefetchable memory */ |
| 29 | - 0xc2000000 0x0 0x00000000 0x1 0xf8230000 0x0 0x020000>; |
| 30 | + 0xc2000000 0x0 0x00000000 0x1 0xf8230000 0x0 0x020000 |
| 31 | + /* BAR4 (PF5) - non-prefetchable memory */ |
| 32 | + 0x82000000 0x0 0x00000000 0x1 0xfc000000 0x0 0x400000>; |
| 33 | |
| 34 | enetc_port0: ethernet@0,0 { |
| 35 | compatible = "fsl,enetc"; |
| 36 | @@ -764,12 +766,66 @@ |
| 37 | #address-cells = <1>; |
| 38 | #size-cells = <0>; |
| 39 | }; |
| 40 | + ethernet@0,2 { |
| 41 | + compatible = "fsl,enetc"; |
| 42 | + reg = <0x000200 0 0 0 0>; |
| 43 | + fixed-link { |
| 44 | + speed = <1000>; |
| 45 | + full-duplex; |
| 46 | + }; |
| 47 | + }; |
| 48 | ethernet@0,4 { |
| 49 | compatible = "fsl,enetc-ptp"; |
| 50 | reg = <0x000400 0 0 0 0>; |
| 51 | clocks = <&clockgen 2 3>; |
| 52 | little-endian; |
| 53 | }; |
| 54 | + switch@0,5 { |
| 55 | + compatible = "mscc,felix-switch"; |
| 56 | + reg = <0x000500 0 0 0 0>; |
| 57 | + |
| 58 | + ports { |
| 59 | + #address-cells = <1>; |
| 60 | + #size-cells = <0>; |
| 61 | + |
| 62 | + /* external ports */ |
| 63 | + switch_port0: port@0 { |
| 64 | + reg = <0>; |
| 65 | + }; |
| 66 | + switch_port1: port@1 { |
| 67 | + reg = <1>; |
| 68 | + }; |
| 69 | + switch_port2: port@2 { |
| 70 | + reg = <2>; |
| 71 | + }; |
| 72 | + switch_port3: port@3 { |
| 73 | + reg = <3>; |
| 74 | + }; |
| 75 | + /* internal to-cpu ports */ |
| 76 | + port@4 { |
| 77 | + reg = <4>; |
| 78 | + fixed-link { |
| 79 | + speed = <1000>; |
| 80 | + full-duplex; |
| 81 | + }; |
| 82 | + }; |
| 83 | + port@5 { |
| 84 | + reg = <5>; |
| 85 | + fixed-link { |
| 86 | + speed = <1000>; |
| 87 | + full-duplex; |
| 88 | + }; |
| 89 | + }; |
| 90 | + }; |
| 91 | + }; |
| 92 | + ethernet@0,6 { |
| 93 | + compatible = "fsl,enetc"; |
| 94 | + reg = <0x000600 0 0 0 0>; |
| 95 | + fixed-link { |
| 96 | + speed = <1000>; |
| 97 | + full-duplex; |
| 98 | + }; |
| 99 | + }; |
| 100 | }; |
| 101 | |
| 102 | rcpm: rcpm@1e34040 { |