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192.168.1.100 / T108 / 50f43abd51b98a89a2ec2d51cd2725a28869fae6 / . / marvell / linux / arch / arm / boot / dts / imx6dl-yapp4-common.dtsi
blob: 68af441e7894849be2218b5f6e179169a9905524 [file] [log] [blame]
b.liue9582032025-04-17 19:18:16 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2//
3// Copyright (C) 2015-2018 Y Soft Corporation, a.s.
4
5#include <dt-bindings/gpio/gpio.h>
6#include <dt-bindings/interrupt-controller/irq.h>
7#include <dt-bindings/pwm/pwm.h>
8
9/ {
10 backlight: backlight {
11 compatible = "pwm-backlight";
12 pwms = <&pwm1 0 500000 PWM_POLARITY_INVERTED>;
13 brightness-levels = <0 32 64 128 255>;
14 default-brightness-level = <32>;
15 num-interpolated-steps = <8>;
16 power-supply = <&sw2_reg>;
17 status = "disabled";
18 };
19
20 lcd_display: display {
21 compatible = "fsl,imx-parallel-display";
22 #address-cells = <1>;
23 #size-cells = <0>;
24 interface-pix-fmt = "rgb24";
25 pinctrl-names = "default";
26 pinctrl-0 = <&pinctrl_ipu1>;
27 status = "disabled";
28
29 port@0 {
30 reg = <0>;
31
32 lcd_display_in: endpoint {
33 remote-endpoint = <&ipu1_di0_disp0>;
34 };
35 };
36
37 port@1 {
38 reg = <1>;
39
40 lcd_display_out: endpoint {
41 remote-endpoint = <&lcd_panel_in>;
42 };
43 };
44 };
45
46 panel: panel {
47 compatible = "dataimage,scf0700c48ggu18";
48 power-supply = <&sw2_reg>;
49 status = "disabled";
50
51 port {
52 lcd_panel_in: endpoint {
53 remote-endpoint = <&lcd_display_out>;
54 };
55 };
56 };
57
58 reg_pcie: regulator-pcie {
59 compatible = "regulator-fixed";
60 pinctrl-names = "default";
61 pinctrl-0 = <&pinctrl_pcie_reg>;
62 regulator-name = "MPCIE_3V3";
63 regulator-min-microvolt = <3300000>;
64 regulator-max-microvolt = <3300000>;
65 gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>;
66 enable-active-high;
67 status = "disabled";
68 };
69
70 reg_usb_h1_vbus: regulator-usb-h1-vbus {
71 compatible = "regulator-fixed";
72 pinctrl-names = "default";
73 pinctrl-0 = <&pinctrl_usbh1_vbus>;
74 regulator-name = "usb_h1_vbus";
75 regulator-min-microvolt = <5000000>;
76 regulator-max-microvolt = <5000000>;
77 gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>;
78 enable-active-high;
79 status = "disabled";
80 };
81
82 reg_usb_otg_vbus: regulator-usb-otg-vbus {
83 compatible = "regulator-fixed";
84 pinctrl-names = "default";
85 pinctrl-0 = <&pinctrl_usbotg_vbus>;
86 regulator-name = "usb_otg_vbus";
87 regulator-min-microvolt = <5000000>;
88 regulator-max-microvolt = <5000000>;
89 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
90 enable-active-high;
91 status = "okay";
92 };
93};
94
95&fec {
96 pinctrl-names = "default";
97 pinctrl-0 = <&pinctrl_enet>;
98 phy-mode = "rgmii-id";
99 phy-supply = <&sw2_reg>;
100 status = "okay";
101
102 fixed-link {
103 speed = <1000>;
104 full-duplex;
105 };
106
107 mdio {
108 #address-cells = <1>;
109 #size-cells = <0>;
110
111 switch@10 {
112 compatible = "qca,qca8334";
113 reg = <0x10>;
114 reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
115
116 switch_ports: ports {
117 #address-cells = <1>;
118 #size-cells = <0>;
119
120 ethphy0: port@0 {
121 reg = <0>;
122 label = "cpu";
123 phy-mode = "rgmii-id";
124 ethernet = <&fec>;
125
126 fixed-link {
127 speed = <1000>;
128 full-duplex;
129 };
130 };
131
132 port@2 {
133 reg = <2>;
134 label = "eth2";
135 phy-mode = "internal";
136 phy-handle = <&phy_port2>;
137 };
138
139 port@3 {
140 reg = <3>;
141 label = "eth1";
142 phy-mode = "internal";
143 phy-handle = <&phy_port3>;
144 };
145 };
146
147 mdio {
148 #address-cells = <1>;
149 #size-cells = <0>;
150
151 phy_port2: ethernet-phy@1 {
152 reg = <1>;
153 };
154
155 phy_port3: ethernet-phy@2 {
156 reg = <2>;
157 };
158 };
159 };
160 };
161};
162
163&hdmi {
164 pinctrl-names = "default";
165 pinctrl-0 = <&pinctrl_hdmi_cec>;
166 ddc-i2c-bus = <&i2c2>;
167 status = "disabled";
168};
169
170&i2c2 {
171 clock-frequency = <100000>;
172 pinctrl-names = "default";
173 pinctrl-0 = <&pinctrl_i2c2>;
174 status = "okay";
175
176 pmic@8 {
177 compatible = "fsl,pfuze200";
178 pinctrl-names = "default";
179 pinctrl-0 = <&pinctrl_pmic>;
180 reg = <0x8>;
181
182 regulators {
183 sw1a_reg: sw1ab {
184 regulator-min-microvolt = <300000>;
185 regulator-max-microvolt = <1875000>;
186 regulator-boot-on;
187 regulator-always-on;
188 regulator-ramp-delay = <6250>;
189 };
190
191 sw2_reg: sw2 {
192 regulator-min-microvolt = <800000>;
193 regulator-max-microvolt = <3300000>;
194 regulator-boot-on;
195 regulator-always-on;
196 };
197
198 sw3a_reg: sw3a {
199 regulator-min-microvolt = <400000>;
200 regulator-max-microvolt = <1975000>;
201 regulator-boot-on;
202 regulator-always-on;
203 };
204
205 sw3b_reg: sw3b {
206 regulator-min-microvolt = <400000>;
207 regulator-max-microvolt = <1975000>;
208 regulator-boot-on;
209 regulator-always-on;
210 };
211
212 swbst_reg: swbst {
213 regulator-min-microvolt = <5000000>;
214 regulator-max-microvolt = <5150000>;
215 };
216
217 vgen1_reg: vgen1 {
218 regulator-min-microvolt = <800000>;
219 regulator-max-microvolt = <1550000>;
220 };
221
222 vgen2_reg: vgen2 {
223 regulator-min-microvolt = <800000>;
224 regulator-max-microvolt = <1550000>;
225 };
226
227 vgen3_reg: vgen3 {
228 regulator-min-microvolt = <1800000>;
229 regulator-max-microvolt = <3300000>;
230 regulator-always-on;
231 };
232
233 vgen4_reg: vgen4 {
234 regulator-min-microvolt = <1800000>;
235 regulator-max-microvolt = <3300000>;
236 regulator-always-on;
237 };
238
239 vgen5_reg: vgen5 {
240 regulator-min-microvolt = <1800000>;
241 regulator-max-microvolt = <3300000>;
242 regulator-always-on;
243 };
244
245 vgen6_reg: vgen6 {
246 regulator-min-microvolt = <1800000>;
247 regulator-max-microvolt = <3300000>;
248 regulator-always-on;
249 };
250
251 vref_reg: vrefddr {
252 regulator-boot-on;
253 regulator-always-on;
254 };
255
256 vsnvs_reg: vsnvs {
257 regulator-min-microvolt = <1000000>;
258 regulator-max-microvolt = <3000000>;
259 regulator-boot-on;
260 regulator-always-on;
261 };
262 };
263 };
264
265 leds: led-controller@30 {
266 compatible = "ti,lp5562";
267 reg = <0x30>;
268 clock-mode = /bits/ 8 <1>;
269 status = "disabled";
270
271 chan0 {
272 chan-name = "R";
273 led-cur = /bits/ 8 <0x20>;
274 max-cur = /bits/ 8 <0x60>;
275 };
276
277 chan1 {
278 chan-name = "G";
279 led-cur = /bits/ 8 <0x20>;
280 max-cur = /bits/ 8 <0x60>;
281 };
282
283 chan2 {
284 chan-name = "B";
285 led-cur = /bits/ 8 <0x20>;
286 max-cur = /bits/ 8 <0x60>;
287 };
288
289 chan3 {
290 chan-name = "W";
291 led-cur = /bits/ 8 <0x0>;
292 max-cur = /bits/ 8 <0x0>;
293 };
294 };
295
296 eeprom@57 {
297 compatible = "atmel,24c128";
298 reg = <0x57>;
299 pagesize = <64>;
300 status = "okay";
301 };
302
303 touchscreen: touchscreen@5c {
304 compatible = "pixcir,pixcir_tangoc";
305 reg = <0x5c>;
306 pinctrl-0 = <&pinctrl_touch>;
307 interrupt-parent = <&gpio4>;
308 interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
309 attb-gpio = <&gpio4 5 GPIO_ACTIVE_HIGH>;
310 reset-gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
311 touchscreen-size-x = <800>;
312 touchscreen-size-y = <480>;
313 status = "disabled";
314 };
315};
316
317&i2c3 {
318 clock-frequency = <100000>;
319 pinctrl-names = "default";
320 pinctrl-0 = <&pinctrl_i2c3>;
321 status = "disabled";
322
323 oled: oled@3d {
324 compatible = "solomon,ssd1305fb-i2c";
325 reg = <0x3d>;
326 solomon,height = <64>;
327 solomon,width = <128>;
328 solomon,page-offset = <0>;
329 solomon,prechargep2 = <15>;
330 reset-gpios = <&gpio_oled 1 GPIO_ACTIVE_LOW>;
331 vbat-supply = <&sw2_reg>;
332 status = "disabled";
333 };
334
335 gpio_oled: gpio@41 {
336 compatible = "nxp,pca9536";
337 gpio-controller;
338 #gpio-cells = <2>;
339 reg = <0x41>;
340 vcc-supply = <&sw2_reg>;
341 status = "disabled";
342 };
343};
344
345&iomuxc {
346 pinctrl_enet: enetgrp {
347 fsl,pins = <
348 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b020
349 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b020
350 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b020
351 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b020
352 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b020
353 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b020
354 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b020
355 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b020
356 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b020
357 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b020
358 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b020
359 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b020
360 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b020
361 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b020
362 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b010
363 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b010
364 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b098
365 >;
366 };
367
368 pinctrl_hdmi_cec: hdmicecgrp {
369 fsl,pins = <
370 MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1b898
371 >;
372 };
373
374 pinctrl_i2c2: i2c2grp {
375 fsl,pins = <
376 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b899
377 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b899
378 >;
379 };
380
381 pinctrl_i2c3: i2c3grp {
382 fsl,pins = <
383 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b899
384 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b899
385 >;
386 };
387
388 pinctrl_ipu1: ipu1grp {
389 fsl,pins = <
390 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
391 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
392 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
393 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
394 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
395 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
396 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
397 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
398 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
399 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
400 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
401 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
402 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
403 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
404 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
405 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
406 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
407 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
408 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
409 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
410 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
411 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
412 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
413 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
414 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
415 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
416 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
417 >;
418 };
419
420 pinctrl_pcie: pciegrp {
421 fsl,pins = <
422 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b098
423 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b098
424 MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b098
425 >;
426 };
427
428 pinctrl_pcie_reg: pciereggrp {
429 fsl,pins = <
430 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b098
431 >;
432 };
433
434 pinctrl_pmic: pmicgrp {
435 fsl,pins = <
436 MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b098
437 >;
438 };
439
440 pinctrl_pwm1: pwm1grp {
441 fsl,pins = <
442 MX6QDL_PAD_GPIO_9__PWM1_OUT 0x8
443 >;
444 };
445
446 pinctrl_touch: touchgrp {
447 fsl,pins = <
448 MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b098
449 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b098
450 >;
451 };
452
453 pinctrl_uart1: uart1grp {
454 fsl,pins = <
455 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0a8
456 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0a8
457 >;
458 };
459
460 pinctrl_usbh1: usbh1grp {
461 fsl,pins = <
462 MX6QDL_PAD_EIM_D30__USB_H1_OC 0x1b098
463 >;
464 };
465
466 pinctrl_usbh1_vbus: usbh1-vbus {
467 fsl,pins = <
468 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x98
469 >;
470 };
471
472 pinctrl_usbotg: usbotggrp {
473 fsl,pins = <
474 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x1b098
475 MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b098
476 >;
477 };
478
479 pinctrl_usbotg_vbus: usbotg-vbus {
480 fsl,pins = <
481 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x98
482 >;
483 };
484
485 pinctrl_usdhc3: usdhc3grp {
486 fsl,pins = <
487 MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b018
488 MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x1b018
489 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
490 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
491 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
492 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
493 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
494 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
495 >;
496 };
497
498 pinctrl_usdhc4: usdhc4grp {
499 fsl,pins = <
500 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x1f069
501 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10069
502 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17069
503 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17069
504 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17069
505 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17069
506 MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17069
507 MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17069
508 MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17069
509 MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17069
510 >;
511 };
512
513 pinctrl_wdog: wdoggrp {
514 fsl,pins = <
515 MX6QDL_PAD_GPIO_1__WDOG2_B 0x1b0b0
516 >;
517 };
518};
519
520&ipu1_di0_disp0 {
521 remote-endpoint = <&lcd_display_in>;
522};
523
524&pcie {
525 pinctrl-names = "default";
526 pinctrl-0 = <&pinctrl_pcie>;
527 reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
528 vpcie-supply = <&reg_pcie>;
529 status = "disabled";
530};
531
532&pwm1 {
533 #pwm-cells = <3>;
534 pinctrl-names = "default";
535 pinctrl-0 = <&pinctrl_pwm1>;
536 status = "disabled";
537};
538
539&uart1 {
540 pinctrl-names = "default";
541 pinctrl-0 = <&pinctrl_uart1>;
542 status = "okay";
543};
544
545&usbh1 {
546 pinctrl-names = "default";
547 pinctrl-0 = <&pinctrl_usbh1>;
548 vbus-supply = <&reg_usb_h1_vbus>;
549 status = "disabled";
550};
551
552&usbotg {
553 pinctrl-names = "default";
554 pinctrl-0 = <&pinctrl_usbotg>;
555 vbus-supply = <&reg_usb_otg_vbus>;
556 srp-disable;
557 hnp-disable;
558 adp-disable;
559 status = "okay";
560};
561
562&usbphy1 {
563 fsl,tx-d-cal = <106>;
564 status = "okay";
565};
566
567&usbphy2 {
568 fsl,tx-d-cal = <109>;
569 status = "disabled";
570};
571
572&usdhc3 {
573 pinctrl-names = "default";
574 pinctrl-0 = <&pinctrl_usdhc3>;
575 bus-width = <4>;
576 cd-gpios = <&gpio7 8 GPIO_ACTIVE_LOW>;
577 wp-gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>;
578 no-1-8-v;
579 keep-power-in-suspend;
580 wakeup-source;
581 vmmc-supply = <&sw2_reg>;
582 status = "disabled";
583};
584
585&usdhc4 {
586 pinctrl-names = "default";
587 pinctrl-0 = <&pinctrl_usdhc4>;
588 bus-width = <8>;
589 non-removable;
590 no-1-8-v;
591 keep-power-in-suspend;
592 vmmc-supply = <&sw2_reg>;
593 status = "okay";
594};
595
596&wdog1 {
597 status = "disabled";
598};
599
600&wdog2 {
601 pinctrl-names = "default";
602 pinctrl-0 = <&pinctrl_wdog>;
603 fsl,ext-reset-output;
604 status = "okay";
605};