| b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * Samsung's Exynos3250 based ARTIK5 evaluation board device tree source |
| 4 | * |
| 5 | * Copyright (c) 2016 Samsung Electronics Co., Ltd. |
| 6 | * http://www.samsung.com |
| 7 | * |
| 8 | * Device tree source file for Samsung's ARTIK5 evaluation board |
| 9 | * which is based on Samsung Exynos3250 SoC. |
| 10 | */ |
| 11 | |
| 12 | /dts-v1/; |
| 13 | #include "exynos3250-artik5.dtsi" |
| 14 | |
| 15 | / { |
| 16 | model = "Samsung ARTIK5 evaluation board"; |
| 17 | compatible = "samsung,artik5-eval", "samsung,artik5", |
| 18 | "samsung,exynos3250", "samsung,exynos3"; |
| 19 | }; |
| 20 | |
| 21 | &mshc_2 { |
| 22 | cap-sd-highspeed; |
| 23 | disable-wp; |
| 24 | vqmmc-supply = <&ldo3_reg>; |
| 25 | card-detect-delay = <200>; |
| 26 | clock-frequency = <100000000>; |
| 27 | max-frequency = <100000000>; |
| 28 | samsung,dw-mshc-ciu-div = <1>; |
| 29 | samsung,dw-mshc-sdr-timing = <0 1>; |
| 30 | samsung,dw-mshc-ddr-timing = <1 2>; |
| 31 | pinctrl-names = "default"; |
| 32 | pinctrl-0 = <&sd2_cmd &sd2_clk &sd2_cd &sd2_bus1 &sd2_bus4>; |
| 33 | bus-width = <4>; |
| 34 | status = "okay"; |
| 35 | }; |
| 36 | |
| 37 | &serial_2 { |
| 38 | status = "okay"; |
| 39 | }; |