| b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0-only |
| 2 | /* |
| 3 | * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ |
| 4 | */ |
| 5 | /dts-v1/; |
| 6 | |
| 7 | #include "omap34xx.dtsi" |
| 8 | #include "omap3-evm-common.dtsi" |
| 9 | #include "omap3-evm-processor-common.dtsi" |
| 10 | |
| 11 | / { |
| 12 | model = "TI OMAP35XX EVM (TMDSEVM3530)"; |
| 13 | compatible = "ti,omap3-evm", "ti,omap3430", "ti,omap3"; |
| 14 | }; |
| 15 | |
| 16 | &omap3_pmx_core2 { |
| 17 | pinctrl-names = "default"; |
| 18 | pinctrl-0 = <&hsusb2_2_pins>; |
| 19 | |
| 20 | ehci_phy_pins: pinmux_ehci_phy_pins { |
| 21 | pinctrl-single,pins = < |
| 22 | |
| 23 | /* EHCI PHY reset GPIO etk_d7.gpio_21 */ |
| 24 | OMAP3430_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) |
| 25 | |
| 26 | /* EHCI VBUS etk_d8.gpio_22 */ |
| 27 | OMAP3430_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) |
| 28 | >; |
| 29 | }; |
| 30 | |
| 31 | /* Used by OHCI and EHCI. OHCI won't work without external phy */ |
| 32 | hsusb2_2_pins: pinmux_hsusb2_2_pins { |
| 33 | pinctrl-single,pins = < |
| 34 | |
| 35 | /* etk_d10.hsusb2_clk */ |
| 36 | OMAP3430_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) |
| 37 | |
| 38 | /* etk_d11.hsusb2_stp */ |
| 39 | OMAP3430_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) |
| 40 | |
| 41 | /* etk_d12.hsusb2_dir */ |
| 42 | OMAP3430_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) |
| 43 | |
| 44 | /* etk_d13.hsusb2_nxt */ |
| 45 | OMAP3430_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) |
| 46 | |
| 47 | /* etk_d14.hsusb2_data0 */ |
| 48 | OMAP3430_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) |
| 49 | |
| 50 | /* etk_d15.hsusb2_data1 */ |
| 51 | OMAP3430_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) |
| 52 | >; |
| 53 | }; |
| 54 | }; |
| 55 | |
| 56 | &gpmc { |
| 57 | nand@0,0 { |
| 58 | compatible = "ti,omap2-nand"; |
| 59 | reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ |
| 60 | interrupt-parent = <&gpmc>; |
| 61 | interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ |
| 62 | <1 IRQ_TYPE_NONE>; /* termcount */ |
| 63 | linux,mtd-name= "micron,mt29f2g16abdhc"; |
| 64 | nand-bus-width = <16>; |
| 65 | gpmc,device-width = <2>; |
| 66 | ti,nand-ecc-opt = "bch8"; |
| 67 | |
| 68 | gpmc,sync-clk-ps = <0>; |
| 69 | gpmc,cs-on-ns = <0>; |
| 70 | gpmc,cs-rd-off-ns = <44>; |
| 71 | gpmc,cs-wr-off-ns = <44>; |
| 72 | gpmc,adv-on-ns = <6>; |
| 73 | gpmc,adv-rd-off-ns = <34>; |
| 74 | gpmc,adv-wr-off-ns = <44>; |
| 75 | gpmc,we-off-ns = <40>; |
| 76 | gpmc,oe-off-ns = <54>; |
| 77 | gpmc,access-ns = <64>; |
| 78 | gpmc,rd-cycle-ns = <82>; |
| 79 | gpmc,wr-cycle-ns = <82>; |
| 80 | gpmc,wr-access-ns = <40>; |
| 81 | gpmc,wr-data-mux-bus-ns = <0>; |
| 82 | |
| 83 | #address-cells = <1>; |
| 84 | #size-cells = <1>; |
| 85 | }; |
| 86 | }; |