b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * Copyright (C) 2023 ASR Microelectronics Co., Ltd. |
| 4 | */ |
| 5 | |
| 6 | /dts-v1/; |
| 7 | #include "asr1806.dtsi" |
| 8 | |
| 9 | / { |
| 10 | model = "ASR 1806(FALCON-T) Board EVB"; |
| 11 | compatible = "asr,1803-evb", "asr,1803"; |
| 12 | |
| 13 | chosen { |
| 14 | bootargs = "root=/dev/mtdblock5 rootfstype=squashfs init=/etc/preinit noinitrd console=ttyS0,115200 mem=128M"; |
| 15 | }; |
| 16 | |
| 17 | memory { |
| 18 | reg = <0x00000000 0x10000000>; |
| 19 | }; |
| 20 | |
| 21 | firmware { |
| 22 | optee { |
| 23 | compatible = "linaro,optee-tz"; |
| 24 | method = "smc"; |
| 25 | }; |
| 26 | }; |
| 27 | |
| 28 | soc { |
| 29 | axi@d4200000 { /* AXI */ |
| 30 | usbphy: usbphy@d4207000 { |
| 31 | status = "okay"; |
| 32 | }; |
| 33 | #ifdef CONFIG_USB_DWC2_ASR_OTG /* otg mode */ |
| 34 | usb: usb@c0000000 { |
| 35 | dr_mode = "otg"; |
| 36 | pinctrl-names = "default","sleep"; |
| 37 | pinctrl-0 = <&usb_id_pinmux &usb_host_pinmux>; |
| 38 | pinctrl-1 = <&usb_id_pinmux_slp &usb_host_pinmux>; |
| 39 | usbid_gpio = <99>; |
| 40 | edge_detect_gpio = <99>; |
| 41 | otg,use-gpio-vbus; |
| 42 | gpio-num = <122>; |
| 43 | status = "okay"; |
| 44 | }; |
| 45 | #else |
| 46 | usb: usb@c0000000 { |
| 47 | status = "okay"; |
| 48 | }; |
| 49 | #endif |
| 50 | |
| 51 | eth0: asr-eth@0xd4281800 { |
| 52 | compatible = "asr,asr-eth"; |
| 53 | pinctrl-names = "default", "rgmii-pins"; |
| 54 | pinctrl-0 = <&emac_pmx_func0 &emac_pmx_func2 &emac_pmx_func3>; |
| 55 | pinctrl-1 = <&emac_pmx_func0 &emac_pmx_func1 &emac_pmx_func2 &emac_pmx_func3>; |
| 56 | reg = <0xd4281800 0x200>; |
| 57 | interrupts = <10 11>; |
| 58 | lpm-qos = <PM_QOS_CPUIDLE_BLOCK_AXI>; |
| 59 | clocks = <&soc_clocks ASR1803_CLK_EMAC |
| 60 | &soc_clocks ASR1803_CLK_EMAC_PTP>; |
| 61 | clock-names = "emac-clk", "ptp-clk"; |
| 62 | ptp-support; |
| 63 | ptp-clk-rate = <100000000>; |
| 64 | status = "okay"; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 65 | enable-suspend; |
| 66 | reset-gpio = <&gpio 42 0>; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 67 | reset-active-low; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 68 | reset-delays-us = <100000 100000 100000>; |
| 69 | //ldo-gpio = <&gpio 40 0>; |
| 70 | //ldo-active-low; |
| 71 | // ldo-delays-us = <0 100000 100000>; |
| 72 | //vmmc-supply = <0x19>; |
| 73 | mdio-clk-div = <254>; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 74 | flow-control-threshold = <60 90>; |
| 75 | clk-tuning-enable; |
| 76 | /* clk-config(32bit) |
| 77 | * |
| 78 | * clk_sel(clk-config[23:16]) |
| 79 | * RGMII: |
| 80 | * tx | clk_sel: 0 - from external RX clock |
| 81 | * 1 - from inverted external RX clock |
| 82 | * rx | clk_sel: 0 - from external RX clock |
| 83 | * 1 - from inverted external RX clock |
| 84 | * |
| 85 | * RMII: |
| 86 | * tx | clk_sel: 0 - RMII clock |
| 87 | * 1 - Inverted RMII clock |
| 88 | * rx | clk_sel: 0 - RMII clock |
| 89 | * 1 - Inverted RMII clock |
| 90 | * |
| 91 | */ |
| 92 | #if 0 |
| 93 | /* enable 1000M phy*/ |
| 94 | 3v3-enable = <0>; /* IO voltage, 1 - 3.3v, 0 - 1.8v */ |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 95 | phy-handle = <&phy3>; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 96 | #else |
| 97 | /* enable 100M phy*/ |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 98 | 3v3-enable = <0>; /* IO voltage, 1 - 3.3v, 0 - 1.8v */ |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 99 | phy-handle = <&phy3>; |
| 100 | #endif |
| 101 | /* enable fix link for ethernet switch */ |
| 102 | /* |
| 103 | fixed-link { |
| 104 | speed = <100>; |
| 105 | full-duplex; |
| 106 | phy-mode = "rmii"; |
| 107 | }; |
| 108 | */ |
| 109 | |
| 110 | mdio: mdio-bus { |
| 111 | #address-cells = <0x1>; |
| 112 | #size-cells = <0x0>; |
| 113 | /* YT8521 10M/100M/100OM 1.8V RGMII PHY */ |
| 114 | phy0: phy@0 { |
| 115 | compatible = "ethernet-phy-ieee802.3-c22"; |
| 116 | device_type = "ethernet-phy"; |
| 117 | reg = <0x0>; /* set phy address*/ |
| 118 | phy-mode = "rgmii"; |
| 119 | tx_rx_delay = <0xb 0x0>; /* 150ps per step*/ |
| 120 | }; |
| 121 | |
| 122 | /* YT8512B 10M/100M 3.3V RMII PHY */ |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 123 | // phy3: phy@3 { |
| 124 | // compatible = "ethernet-phy-ieee802.3-c22"; |
| 125 | // device_type = "ethernet-phy"; |
| 126 | // reg = <0x3>; /* set phy address*/ |
| 127 | // phy-mode = "rmii"; |
| 128 | // driver_strength = <0x3>; |
| 129 | // }; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 130 | |
| 131 | /* IP175D 10M/100M 3.3V RMII SWITCH */ |
| 132 | phy1: phy@1 { |
| 133 | compatible = "ethernet-phy-ieee802.3-c22"; |
| 134 | device_type = "ethernet-phy"; |
| 135 | reg = <0x1>; /* set phy address*/ |
| 136 | phy-mode = "rmii"; |
| 137 | }; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 138 | |
| 139 | |
| 140 | /* jl 3103 phy */ |
| 141 | phy3: phy@3 { |
| 142 | compatible = "ethernet-phy-ieee802.3-c22"; |
| 143 | device_type = "ethernet-phy"; |
| 144 | reg = <0x3>; /* set phy address*/ |
| 145 | phy-mode = "rgmii-id"; |
| 146 | lynq,jl3103=<100 0>; |
| 147 | }; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 148 | }; |
| 149 | }; |
| 150 | qspi: spi@0xd420b000 { |
| 151 | asr,qspi-freq = <78000000>; |
| 152 | status = "okay"; |
| 153 | }; |
| 154 | /* SD card */ |
| 155 | sdh0: sdh@d4280000 { |
| 156 | pinctrl-names = "default", "slow", "fast", "sleep"; |
| 157 | pinctrl-0 = <&sdh0_pmx_func1 &sdh0_pmx_func2 &sdh0_pmx_func3>; |
| 158 | pinctrl-1 = <&sdh0_pmx_func1_slow &sdh0_pmx_func2_slow &sdh0_pmx_func3>; |
| 159 | pinctrl-2 = <&sdh0_pmx_func1_fast &sdh0_pmx_func2_fast &sdh0_pmx_func3>; |
| 160 | pinctrl-3 = <&sdh0_pmx_cd_wakeup>; |
| 161 | /* |
| 162 | * Genernal use, juse set vmmc-supply and vqmmc-supply |
| 163 | * vmmc-supply = <&supply1> |
| 164 | * vqmmc-supply = <&supply2> |
| 165 | * |
| 166 | * For compatibility, to select one from two supply source |
| 167 | * vmmc-supply = <&supply1 &supply1_backup>; |
| 168 | * vqmmc-supply = <&supply2 &supply2_backup>; |
| 169 | * vmmc2-supply = <&supply1_backup &supply1>; |
| 170 | * vqmmc2-supply = <&supply2_backup &supply2>; |
| 171 | */ |
| 172 | vmmc-supply = <&vcc_sdh1>; |
| 173 | vqmmc-supply = <&pm802ldo6>; |
| 174 | #ifndef CONFIG_ASR_DSDS |
| 175 | vmmc2-supply = <&vcc_sdh1 &pm802ldo4>; |
| 176 | vqmmc2-supply = <&pm803ldo8 &pm802ldo6>; |
| 177 | #endif |
| 178 | bus-width = <4>; |
| 179 | no-mmc; |
| 180 | no-sdio; |
| 181 | /*non-removable; |
| 182 | broken-cd;*/ |
| 183 | wp-inverted; |
| 184 | asr,sdh-pm-runtime-en; |
| 185 | asr,sdh-host-caps-disable = <(MMC_CAP_UHS_SDR104)>; |
| 186 | #if 1 /* CD via gpio */ |
| 187 | cd-gpios = <&gpio 90 1>; |
| 188 | asr,sdh-quirks2 = <( |
| 189 | SDHCI_QUIRK2_SET_AIB_MMC | |
| 190 | SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
| 191 | )>; |
| 192 | asr,sdh-host-caps = <( |
| 193 | MMC_CAP_CD_WAKE |
| 194 | )>; |
| 195 | asr,sdh-quirks = <( |
| 196 | SDHCI_QUIRK_BROKEN_CARD_DETECTION | |
| 197 | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
| 198 | )>; |
| 199 | #else /* CD via SDH */ |
| 200 | asr,sdh-quirks = <( |
| 201 | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
| 202 | )>; |
| 203 | asr,sdh-quirks2 = <( |
| 204 | SDHCI_QUIRK2_SET_AIB_MMC | |
| 205 | SDHCI_QUIRK2_PRESET_VALUE_BROKEN | |
| 206 | SDHCI_QUIRK2_BASE_CLOCK_ALWAYS_ON |
| 207 | )>; |
| 208 | #endif |
| 209 | /* prop "sdh-dtr-data": |
| 210 | <timing preset_rate src_rate tx_delay rx_delay tx_dline_reg rx_dline_reg> */ |
| 211 | asr,sdh-dtr-data = |
| 212 | <PXA_MMC_TIMING_LEGACY PXA_SDH_DTR_26M PXA_SDH_DTR_104M 0 0 0 0>, |
| 213 | <PXA_MMC_TIMING_SD_HS PXA_SDH_DTR_52M PXA_SDH_DTR_104M 0 0 0 0>, |
| 214 | <PXA_MMC_TIMING_UHS_DDR50 PXA_SDH_DTR_52M PXA_SDH_DTR_104M 0 0 0 3>, |
| 215 | <PXA_MMC_TIMING_UHS_SDR50 PXA_SDH_DTR_104M PXA_SDH_DTR_208M 0 0 0 0>, |
| 216 | <PXA_MMC_TIMING_UHS_SDR104 PXA_SDH_DTR_208M PXA_SDH_DTR_208M 0 0 0 0>, |
| 217 | <PXA_MMC_TIMING_MAX PXA_SDH_DTR_PS_NONE PXA_SDH_DTR_104M 0 0 0 0>; |
| 218 | status = "okay"; |
| 219 | }; |
| 220 | |
| 221 | /* SDIO */ |
| 222 | sdh1: sdh@d4280800 { |
| 223 | pinctrl-names = "default", "fast", "sleep"; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 224 | pinctrl-0 = <&sdh1_pmx_func1 &sdh1_pmx_func2>; |
| 225 | pinctrl-1 = <&sdh1_pmx_func1_fast &sdh1_pmx_func2_fast>; |
| 226 | /* pinctrl-2 = <&sdh1_pmx_edge_wakeup>;*/ |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 227 | bus-width = <4>; |
| 228 | no-mmc; |
| 229 | no-sd; |
| 230 | non-removable; |
| 231 | keep-power-in-suspend; |
| 232 | enable-sdio-wakeup; |
| 233 | /* clk-scaling-config: |
| 234 | <up_threshold down_threshold polling_interval> */ |
| 235 | clk-scaling-config = <25 12 200>; |
| 236 | min-ddr-qos = <156000 312000 400000>; |
| 237 | asr,sdh-pm-runtime-en; |
| 238 | asr,sdh-quirks = <( |
| 239 | SDHCI_QUIRK_BROKEN_CARD_DETECTION | |
| 240 | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
| 241 | )>; |
| 242 | asr,sdh-quirks2 = <( |
| 243 | SDHCI_QUIRK2_NO_TIMER_RETUNING | |
| 244 | SDHCI_QUIRK2_PRESET_VALUE_BROKEN | |
| 245 | SDHCI_QUIRK2_BASE_CLOCK_ALWAYS_ON |
| 246 | )>; |
| 247 | asr,sdh-pm-caps = <(MMC_PM_KEEP_POWER)>; |
| 248 | asr,sdh-host-caps2 = <( |
| 249 | MMC_CAP2_ONLY_1_8V | |
| 250 | MMC_CAP2_DISABLE_PROBE_CDSCAN | |
| 251 | MMC_CAP2_CLK_SCALE | |
| 252 | MMC_CAP2_BUS_CLK_NO_SCALE |
| 253 | )>; |
| 254 | /* prop "sdh-dtr-data": |
| 255 | <timing preset_rate src_rate tx_delay rx_delay tx_dline_reg rx_dline_reg> */ |
| 256 | asr,sdh-dtr-data = |
| 257 | <PXA_MMC_TIMING_LEGACY PXA_SDH_DTR_26M PXA_SDH_DTR_104M 0 0 0 0>, |
| 258 | <PXA_MMC_TIMING_SD_HS PXA_SDH_DTR_45M PXA_SDH_DTR_89M 0 0 0 0>, |
| 259 | <PXA_MMC_TIMING_UHS_DDR50 PXA_SDH_DTR_52M PXA_SDH_DTR_104M 0 0 0 3>, |
| 260 | <PXA_MMC_TIMING_UHS_SDR50 PXA_SDH_DTR_83M PXA_SDH_DTR_83M 0 0 0 3>, |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 261 | //<PXA_MMC_TIMING_UHS_SDR104 PXA_SDH_DTR_208M PXA_SDH_DTR_208M 0 0 0 0>, |
| 262 | <PXA_MMC_TIMING_UHS_SDR104 PXA_SDH_DTR_52M PXA_SDH_DTR_52M 0 0 0 0>, |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 263 | <PXA_MMC_TIMING_MAX PXA_SDH_DTR_PS_NONE PXA_SDH_DTR_89M 0 0 0 0>; |
| 264 | status = "okay"; |
| 265 | }; |
| 266 | pcie0: pcie@0xd4288000{ |
| 267 | reset-gpios = <&gpio 42 0 >; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 268 | status = "disbabled"; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 269 | }; |
| 270 | pciephy0: pcie-phy@d4206000 { |
| 271 | status = "okay"; |
| 272 | }; |
| 273 | }; |
| 274 | |
| 275 | apb@d4000000 { |
| 276 | ssp_dai1: pxa-ssp-dai@1 { |
| 277 | compatible = "asr,pxa-ssp-dai"; |
| 278 | reg = <0x1 0x0>; |
| 279 | |
| 280 | port = <&ssp1>; |
| 281 | pinctrl-names = "default","ssp"; |
| 282 | pinctrl-0 = <&i2s_gpio>; |
| 283 | pinctrl-1 = <&i2s_func>; |
| 284 | ssp-gpio = <&gpio 25 0 &gpio 26 0 &gpio 27 0 &gpio 28 0>; |
| 285 | |
| 286 | dmas = <&pdma0 54 1 |
| 287 | &pdma0 55 1>; |
| 288 | dma-names = "rx", "tx"; |
| 289 | |
| 290 | platform_driver_name = "pdma_platform"; |
| 291 | burst_size = <4>; |
| 292 | playback_period_bytes = <2048>; |
| 293 | playback_buffer_bytes = <4096>; |
| 294 | capture_period_bytes = <2048>; |
| 295 | capture_buffer_bytes = <4096>; |
| 296 | }; |
| 297 | mfpr: mfpr@d401e000 { |
| 298 | status = "okay"; |
| 299 | /* intend to replace lpm-board-cfg |
| 300 | no-apbsd-in-d1pp = <0x1>; //"wakeup-state-d1pp" |
| 301 | pin1:pin1@d401e01B0 { |
| 302 | offset = <0x1B0>; |
| 303 | udr-cfg = <0xA040>; |
| 304 | }; |
| 305 | pin2:pin2@d401e01B4 { |
| 306 | offset = <0x1B4>; |
| 307 | udr-cfg = <0xA040>; |
| 308 | }; |
| 309 | */ |
| 310 | }; |
| 311 | timer0: timer@d4014000 { |
| 312 | status = "okay"; |
| 313 | }; |
| 314 | uart1: uart@d4017000 { /* nezhas evb use ap uart */ |
| 315 | pinctrl-names = "default","sleep"; |
| 316 | pinctrl-0 = <&uart1_pmx_func1 &uart1_pmx_func2>; |
| 317 | pinctrl-1 = <&uart1_pmx_func1_sleep &uart1_pmx_func2>; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 318 | //edge-wakeup-gpio = <&gpio 29 0>; /* GPIO29: AP UART rx pin */ |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 319 | status = "okay"; |
| 320 | }; |
| 321 | uart2: uart@d4036000 { |
| 322 | pinctrl-names = "default"; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 323 | pinctrl-0 = <&gps_pmx_uart_rxd &gps_pmx_uart_txd &gps_pmx_func_cts_rts>; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 324 | status = "okay"; |
| 325 | }; |
| 326 | uart3: uart@d4018000 { |
| 327 | pinctrl-names = "default"; |
| 328 | pinctrl-0 = <&uart3_pmx_func>; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 329 | status = "okay"; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 330 | }; |
| 331 | uart4: uart@d401f000 { |
| 332 | pinctrl-names = "default"; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 333 | pinctrl-0 = <&uart4_pmx_func>; /*BAUD :9600*/ |
| 334 | /*pinctrl-0 = <&uart4_pmx_func_rxd &uart4_pmx_func_txd &uart4_pmx_func_cts_rts>;*/ |
| 335 | status = "okay"; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 336 | }; |
| 337 | rtc: rtc@d4010000 { |
| 338 | status = "okay"; |
| 339 | }; |
| 340 | pmx: pinmux@d401e000 { |
| 341 | /* pin base = base_addr / 4, nr pins & gpio function */ |
| 342 | pinctrl-single,gpio-range = < |
| 343 | /* |
| 344 | * GPIO number is hardcoded for range at here. |
| 345 | * In gpio chip, GPIO number is not hardcoded for range. |
| 346 | * Since one gpio pin may be routed to multiple pins, |
| 347 | * define these gpio range in pxa910-dkb.dts not pxa910.dtsi. |
| 348 | */ |
| 349 | /*&range 80 4 0 */ /* GPIO25 ~ GPIO28 */ |
| 350 | &range 55 32 0 /* GPIO0 ~ GPIO31 */ |
| 351 | &range 87 32 0 /* GPIO32 ~ GPIO63 */ |
| 352 | &range 119 32 0 /* GPIO64 ~ GPIO95 */ |
| 353 | &range 151 32 0 /* GPIO96 ~ GPIO127 */ |
| 354 | >; |
| 355 | |
| 356 | ssp0_pmx_func: ssp0_pmx_func { |
| 357 | pinctrl-single,pins = < |
| 358 | GPIO36 AF1 /* TXD */ |
| 359 | GPIO35 AF1 /* RXD */ |
| 360 | GPIO34 AF1 /* FRM */ |
| 361 | /*GPIO34 AF0*/ /* FRM *//* DXS101 Use the config of Cs-gpios */ |
| 362 | GPIO33 AF1 /* SCLK */ |
| 363 | >; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 364 | DS_SLOW0;PULL_NONE;EDGE_NONE;SL_NORMAL; //DS_MEDIUM modify for overvoltage |
| 365 | }; |
| 366 | ssp2_pmx_func: ssp2_pmx_func { |
| 367 | pinctrl-single,pins = < |
| 368 | GPIO37 AF3 /* TXD */ |
| 369 | GPIO38 AF3 /* SCLK */ |
| 370 | GPIO39 AF3 /* FRM */ |
| 371 | GPIO40 AF3 /* RXD */ |
| 372 | >; |
| 373 | DS_SLOW0;PULL_NONE;EDGE_NONE;SL_NORMAL; //DS_MEDIUM modify for overvoltage |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 374 | }; |
| 375 | lcd_bl_func: lcd_bl_func { |
| 376 | pinctrl-single,pins = < |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 377 | /* VCXO_OUT AF1 GPIO126, lcd bl */ |
| 378 | /* GPIO24 AF0 reset */ |
| 379 | /* GPIO22 AF0 lcd d/c */ |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 380 | >; |
| 381 | MFP_DEFAULT; |
| 382 | }; |
| 383 | uart1_pmx_func1: uart1_pmx_func1 { |
| 384 | pinctrl-single,pins = < |
| 385 | GPIO29 AF1 |
| 386 | >; |
| 387 | MFP_DEFAULT; |
| 388 | }; |
| 389 | uart1_pmx_func2: uart1_pmx_func2 { |
| 390 | pinctrl-single,pins = < |
| 391 | GPIO30 AF1 |
| 392 | >; |
| 393 | MFP_DEFAULT; |
| 394 | }; |
| 395 | uart1_pmx_func1_sleep: uart1_pmx_func1_sleep { |
| 396 | pinctrl-single,pins = < |
| 397 | GPIO29 AF1 |
| 398 | >; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 399 | DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 400 | }; |
| 401 | twsi0_pmx_func: twsi0_pmx_func { |
| 402 | pinctrl-single,pins = < |
| 403 | GPIO49 AF1 |
| 404 | GPIO50 AF1 |
| 405 | >; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 406 | DS_MEDIUM;PULL_NONE;EDGE_NONE;LPM_FLOAT; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 407 | }; |
| 408 | twsi0_pmx_gpio: twsi0_pmx_gpio { |
| 409 | pinctrl-single,pins = < |
| 410 | GPIO49 AF0 |
| 411 | GPIO50 AF0 |
| 412 | >; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 413 | DS_MEDIUM;PULL_NONE;EDGE_NONE;LPM_FLOAT; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 414 | }; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 415 | #if 1 |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 416 | twsi1_pmx_func: twsi1_pmx_func { |
| 417 | pinctrl-single,pins = < |
| 418 | GPIO10 AF1 |
| 419 | GPIO11 AF1 |
| 420 | >; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 421 | DS_SLOW0;PULL_NONE;EDGE_NONE;LPM_FLOAT; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 422 | }; |
| 423 | twsi1_pmx_gpio: twsi1_pmx_gpio { |
| 424 | pinctrl-single,pins = < |
| 425 | GPIO10 AF0 |
| 426 | GPIO11 AF0 |
| 427 | >; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 428 | DS_SLOW0;PULL_NONE;EDGE_NONE;LPM_FLOAT; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 429 | }; |
| 430 | #endif |
| 431 | /* no pull, no LPM */ |
| 432 | dvc_pmx_func: dvc_pmx_func { |
| 433 | /* hw-dvc */ |
| 434 | pinctrl-single,pins = < |
| 435 | TDS_DIO0 AF0 |
| 436 | TDS_DIO1 AF0 |
| 437 | >; |
| 438 | DS_MEDIUM;PULL_FLOAT;EDGE_NONE;SL_NORMAL; |
| 439 | }; |
| 440 | leds_pmx_func: leds_pmx_func { |
| 441 | pinctrl-single,pins = < |
| 442 | DF_IO10 AF1 |
| 443 | DF_IO11 AF1 |
| 444 | DF_IO12 AF1 |
| 445 | >; |
| 446 | DS_MEDIUM;PULL_FLOAT;EDGE_NONE;SL_NORMAL; |
| 447 | }; |
| 448 | |
| 449 | gps_pmx_onoff: gps_pmx_onoff { |
| 450 | pinctrl-single,pins = < |
| 451 | TDS_TXREV AF1 |
| 452 | >; |
| 453 | DS_MEDIUM;PULL_DOWN;EDGE_NONE;SL_NORMAL; |
| 454 | }; |
| 455 | gps_pmx_reset: gps_pmx_reset { |
| 456 | pinctrl-single,pins = < |
| 457 | TDS_RXON AF1 |
| 458 | >; |
| 459 | DS_MEDIUM;PULL_DOWN;EDGE_NONE;SL_NORMAL; |
| 460 | }; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 461 | |
| 462 | //zqy |
| 463 | gnss_clk_on: gnss_clk_on { |
| 464 | pinctrl-single,pins = < |
| 465 | GPIO43 AF2 /*32K CLK */ |
| 466 | |
| 467 | /*VCXO_REQ AF1 GPIO[125] GPS_WAKE_HOST */ |
| 468 | GPIO47 AF0 /* HOST_WAKE_GPS */ |
| 469 | GPIO45 AF0 /*RESET */ |
| 470 | CLK_REQ AF1 /*sleep en*/ |
| 471 | |
| 472 | >; |
| 473 | DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_LOW; |
| 474 | }; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 475 | gps_pmx_uart_rxd: gps_pmx_uart_rxd { |
| 476 | /* gps dedicated uart */ |
| 477 | pinctrl-single,pins = < |
| 478 | GPIO51 AF1 |
| 479 | GPIO32 AF1 |
| 480 | >; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 481 | DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 482 | }; |
| 483 | gps_pmx_uart_txd: gps_pmx_uart_txd { |
| 484 | /* gps dedicated uart */ |
| 485 | pinctrl-single,pins = < |
| 486 | GPIO52 AF1 |
| 487 | GPIO31 AF1 |
| 488 | >; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 489 | DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 490 | }; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 491 | gps_pmx_func_cts_rts: gps_pmx_func_cts_rts { |
| 492 | pinctrl-single,pins = < |
| 493 | GPIO31 AF1 /* cts */ |
| 494 | GPIO32 AF1 /* rts */ |
| 495 | >; |
| 496 | DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL; |
| 497 | }; |
| 498 | |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 499 | uart3_pmx_func: uart3_pmx_func { |
| 500 | pinctrl-single,pins = < |
| 501 | GPIO53 AF1 /* RX */ |
| 502 | GPIO54 AF1 /* TX */ |
| 503 | >; |
| 504 | MFP_DEFAULT; |
| 505 | }; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 506 | |
| 507 | |
| 508 | uart4_pmx_func_rxd: uart4_pmx_func_rxd { |
| 509 | pinctrl-single,pins = < |
| 510 | GPIO37 AF2 |
| 511 | GPIO40 AF2 |
| 512 | >; |
| 513 | DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL; |
| 514 | }; |
| 515 | uart4_pmx_func_txd: uart4_pmx_func_txd { |
| 516 | pinctrl-single,pins = < |
| 517 | GPIO38 AF2 |
| 518 | GPIO39 AF2 |
| 519 | >; |
| 520 | DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL; |
| 521 | }; |
| 522 | |
| 523 | uart4_pmx_func_cts_rts: uart4_pmx_func_cts_rts { |
| 524 | pinctrl-single,pins = < |
| 525 | GPIO39 AF2 |
| 526 | GPIO40 AF2 |
| 527 | >; |
| 528 | DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL; |
| 529 | }; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 530 | uart4_pmx_func: uart4_pmx_func { |
| 531 | pinctrl-single,pins = < |
| 532 | GPIO44 AF1 /* RX */ |
| 533 | GPIO45 AF1 /* TX */ |
| 534 | >; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 535 | DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 536 | }; |
| 537 | panel_rst_func: panel_rst_func { |
| 538 | pinctrl-single,pins = < |
| 539 | DF_nCS1 AF1 |
| 540 | >; |
| 541 | DS_MEDIUM;PULL_FLOAT;EDGE_NONE;SL_NORMAL; |
| 542 | }; |
| 543 | |
| 544 | sd_ldo_en: sd_ldo_en { |
| 545 | pinctrl-single,pins = < |
| 546 | GPIO45 AF0 |
| 547 | >; |
| 548 | MFP_PULL_DOWN; |
| 549 | }; |
| 550 | sdh0_pmx_func1: sdh0_pmx_func1 { |
| 551 | pinctrl-single,pins = < |
| 552 | MMC1_DAT3 AF0 |
| 553 | MMC1_DAT2 AF0 |
| 554 | MMC1_DAT1 AF0 |
| 555 | MMC1_DAT0 AF0 |
| 556 | MMC1_CMD AF0 |
| 557 | >; |
| 558 | DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL; |
| 559 | }; |
| 560 | sdh0_pmx_func2: sdh0_pmx_func2 { |
| 561 | pinctrl-single,pins = < |
| 562 | MMC1_CLK AF0 |
| 563 | >; |
| 564 | DS_MEDIUM;PULL_NONE;EDGE_NONE; |
| 565 | }; |
| 566 | sdh0_pmx_func3: sdh0_pmx_func3 { |
| 567 | pinctrl-single,pins = < |
| 568 | MMC1_CD AF1 |
| 569 | >; |
| 570 | DS_MEDIUM;PULL_UP;EDGE_NONE;SL_NORMAL; |
| 571 | }; |
| 572 | sdh0_pmx_cd_wakeup: sdh0_pmx_func1_cd_wakeup { |
| 573 | pinctrl-single,pins = < |
| 574 | MMC1_CD AF1 |
| 575 | >; |
| 576 | DS_MEDIUM;PULL_UP;EDGE_BOTH;SL_NORMAL; |
| 577 | }; |
| 578 | sdh0_pmx_func1_slow: sdh0_pmx_func1_slow { |
| 579 | pinctrl-single,pins = < |
| 580 | MMC1_DAT3 AF0 |
| 581 | MMC1_DAT2 AF0 |
| 582 | MMC1_DAT1 AF0 |
| 583 | MMC1_DAT0 AF0 |
| 584 | MMC1_CMD AF0 |
| 585 | >; |
| 586 | DS_FAST0;PULL_NONE;EDGE_NONE;SL_NORMAL; |
| 587 | }; |
| 588 | sdh0_pmx_func2_slow: sdh0_pmx_func2_slow { |
| 589 | pinctrl-single,pins = < |
| 590 | MMC1_CLK AF0 |
| 591 | >; |
| 592 | DS_FAST0;PULL_NONE;EDGE_NONE; |
| 593 | }; |
| 594 | sdh0_pmx_func1_fast: sdh0_pmx_func1_fast { |
| 595 | pinctrl-single,pins = < |
| 596 | MMC1_DAT3 AF0 |
| 597 | MMC1_DAT2 AF0 |
| 598 | MMC1_DAT1 AF0 |
| 599 | MMC1_DAT0 AF0 |
| 600 | MMC1_CMD AF0 |
| 601 | >; |
| 602 | DS_FAST1;PULL_NONE;EDGE_NONE;SL_NORMAL; |
| 603 | }; |
| 604 | sdh0_pmx_func2_fast: sdh0_pmx_func2_fast { |
| 605 | pinctrl-single,pins = < |
| 606 | MMC1_CLK AF0 |
| 607 | >; |
| 608 | DS_FAST1;PULL_NONE;EDGE_NONE; |
| 609 | }; |
| 610 | sdh1_pmx_func1_fast: sdh1_pmx_func1_fast { |
| 611 | pinctrl-single,pins = < |
| 612 | TDS_DIO13 AF0 /* WLAN_DAT3 */ |
| 613 | TDS_DIO14 AF0 /* WLAN_DAT2 */ |
| 614 | TDS_DIO15 AF0 /* WLAN_DAT1 */ |
| 615 | TDS_DIO16 AF0 /* WLAN_DAT0 */ |
| 616 | TDS_DIO17 AF0 /* WLAN_CMD */ |
| 617 | >; |
| 618 | DS_FAST0;PULL_NONE;EDGE_NONE;SL_NORMAL; |
| 619 | }; |
| 620 | sdh1_pmx_func2_fast: sdh1_pmx_func2_fast { |
| 621 | pinctrl-single,pins = < |
| 622 | TDS_DIO18 AF0 /* WLAN_CLK */ |
| 623 | >; |
| 624 | DS_FAST0;PULL_DOWN;EDGE_NONE;SL_NORMAL; |
| 625 | }; |
| 626 | sdh1_pmx_func1: sdh1_pmx_func1 { |
| 627 | pinctrl-single,pins = < |
| 628 | TDS_DIO13 AF0 /* WLAN_DAT3 */ |
| 629 | TDS_DIO14 AF0 /* WLAN_DAT2 */ |
| 630 | TDS_DIO15 AF0 /* WLAN_DAT1 */ |
| 631 | TDS_DIO16 AF0 /* WLAN_DAT0 */ |
| 632 | TDS_DIO17 AF0 /* WLAN_CMD */ |
| 633 | >; |
| 634 | DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_LOW; |
| 635 | }; |
| 636 | sdh1_pmx_func2: sdh1_pmx_func2 { |
| 637 | pinctrl-single,pins = < |
| 638 | TDS_DIO18 AF0 /* WLAN_CLK */ |
| 639 | >; |
| 640 | DS_MEDIUM;PULL_DOWN;EDGE_NONE;SL_LOW; |
| 641 | }; |
| 642 | sdh1_pmx_func3: sdh1_pmx_func3 { |
| 643 | pinctrl-single,pins = < |
| 644 | GPIO10 AF0 /* VCXO_REQ AF1 WLAN_WAKE_HOST */ |
| 645 | >; |
| 646 | MFP_PULL_DOWN; |
| 647 | }; |
| 648 | sdh1_pmx_edge_wakeup: sdh1_pmx_edge_wakeup { |
| 649 | pinctrl-single,pins = < |
| 650 | GPIO10 AF0 /* VCXO_REQ AF1 */ |
| 651 | >; |
| 652 | DS_MEDIUM;PULL_DOWN;EDGE_RISE;SL_NORMAL; |
| 653 | }; |
| 654 | sdh1_pmx_pd_rst_off: sdh1_pmx_pd_rst_off { |
| 655 | pinctrl-single,pins = < |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 656 | /* GPIO11 AF0 GPIO31 AF0 WLAN_PDn */ |
| 657 | /* GPIO08 AF0 GPIO32 AF0 LDO_EN */ |
| 658 | MMC1_CD AF1 |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 659 | >; |
| 660 | MFP_PULL_DOWN; |
| 661 | }; |
| 662 | sdh1_pmx_pd_rst_on: sdh1_pmx_pd_rst_on { |
| 663 | pinctrl-single,pins = < |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 664 | /* GPIO11 AF0 GPIO31 AF0 WLAN_PDn */ |
| 665 | /* GPIO08 AF0 GPIO32 AF0 LDO_EN */ |
| 666 | MMC1_CD AF1 |
| 667 | >; |
| 668 | MFP_PULL_UP; |
| 669 | }; |
| 670 | |
| 671 | |
| 672 | mbtk_sdh_pmx_off: mbtk_sdh_pmx_off { |
| 673 | pinctrl-single,pins = < |
| 674 | VCXO_REQ AF1 //gpio125 wlan en |
| 675 | GPIO123 AF1 //wlan pwr en |
| 676 | VCXO_OUT AF1 /*gpio127 wifi wake*/ |
| 677 | >; |
| 678 | MFP_PULL_DOWN; |
| 679 | }; |
| 680 | mbtk_sdh_pmx_on: mbtk_sdh_pmx_on { |
| 681 | pinctrl-single,pins = < |
| 682 | VCXO_REQ AF1 //gpio125 wlan en |
| 683 | GPIO123 AF1 //wlan pwr en |
| 684 | VCXO_OUT AF1 /*gpio127 wifi wake*/ |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 685 | >; |
| 686 | MFP_PULL_UP; |
| 687 | }; |
| 688 | alc5616_pmx_func1: alc5616_pmx_func1 { |
| 689 | pinctrl-single,pins = < |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 690 | /* GPIO08 AF0 AP_UART1_DCD_N -> CODEC_IRQ */ |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 691 | GPIO20 AF7 /* MCLK:I2S_SYSCLK */ |
| 692 | >; |
| 693 | MFP_DEFAULT; |
| 694 | }; |
| 695 | alc5616_pmx_func2: alc5616_pmx_func2 { |
| 696 | pinctrl-single,pins = < |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 697 | /* GPIO08 AF0 AP_UART1_DCD_N -> CODEC_IRQ */ |
| 698 | GPIO20 AF7 /* MCLK:I2S_SYSCLK */ |
| 699 | >; |
| 700 | MFP_DEFAULT; |
| 701 | }; |
| 702 | |
| 703 | es8311_pa_func1: es8311_pa_func1 { |
| 704 | pinctrl-single,pins = < |
| 705 | GPIO20 AF7 /* MCLK:I2S_SYSCLK */ |
| 706 | >; |
| 707 | MFP_DEFAULT; |
| 708 | }; |
| 709 | es8311_pa_func2: es8311_pa_func2 { |
| 710 | pinctrl-single,pins = < |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 711 | GPIO20 AF7 /* MCLK:I2S_SYSCLK */ |
| 712 | >; |
| 713 | MFP_DEFAULT; |
| 714 | }; |
| 715 | audio_pa_pmx_func: audio_pa_pmx_func { |
| 716 | pinctrl-single,pins = < |
| 717 | GPIO14 AF0 /* PA */ |
| 718 | >; |
| 719 | MFP_DEFAULT; |
| 720 | }; |
| 721 | ecall_pmx_func: ecall_pmx_func { |
| 722 | pinctrl-single,pins = < |
| 723 | GPIO08 AF0 /* auto mode ecall */ |
| 724 | GPIO09 AF0 /* manual mode ecall */ |
| 725 | >; |
| 726 | MFP_DEFAULT; |
| 727 | }; |
| 728 | slic_pmx_func1: slic_pmx_func1 { |
| 729 | pinctrl-single,pins = < |
| 730 | GPIO20 AF0 /* SLIC_INT, GPIO20 */ |
| 731 | VCXO_OUT AF1 /* GPIO127, SLIC_3V3LDO_EN/LCD_BK_EN */ |
| 732 | >; |
| 733 | MFP_DEFAULT; |
| 734 | }; |
| 735 | slic_pmx_func2: slic_pmx_func2 { |
| 736 | pinctrl-single,pins = < |
| 737 | GPIO21 AF0 /* SLIC_RESET, GPIO21 */ |
| 738 | >; |
| 739 | MFP_DEFAULT; |
| 740 | }; |
| 741 | slic_pmx_func1_sleep: slic_pmx_func1_sleep { |
| 742 | pinctrl-single,pins = < |
| 743 | GPIO20 AF0 /* SLIC_INT, GPIO20 */ |
| 744 | >; |
| 745 | DS_MEDIUM;PULL_UP;EDGE_BOTH;SL_NORMAL; |
| 746 | }; |
| 747 | |
| 748 | otg_vbus_func: otg_vbus_func { |
| 749 | pinctrl-single,pins = < |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 750 | /* VBUS_DRV AF1 GPIO[122] */ |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 751 | >; |
| 752 | DS_MEDIUM;PULL_DOWN;EDGE_NONE; |
| 753 | }; |
| 754 | |
| 755 | emac_pmx_func0: emac_pmx_func0 { |
| 756 | pinctrl-single,pins = < |
| 757 | GPIO00 AF1 /* GMAC1_RX_DV */ |
| 758 | GPIO01 AF1 /* GMAC1_RX_D0 */ |
| 759 | GPIO02 AF1 /* GMAC1_RX_D1 */ |
| 760 | GPIO03 AF1 /* GMAC1_RX_CLK */ |
| 761 | /* GPIO04 AF1 GMAC1_RX_D2 */ |
| 762 | /* GPIO05 AF1 GMAC1_RX_D3 */ |
| 763 | GPIO06 AF1 /* GMAC1_TX_D0 */ |
| 764 | GPIO07 AF1 /* GMAC1_TX_D1 */ |
| 765 | /* GPIO12 AF1 GMAC1_TX_CLK */ |
| 766 | /* GPIO13 AF1 GMAC1_TX_D2 */ |
| 767 | /* GPIO14 AF1 GMAC1_TX_D3 */ |
| 768 | GPIO15 AF1 /* GMAC1_TX_EN */ |
| 769 | GPIO16 AF1 /* GMAC1_TX_MDC */ |
| 770 | /* GPIO17 AF1 GMAC1_TX_MDIO */ |
| 771 | >; |
| 772 | DS_MEDIUM;PULL_DOWN;EDGE_NONE;SL_NORMAL; |
| 773 | }; |
| 774 | emac_pmx_func1: emac_pmx_func1 { |
| 775 | pinctrl-single,pins = < |
| 776 | GPIO04 AF1 /* GMAC1_RX_D2 */ |
| 777 | GPIO05 AF1 /* GMAC1_RX_D3 */ |
| 778 | GPIO12 AF1 /* GMAC1_TX_CLK */ |
| 779 | GPIO13 AF1 /* GMAC1_TX_D2 */ |
| 780 | GPIO14 AF1 /* GMAC1_TX_D3 */ |
| 781 | >; |
| 782 | DS_MEDIUM;PULL_DOWN;EDGE_NONE;SL_NORMAL; |
| 783 | }; |
| 784 | emac_pmx_func2: emac_pmx_func2 { |
| 785 | pinctrl-single,pins = < |
| 786 | GPIO17 AF1 /* GMAC1_TX_MDIO */ |
| 787 | GPIO18 AF1 /* GMAC1_TX_INT_N */ |
| 788 | >; |
| 789 | DS_MEDIUM;PULL_UP;EDGE_NONE;SL_NORMAL; |
| 790 | }; |
| 791 | emac_pmx_func3: emac_pmx_func3 { |
| 792 | pinctrl-single,pins = < |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 793 | GPIO42 AF0 /* RESET */ |
| 794 | /* GPIO40 AF0 LDO_EN */ |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 795 | >; |
| 796 | DS_SLOW0;PULL_FLOAT;EDGE_NONE;SL_NORMAL; |
| 797 | }; |
| 798 | usim1_pmx_func: usim1_pmx_func { |
| 799 | pinctrl-single,pins = < |
yq.wang | 107f986 | 2025-05-12 15:44:50 +0800 | [diff] [blame] | 800 | PRI_TCK AF1 |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 801 | >; |
| 802 | DS_MEDIUM;PULL_UP;EDGE_NONE;SL_NORMAL; |
| 803 | }; |
| 804 | usim1_pmx_func_sleep: usim1_pmx_func_sleep { |
| 805 | pinctrl-single,pins = < |
yq.wang | 107f986 | 2025-05-12 15:44:50 +0800 | [diff] [blame] | 806 | PRI_TCK AF1 |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 807 | >; |
| 808 | DS_MEDIUM;PULL_UP;EDGE_BOTH;SL_NORMAL; |
| 809 | }; |
| 810 | usim2_pmx_func: usim2_pmx_func { |
| 811 | pinctrl-single,pins = < |
| 812 | GPIO44 AF0 |
| 813 | >; |
| 814 | DS_MEDIUM;PULL_UP;EDGE_NONE;SL_NORMAL; |
| 815 | }; |
| 816 | usim2_pmx_func_sleep: usim2_pmx_func_sleep { |
| 817 | pinctrl-single,pins = < |
| 818 | GPIO44 AF0 |
| 819 | >; |
| 820 | DS_MEDIUM;PULL_UP;EDGE_BOTH;SL_NORMAL; |
| 821 | }; |
| 822 | pcie_pmx_pd_rst_off: pcie_pmx_pd_rst_off { |
| 823 | pinctrl-single,pins = < |
| 824 | GPIO42 AF0 /* PERST_N */ |
| 825 | GPIO24 AF0 /* DC_EN */ |
| 826 | >; |
| 827 | MFP_PULL_DOWN; |
| 828 | }; |
| 829 | pcie_pmx_pd_rst_on: pcie_pmx_pd_rst_on { |
| 830 | pinctrl-single,pins = < |
| 831 | GPIO42 AF0 /* PERST_N */ |
| 832 | GPIO24 AF0 /* DC_EN */ |
| 833 | >; |
| 834 | MFP_PULL_UP; |
| 835 | }; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 836 | pin_func_work: pin_func_work { |
| 837 | pinctrl-single,pins = < |
| 838 | |
| 839 | GPIO08 AF0 /*T108 status led* / |
| 840 | |
| 841 | VBUS_DRV AF2 /*32k*/ |
| 842 | |
| 843 | |
| 844 | GPIO46 AF0 /*wifi en*/ |
| 845 | |
| 846 | GPIO19 AF0 /*bt en*/ |
| 847 | |
| 848 | >; |
| 849 | MFP_DEFAULT; |
| 850 | }; |
| 851 | |
| 852 | |
| 853 | sc_ext_int0: sc_ext_int0 { |
| 854 | pinctrl-single,pins = < |
| 855 | GPIO21 AF0 |
| 856 | >; |
| 857 | DS_MEDIUM;PULL_NONE;EDGE_BOTH;SL_NORMAL; |
| 858 | }; |
| 859 | sc_ext_int1: sc_ext_int1 { |
| 860 | pinctrl-single,pins = < |
| 861 | GPIO22 AF0 |
| 862 | >; |
| 863 | MFP_DEFAULT; |
| 864 | }; |
| 865 | |
| 866 | sc_ext_int2: sc_ext_int2 { |
| 867 | pinctrl-single,pins = < |
| 868 | GPIO23 AF0 |
| 869 | >; |
| 870 | MFP_DEFAULT; |
| 871 | }; |
| 872 | |
| 873 | |
| 874 | sc_ext_int3: sc_ext_int3 { |
| 875 | pinctrl-single,pins = < |
| 876 | GPIO24 AF0 |
| 877 | >; |
| 878 | MFP_DEFAULT; |
| 879 | }; |
| 880 | |
| 881 | |
| 882 | mbtk_plat_irq_func: mbtk_plat_irq_func { |
| 883 | pinctrl-single,pins = < |
| 884 | |
| 885 | GPIO21 AF0 |
| 886 | GPIO22 AF0 |
| 887 | GPIO23 AF0 |
| 888 | GPIO24 AF0 |
| 889 | |
| 890 | >; |
| 891 | DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL; |
| 892 | }; |
| 893 | mbtk_plat_irq_func_sleep: mbtk_plat_irq_func_sleep { |
| 894 | pinctrl-single,pins = < |
| 895 | GPIO21 AF0 |
| 896 | GPIO22 AF0 |
| 897 | GPIO23 AF0 |
| 898 | GPIO24 AF0 |
| 899 | >; |
| 900 | DS_MEDIUM;PULL_NONE;EDGE_BOTH;SL_NORMAL; |
| 901 | }; |
| 902 | |
| 903 | |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 904 | gpiokey_pmx_func: gpiokey_pmx_func { |
| 905 | pinctrl-single,pins = < |
| 906 | GPIO09 AF0 |
| 907 | >; |
| 908 | DS_MEDIUM;PULL_UP;EDGE_NONE;SL_NORMAL; |
| 909 | }; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 910 | |
| 911 | wake_pmx_func1: wake_pmx_func1 { |
| 912 | pinctrl-single,pins = < |
| 913 | USB_ID AF1 |
| 914 | >; |
| 915 | DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL; |
| 916 | }; |
| 917 | |
hong.liu | f241688 | 2025-05-23 20:41:06 -0700 | [diff] [blame] | 918 | led_pmx_func1: led_pmx_func1 { |
| 919 | pinctrl-single,pins = < |
| 920 | GPIO08 AF0 |
| 921 | >; |
| 922 | DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL; |
| 923 | }; |
| 924 | |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 925 | |
| 926 | wake_pmx_func: wake_pmx_func { |
| 927 | pinctrl-single,pins = < |
| 928 | PRI_TDI AF1 /*GPIO117 WAKEUP_OUT*/ |
| 929 | |
| 930 | PRI_TMS AF1 /*GPIO118 WAKEUP_IN*/ |
| 931 | GPIO41 AF0 |
| 932 | PRI_TDO AF1 /*GPIO120*/ |
| 933 | |
| 934 | |
| 935 | >; |
| 936 | DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL; |
| 937 | }; |
| 938 | wake_pmx_func_sleep: wake_pmx_func_sleep { |
| 939 | pinctrl-single,pins = < |
| 940 | PRI_TDI AF1 /*GPIO117 WAKEUP_OUT*/ |
| 941 | |
| 942 | PRI_TMS AF1 /*GPIO118 WAKEUP_IN*/ |
| 943 | GPIO41 AF0 |
| 944 | PRI_TDO AF1 /*GPIO120*/ |
| 945 | |
| 946 | >; |
| 947 | DS_MEDIUM;PULL_NONE;EDGE_BOTH;SL_NORMAL; |
| 948 | }; |
| 949 | usb_id_pinmux: usb_id_pinmux { |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 950 | pinctrl-single,pins = < |
| 951 | USB_ID AF1/* usbid-gpio99 */ |
| 952 | >; |
| 953 | DS_MEDIUM;PULL_UP;EDGE_NONE;LPM_NONE; |
| 954 | }; |
| 955 | usb_id_pinmux_slp: usb_id_pinmux_slp { |
| 956 | pinctrl-single,pins = < |
| 957 | USB_ID AF1 /* usbid-gpio99 */ |
| 958 | >; |
| 959 | DS_MEDIUM;PULL_UP;EDGE_BOTH;LPM_NONE; |
| 960 | }; |
| 961 | usb_host_pinmux: usb_host_pinmux { |
| 962 | pinctrl-single,pins = < |
| 963 | VBUS_DRV AF1 /* gpio-122 */ |
| 964 | >; |
| 965 | DS_MEDIUM;PULL_FLOAT;EDGE_NONE;LPM_NONE; |
| 966 | }; |
| 967 | i2s_func: i2s_func { |
| 968 | pinctrl-single,pins = < |
| 969 | GPIO25 AF2 |
| 970 | GPIO26 AF2 |
| 971 | GPIO27 AF2 |
| 972 | GPIO28 AF2 |
| 973 | >; |
| 974 | MFP_DEFAULT; |
| 975 | }; |
| 976 | i2s_gpio: i2s_gpio { |
| 977 | pinctrl-single,pins = < |
| 978 | GPIO25 AF0 |
| 979 | GPIO26 AF0 |
| 980 | GPIO27 AF0 |
| 981 | GPIO28 AF0 |
| 982 | >; |
| 983 | MFP_LPM_FLOAT; |
| 984 | }; |
| 985 | }; |
| 986 | |
| 987 | ssp0: spi@d401b000 { |
| 988 | status = "okay"; |
| 989 | pinctrl-names = "default"; |
| 990 | pinctrl-0 = <&ssp0_pmx_func>; |
| 991 | asr,spi-inc-mode; |
| 992 | #ifdef CONFIG_FB_SPI_LCD |
| 993 | /* this enhancemnet feature is not suitable for |
| 994 | 3 line 9bits spi lcd. */ |
| 995 | /* asr,ssp-enhancement; */ |
| 996 | |
| 997 | lcd: spidev@0 { |
| 998 | #address-cells = <1>; |
| 999 | #size-cells = <1>; |
| 1000 | compatible = "spilcd"; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 1001 | // pinctrl-names = "default"; |
| 1002 | // pinctrl-0 = <&lcd_bl_func>; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 1003 | reg = <0>; |
| 1004 | /* ST7735: need to set spi-max-frequency to 26M |
| 1005 | * ST7789V: can set spi-max-frequency to 52M |
| 1006 | */ |
| 1007 | spi-max-frequency = <26000000>; |
| 1008 | xres = <128>; |
| 1009 | yres = <128>; |
| 1010 | bits = <8>; /* 8: 4line, 9: 3line */ |
| 1011 | rst_gpio = <&gpio 24 0>; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 1012 | // bl_gpio = <&gpio 126 0>; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 1013 | rs_gpio = <&gpio 22 0>; |
| 1014 | /* if comment the following statement, it means |
| 1015 | * the avdd is sit on the "always-on" ldo. |
| 1016 | */ |
| 1017 | /* avdd-supply = <&LDO1>; */ |
| 1018 | }; |
| 1019 | #else |
| 1020 | /*cs-gpios = <&gpio 34 0>;*//* DXS101 Use the config of Cs-gpios */ |
| 1021 | slic: spidev@0{ |
| 1022 | #address-cells = <1>; |
| 1023 | #size-cells = <1>; |
| 1024 | compatible = "asr,slic"; |
| 1025 | reg = <0>; |
| 1026 | spi-cpol; |
| 1027 | spi-cpha; |
| 1028 | spi-max-frequency = <6500000>; |
| 1029 | }; |
| 1030 | #endif |
| 1031 | }; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 1032 | ssp2: spi@d401c000{ |
| 1033 | status = "okay"; |
| 1034 | pinctrl-names = "default"; |
| 1035 | pinctrl-0 = <&ssp2_pmx_func>; |
| 1036 | asr,spi-inc-mode; |
| 1037 | cs-gpios = <&gpio 39 0>; |
| 1038 | status = "okay"; |
| 1039 | mbtk: spidev@0{ |
| 1040 | compatible = "asr,spidev"; |
| 1041 | reg = <0>; |
| 1042 | status = "okay"; |
| 1043 | spi-cpol; |
| 1044 | spi-cpha; |
| 1045 | spi-max-frequency = <6500000>; |
| 1046 | }; |
| 1047 | }; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 1048 | twsi0: i2c@d4011000 { |
| 1049 | status= "okay"; |
| 1050 | alc5616@1b { |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 1051 | status= "disabled"; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 1052 | compatible = "asrmicro,alc5616"; |
| 1053 | reg = <0x1b>; |
| 1054 | pinctrl-names = "default", "sleep"; |
| 1055 | pinctrl-0 = <&alc5616_pmx_func1>; |
| 1056 | pinctrl-1 = <&alc5616_pmx_func2>; |
| 1057 | clocks = <&soc_clocks ASR1803_CLK_I2S_SYSCLK>; |
| 1058 | clock-names = "i2s_sys_clk"; |
| 1059 | #if 0 |
| 1060 | 3V3-gpio = <&gpio 23 0>;/* CODEC_LDO_EN */ |
| 1061 | irq-gpio = <&gpio 24 0>;/* CODEC_IRQ for headset detection */ |
| 1062 | #else |
| 1063 | irq-gpio = <&gpio 8 0>;/* CODEC_IRQ for headset detection */ |
| 1064 | #endif |
| 1065 | }; |
| 1066 | |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 1067 | nau8810@1a { |
| 1068 | compatible = "marvell,nau8810"; |
| 1069 | clocks = <&soc_clocks ASR1803_CLK_I2S_SYSCLK>; |
| 1070 | clock-names = "i2s_sys_clk"; |
| 1071 | |
| 1072 | |
| 1073 | pinctrl-names = "default"; |
| 1074 | pinctrl-0 = <&es8311_pa_func1>; |
| 1075 | pinctrl-1 = <&es8311_pa_func2>; |
| 1076 | reg = <0x1a>; |
| 1077 | status= "disabled"; |
| 1078 | }; |
| 1079 | |
| 1080 | es8311@18 { |
| 1081 | compatible = "ambarella,es8311"; |
| 1082 | reg = <0x18>; |
| 1083 | clocks = <&soc_clocks ASR1803_CLK_I2S_SYSCLK>; |
| 1084 | clock-names = "i2s_sys_clk"; |
| 1085 | |
| 1086 | pinctrl-names = "default"; |
| 1087 | pinctrl-0 = <&es8311_pa_func1>; |
| 1088 | pinctrl-1 = <&es8311_pa_func2>; |
| 1089 | |
| 1090 | // gpios = <&gpio 21 0>, |
| 1091 | // <&gpio 23 0>, |
| 1092 | // <&gpio 24 0>, |
| 1093 | // <&gpio 22 0>; |
| 1094 | |
| 1095 | status= "okay"; |
| 1096 | }; |
| 1097 | |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 1098 | /* |
| 1099 | pmic4: 88pm805@38 { |
| 1100 | compatible = "marvell,88pm805"; |
| 1101 | reg = <0x38>; |
| 1102 | }; |
| 1103 | */ |
| 1104 | }; |
| 1105 | twsi1: i2c@d4010800 { |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 1106 | #if 1 |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 1107 | pinctrl-names = "default","gpio"; |
| 1108 | pinctrl-0 = <&twsi1_pmx_func>; |
| 1109 | pinctrl-1 = <&twsi1_pmx_gpio>; |
| 1110 | i2c-gpio = <&gpio 10 0 &gpio 11 0>; |
| 1111 | #endif |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 1112 | status= "okay"; |
| 1113 | //nau8810@1a { |
| 1114 | // compatible = "marvell,nau8810"; |
| 1115 | // reg = <0x1a>; |
| 1116 | //}; |
| 1117 | |
| 1118 | |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 1119 | }; |
| 1120 | twsi2: i2c@d4037000 { |
| 1121 | status = "okay"; |
| 1122 | |
| 1123 | pmic4: 88pm805@38 { |
| 1124 | compatible = "marvell,88pm805"; |
| 1125 | reg = <0x38>; |
| 1126 | }; |
| 1127 | |
| 1128 | pmic5: pm802@0 { |
| 1129 | compatible = "asr,pm802"; |
| 1130 | reg = <0x00>; |
| 1131 | interrupts = <4>; |
| 1132 | interrupt-parent = <&intc>; |
| 1133 | interrupt-controller; |
| 1134 | #interrupt-cells = <1>; |
| 1135 | chg_irq_from_exton; |
| 1136 | scs-int-active-high; |
| 1137 | battery { |
| 1138 | compatible = "asr,pm802-bat"; |
| 1139 | status = "disabled"; |
| 1140 | |
| 1141 | online-gpadc = <1>; |
| 1142 | temperature-gpadc = <1>; |
| 1143 | |
| 1144 | hi-volt-online = <1150>; /* mV */ |
| 1145 | lo-volt-online = <20>; /* mV */ |
| 1146 | hi-volt-temp = <1150>; /* mV */ |
| 1147 | lo-volt-temp = <200>; /* mV */ |
| 1148 | |
| 1149 | sw-fg-use-ntc; |
| 1150 | full-capacity = <2050>; /* mAh */ |
| 1151 | r1-resistor = <40>; /* mohm */ |
| 1152 | r2-resistor = <30>; /* mohm */ |
| 1153 | rs-resistor = <120>; /* mohm */ |
| 1154 | roff-resistor = <0>; /* mohm */ |
| 1155 | roff-initial-resistor = <0>; /* mohm */ |
| 1156 | |
| 1157 | times-in-zero-degree = <1>; |
| 1158 | offset-in-zero-degree = <0>; |
| 1159 | |
| 1160 | times-in-ten-degree = <2>; |
| 1161 | offset-in-ten-degree = <100>; |
| 1162 | |
| 1163 | power-off-threshold = <3350>; /* mV */ |
| 1164 | safe-power-off-threshold = <3200>; /* mV */ |
| 1165 | |
| 1166 | online-gp-bias-curr = <11>; /* uA */ |
| 1167 | |
| 1168 | soc-ramp-up-interval = <150>; /* s */ |
| 1169 | /* choose -20C, 0C, 10C, 40C, 45C, 55C as threshold */ |
| 1170 | tbat-threshold = <20 0 10 40 45 55>; /* ohm */ |
| 1171 | ntc-table-size = <88>; |
| 1172 | stop-chg-for-vbatmeas; |
| 1173 | /* -24C, -23C, ..., 62C, 63C */ |
| 1174 | ntc-table = < |
| 1175 | 89680 85130 80840 76790 72970 69360 65960 62740 |
| 1176 | 59700 56830 54130 51530 49100 46800 44610 42550 |
| 1177 | 40590 38730 36970 35300 33710 32210 30780 29420 |
| 1178 | 28130 26910 25750 24640 23590 22580 21630 20720 |
| 1179 | 19860 19030 18250 17500 16790 16110 15460 14840 |
| 1180 | 14250 13690 13150 12640 12150 11680 11230 10800 |
| 1181 | 10390 10000 9620 9270 8920 8590 8280 7980 |
| 1182 | 7690 7410 7150 6890 6650 6410 6190 5970 |
| 1183 | 5770 5570 5380 5190 5020 4850 4680 4530 |
| 1184 | 4380 4230 4100 3960 3830 3710 3590 3480 |
| 1185 | 3370 3260 3160 3060 2960 2870 2780 2700 |
| 1186 | >; |
| 1187 | }; |
| 1188 | usb { |
| 1189 | status = "disabled"; |
| 1190 | vbus_gpio = <0xff>; /* set_vbus */ |
| 1191 | id-gpadc = <0xff>; /* usb-id */ |
| 1192 | vchg-from-exton = <1>; |
| 1193 | vbus-detect = <1>; /* vbus-irq */ |
| 1194 | get-vbus = <1>; /* get-vbus */ |
| 1195 | }; |
| 1196 | }; |
| 1197 | pmic6: pm803@30 { |
| 1198 | compatible = "asr,pm803"; |
| 1199 | reg = <0x30>; |
| 1200 | interrupts = <4>; |
| 1201 | interrupt-parent = <&intc>; |
| 1202 | interrupt-controller; |
| 1203 | #interrupt-cells = <1>; |
| 1204 | chg_irq_from_exton; |
| 1205 | scs-int-active-high; |
| 1206 | battery { |
| 1207 | compatible = "asr,pm803-bat"; |
| 1208 | status = "disabled"; |
| 1209 | |
| 1210 | online-gpadc = <1>; |
| 1211 | temperature-gpadc = <1>; |
| 1212 | |
| 1213 | hi-volt-online = <1150>; /* mV */ |
| 1214 | lo-volt-online = <20>; /* mV */ |
| 1215 | hi-volt-temp = <1150>; /* mV */ |
| 1216 | lo-volt-temp = <200>; /* mV */ |
| 1217 | |
| 1218 | sw-fg-use-ntc; |
| 1219 | full-capacity = <2050>; /* mAh */ |
| 1220 | r1-resistor = <40>; /* mohm */ |
| 1221 | r2-resistor = <30>; /* mohm */ |
| 1222 | rs-resistor = <120>; /* mohm */ |
| 1223 | roff-resistor = <0>; /* mohm */ |
| 1224 | roff-initial-resistor = <0>; /* mohm */ |
| 1225 | |
| 1226 | times-in-zero-degree = <1>; |
| 1227 | offset-in-zero-degree = <0>; |
| 1228 | |
| 1229 | times-in-ten-degree = <2>; |
| 1230 | offset-in-ten-degree = <100>; |
| 1231 | |
| 1232 | power-off-threshold = <3350>; /* mV */ |
| 1233 | safe-power-off-threshold = <3200>; /* mV */ |
| 1234 | |
| 1235 | online-gp-bias-curr = <11>; /* uA */ |
| 1236 | |
| 1237 | soc-ramp-up-interval = <150>; /* s */ |
| 1238 | /* choose -20C, 0C, 10C, 40C, 45C, 55C as threshold */ |
| 1239 | tbat-threshold = <20 0 10 40 45 55>; /* ohm */ |
| 1240 | ntc-table-size = <88>; |
| 1241 | stop-chg-for-vbatmeas; |
| 1242 | /* -24C, -23C, ..., 62C, 63C */ |
| 1243 | ntc-table = < |
| 1244 | 89680 85130 80840 76790 72970 69360 65960 62740 |
| 1245 | 59700 56830 54130 51530 49100 46800 44610 42550 |
| 1246 | 40590 38730 36970 35300 33710 32210 30780 29420 |
| 1247 | 28130 26910 25750 24640 23590 22580 21630 20720 |
| 1248 | 19860 19030 18250 17500 16790 16110 15460 14840 |
| 1249 | 14250 13690 13150 12640 12150 11680 11230 10800 |
| 1250 | 10390 10000 9620 9270 8920 8590 8280 7980 |
| 1251 | 7690 7410 7150 6890 6650 6410 6190 5970 |
| 1252 | 5770 5570 5380 5190 5020 4850 4680 4530 |
| 1253 | 4380 4230 4100 3960 3830 3710 3590 3480 |
| 1254 | 3370 3260 3160 3060 2960 2870 2780 2700 |
| 1255 | >; |
| 1256 | }; |
| 1257 | usb { |
| 1258 | status = "disabled"; |
| 1259 | vbus_gpio = <0xff>; /* set_vbus */ |
| 1260 | id-gpadc = <0xff>; /* usb-id */ |
| 1261 | vchg-from-exton = <1>; |
| 1262 | vbus-detect = <1>; /* vbus-irq */ |
| 1263 | get-vbus = <1>; /* get-vbus */ |
| 1264 | }; |
| 1265 | }; |
| 1266 | }; |
| 1267 | }; |
| 1268 | }; |
| 1269 | |
| 1270 | vcc_sdh1: sd-regulator { |
| 1271 | compatible = "regulator-fixed"; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 1272 | /*pinctrl-names = "default";*/ |
| 1273 | /*pinctrl-0 = <&sd_ldo_en>;*/ |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 1274 | regulator-name = "SDH1 VCC"; |
| 1275 | regulator-min-microvolt = <3300000>; |
| 1276 | regulator-max-microvolt = <3300000>; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 1277 | /* gpio = <&gpio 45 0>;*/ |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 1278 | enable-active-high; |
| 1279 | status = "okay"; |
| 1280 | }; |
| 1281 | |
| 1282 | asr-rfkill { |
| 1283 | compatible = "asr,asr-rfkill"; |
| 1284 | pinctrl-names = "off", "on"; |
| 1285 | pinctrl-0 = <&sdh1_pmx_pd_rst_off>; |
| 1286 | pinctrl-1 = <&sdh1_pmx_pd_rst_on>; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 1287 | sd-host = <&sdh0>; |
| 1288 | //pd-gpio = <&gpio 90 0>; |
| 1289 | rst-gpio = <&gpio 90 0>; |
| 1290 | |
| 1291 | /*3v3-ldo-gpio = <&gpio 8 0>;*/ |
| 1292 | /*edge-wakeup-gpio = <&gpio 10 0>;*/ |
| 1293 | status = "okay"; |
| 1294 | }; |
| 1295 | |
| 1296 | mbtk-sdh{ |
| 1297 | compatible = "mbtk,mbtk-sdh"; |
| 1298 | pinctrl-names = "off", "on"; |
| 1299 | pinctrl-0 = <&mbtk_sdh_pmx_off>; |
| 1300 | pinctrl-1 = <&mbtk_sdh_pmx_on>; |
| 1301 | sd-host = <&sdh1>; |
| 1302 | 1v8-ldo-gpio = <&gpio 123 0>; |
| 1303 | host-wakeup-wlan-gpio = <&gpio 127 0>; |
| 1304 | wlan_en_gpio = <&gpio 125 0>; |
| 1305 | status = "okay"; |
| 1306 | }; |
| 1307 | |
| 1308 | asr-gps { |
| 1309 | compatible = "asr,asr-gnss"; |
| 1310 | pinctrl-names = "default"; |
| 1311 | pinctrl-0 = <&gnss_clk_on>; |
| 1312 | enable_vctcxo_out1; |
| 1313 | host-wakeup-gnss-gpio = <&gpio 47 0>; |
| 1314 | /*gnss-wakeup-host-gpio = <&gpio 47 0>;*/ |
| 1315 | rst-gpio = <&gpio 45 0>; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 1316 | status = "okay"; |
| 1317 | }; |
| 1318 | |
| 1319 | pcie-rfkill { |
| 1320 | compatible = "mrvl,pcie-rfkill"; |
| 1321 | pinctrl-names = "off", "on"; |
| 1322 | pinctrl-0 = <&pcie_pmx_pd_rst_off>; |
| 1323 | pinctrl-1 = <&pcie_pmx_pd_rst_on>; |
| 1324 | rst-gpio = <&gpio 42 0>; |
| 1325 | 3v3-ldo-gpio = <&gpio 24 0>; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 1326 | status = "disabled"; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 1327 | }; |
| 1328 | |
| 1329 | sound { |
| 1330 | compatible = "ASRMICRO,asrmicro-snd-card"; |
| 1331 | ssp-controllers = <&ssp_dai1>; |
| 1332 | }; |
| 1333 | |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 1334 | asr-adc { |
| 1335 | compatible = "asr,adc"; |
| 1336 | //pinctrl-names = "default"; |
| 1337 | //pinctrl-0 = <&pin_func_work>; |
| 1338 | status = "okay"; |
| 1339 | }; |
| 1340 | |
| 1341 | #if 0 |
| 1342 | |
| 1343 | mbtk_PlatIrq{ |
| 1344 | compatible = "mbtk,plat-irq"; |
| 1345 | pinctrl-names = "sc_irq0", "sc_irq1", "sc_irq2", "sc_irq3"; |
| 1346 | |
| 1347 | pinctrl-0 = <&sc_ext_int0>; |
| 1348 | pinctrl-1 = <&sc_ext_int1>; |
| 1349 | pinctrl-2 = <&sc_ext_int2>; |
| 1350 | pinctrl-3 = <&sc_ext_int3>; |
| 1351 | status = "okay"; |
| 1352 | }; |
| 1353 | |
| 1354 | #else |
| 1355 | |
| 1356 | mbtk_PlatIrq{ |
| 1357 | compatible = "mbtk,plat-irq"; |
| 1358 | pinctrl-names = "default", "sleep"; |
| 1359 | pinctrl-0 = <&mbtk_plat_irq_func>; |
| 1360 | pinctrl-1 = <&mbtk_plat_irq_func_sleep>; |
| 1361 | gpio_irq0 = <&gpio 21 0>; |
| 1362 | gpio_irq1 = <&gpio 22 0>; |
| 1363 | gpio_irq2 = <&gpio 23 0>; |
| 1364 | gpio_irq3 = <&gpio 24 0>; |
| 1365 | status = "okay"; |
| 1366 | }; |
| 1367 | |
| 1368 | #endif |
| 1369 | |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 1370 | ecall { |
| 1371 | compatible = "asr,ecall-event"; |
| 1372 | pinctrl-names = "default"; |
| 1373 | pinctrl-0 = <&ecall_pmx_func>; |
| 1374 | gpio-auto-ecall = <8>; |
| 1375 | gpio-manual-ecall = <9>; |
| 1376 | status = "disabled"; |
| 1377 | }; |
| 1378 | |
| 1379 | usim1: usim1 { |
| 1380 | compatible = "asr,usim1"; |
| 1381 | pinctrl-names = "default", "sleep"; |
| 1382 | pinctrl-0 = <&usim1_pmx_func>; |
| 1383 | pinctrl-1 = <&usim1_pmx_func_sleep>; |
yq.wang | 107f986 | 2025-05-12 15:44:50 +0800 | [diff] [blame] | 1384 | edge_detect_gpio = <119>; /* GPIO19: SIM detect pin */ |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 1385 | status = "okay"; |
| 1386 | }; |
| 1387 | /* set okay for this node if usim2 is needed */ |
| 1388 | usim2: usim2 { |
| 1389 | compatible = "asr,usim2"; |
| 1390 | pinctrl-names = "default", "sleep"; |
| 1391 | pinctrl-0 = <&usim2_pmx_func>; |
| 1392 | pinctrl-1 = <&usim2_pmx_func_sleep>; |
| 1393 | edge_detect_gpio = <44>; /* GPIO44: SIM detect pin */ |
| 1394 | #ifdef CONFIG_ASR_DSDS |
| 1395 | status = "okay"; |
| 1396 | #else |
| 1397 | status = "disabled"; |
| 1398 | #endif |
| 1399 | }; |
| 1400 | gpio_keys { |
| 1401 | compatible = "gpio-keys"; |
| 1402 | #address-cells = <1>; |
| 1403 | #size-cells = <0>; |
| 1404 | /* autorepeat; */ |
| 1405 | pinctrl-names = "default"; |
| 1406 | pinctrl-0 = <&gpiokey_pmx_func>; |
| 1407 | button@1 { |
| 1408 | label = "qrcode-key"; |
| 1409 | linux,code = <139>; /* KEY_MENU, refer to linux/input.h */ |
| 1410 | /* NOTE: |
| 1411 | * We use the FORCE DOWNLOAD key to implement the qrcode key in DKB. |
| 1412 | * Customer SHOULD change it to any other gpios. |
| 1413 | * Because user may do the misoperation that |
| 1414 | * powerup with FDL key pressed, |
| 1415 | * then the borad will enter force download mode. |
| 1416 | */ |
| 1417 | gpios = <&gpio 9 1>; |
| 1418 | gpio-key,wakeup; |
| 1419 | }; |
| 1420 | }; |
| 1421 | |
| 1422 | audio_pa { |
| 1423 | compatible = "asrmicro,audio-pa"; |
| 1424 | pinctrl-names = "default"; |
| 1425 | pinctrl-0 = <&audio_pa_pmx_func>; |
| 1426 | pa-gpio = <&gpio 14 0>; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 1427 | status = "disabled"; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 1428 | }; |
b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 1429 | mbtk_GpioWakeUp { |
| 1430 | compatible = "mbtk,GpioWakeUp"; |
| 1431 | pinctrl-names = "default", "sleep"; |
| 1432 | pinctrl-0 = <&wake_pmx_func &wake_pmx_func1>; |
| 1433 | pinctrl-1 = <&wake_pmx_func_sleep>; |
| 1434 | wakeup-in-gpio = <&gpio 118 0>; |
| 1435 | wakeup-out-gpio = <&gpio 117 0>; |
| 1436 | status = "okay"; |
| 1437 | }; |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 1438 | |
hong.liu | f241688 | 2025-05-23 20:41:06 -0700 | [diff] [blame] | 1439 | |
| 1440 | dtsleds{ |
| 1441 | compatible = "gpio-leds"; |
| 1442 | pinctrl-names = "default"; |
| 1443 | pinctrl-0 = <&led_pmx_func1>; |
| 1444 | status = "okay"; |
| 1445 | led0{ |
| 1446 | label = "red"; |
| 1447 | gpios = <&gpio 8 0>; |
| 1448 | linux,default-trigger = "pattern"; |
| 1449 | led-pattern = "100:100:100"; |
| 1450 | default-state = "on"; |
| 1451 | |
| 1452 | }; |
| 1453 | |
| 1454 | // led1{ |
| 1455 | // label = "blue"; |
| 1456 | // gpios = <&gpio 99 0>; |
| 1457 | // linux,default-trigger = "timer"; |
| 1458 | // timer-delay-on = <100>; |
| 1459 | // timer-delay-off = <100>; |
| 1460 | // brightness-levels = <100>; |
| 1461 | // brightness-max = <100>; |
| 1462 | // default-state = "on"; |
| 1463 | // }; |
| 1464 | |
| 1465 | }; |
| 1466 | |
b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 1467 | audio_regs { |
| 1468 | compatible = "ASRMICRO,audio-registers"; |
| 1469 | reg = <0xD4050044 0x4>; |
| 1470 | status = "okay"; |
| 1471 | }; |
| 1472 | |
| 1473 | nz3-slic { |
| 1474 | compatible = "asr,nz3-slic"; |
| 1475 | pinctrl-names = "default", "sleep"; |
| 1476 | pinctrl-0 = <&slic_pmx_func1 &slic_pmx_func2>; |
| 1477 | pinctrl-1 = <&slic_pmx_func1_sleep &slic_pmx_func2>; |
| 1478 | rst-gpio = <&gpio 21 0>; |
| 1479 | edge-wakeup-gpio = <&gpio 20 0>; |
| 1480 | vdd-3v3-gpio = <&gpio 127 0>; |
| 1481 | status = "disabled"; |
| 1482 | }; |
| 1483 | microsemi-slic { |
| 1484 | compatible = "asr,microsemi-slic"; |
| 1485 | pinctrl-names = "default", "sleep"; |
| 1486 | pinctrl-0 = <&slic_pmx_func1>; |
| 1487 | pinctrl-1 = <&slic_pmx_func1_sleep>; |
| 1488 | edge-wakeup-gpio = <&gpio 20 0>; |
| 1489 | vdd-3v3-gpio = <&gpio 127 0>; |
| 1490 | status = "disabled"; |
| 1491 | }; |
| 1492 | maxlinear-slic { |
| 1493 | compatible = "asr,maxlinear-slic"; |
| 1494 | pinctrl-names = "default", "sleep"; |
| 1495 | pinctrl-0 = <&slic_pmx_func1 &slic_pmx_func2>; |
| 1496 | pinctrl-1 = <&slic_pmx_func1_sleep &slic_pmx_func2>; |
| 1497 | rst-gpio = <&gpio 21 0>; |
| 1498 | edge-wakeup-gpio = <&gpio 20 0>; |
| 1499 | vdd-3v3-gpio = <&gpio 127 0>; |
| 1500 | status = "disabled"; |
| 1501 | }; |
| 1502 | /* deprecated, move to mfpr@d401e000 |
| 1503 | lpm-board-cfg { |
| 1504 | compatible = "asr,lpm-board-cfg"; |
| 1505 | wakeup-state-d1pp = <0x1>; |
| 1506 | udr-mfpr-config = <0x1B0 0xA040 0x0 |
| 1507 | 0x1B4 0xA040 0x0>; |
| 1508 | }; |
| 1509 | */ |
| 1510 | }; |
| 1511 | #ifdef CONFIG_ASR_DSDS |
| 1512 | #include "asr_pm802_2usim.dtsi" |
| 1513 | #include "88pm805.dtsi" |
| 1514 | #include "asr_pm803_2usim.dtsi" |
| 1515 | #else |
| 1516 | #include "asr_pm802.dtsi" |
| 1517 | #include "88pm805.dtsi" |
| 1518 | #include "asr_pm803.dtsi" |
| 1519 | #endif |
| 1520 | |
| 1521 | #ifdef CONFIG_AB_SYSTEM |
| 1522 | #include "asr1806_ab_flash_layout.dtsi" |
| 1523 | #else |
| 1524 | #include "asr1806_flash_layout.dtsi" |
| 1525 | #endif |