| b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 1 | /******************************************************************************
|
| 2 | *
|
| 3 | * Name: ip175d.h
|
| 4 | *
|
| 5 | * Description: SIOC data structure + switch Header
|
| 6 | *
|
| 7 | * Copyright: (c) 2005-2050 IC Plus Corp.
|
| 8 | * All rights reserved.
|
| 9 | *
|
| 10 | *******************************************************************************/
|
| 11 | #ifndef _IP175D_H_
|
| 12 | #define _IP175D_H_
|
| 13 |
|
| 14 | #ifndef SIOCDEVPRIV
|
| 15 | #define SIOCDEVPRIV 0x89f0
|
| 16 | #define SIOCVLAN SIOCDEVPRIV+0x0
|
| 17 | #define SIOCQOS SIOCDEVPRIV+0x1
|
| 18 | #define SIOCMIRROR SIOCDEVPRIV+0x2
|
| 19 | #define SIOCDATARATE SIOCDEVPRIV+0x3
|
| 20 | #define SIOCLUT SIOCDEVPRIV+0x4
|
| 21 | #define SIOCACL SIOCDEVPRIV+0x5
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| 22 |
|
| 23 | #define SIOCIGMPENT SIOCDEVPRIV+0xe
|
| 24 | #define SIOCHWIGMP SIOCDEVPRIV+0xf
|
| 25 | #endif
|
| 26 | /*
|
| 27 | #ifndef u32
|
| 28 | typedef unsigned long u32;
|
| 29 | #endif
|
| 30 | #ifndef u16
|
| 31 | typedef unsigned short u16;
|
| 32 | #endif
|
| 33 | #ifndef u8
|
| 34 | typedef unsigned char u8;
|
| 35 | #endif
|
| 36 | */
|
| 37 | #define CMD_WRITE 0x10
|
| 38 | #define CMD_READ 0x00
|
| 39 |
|
| 40 | #define MAX_PORT_NUM 6
|
| 41 | #define MAX_VLAN_NUM 16
|
| 42 | #define TBASE_VLAN_NUM MAX_VLAN_NUM
|
| 43 | #define PBASE_VLAN_NUM 6
|
| 44 |
|
| 45 | struct _VLAN_entry
|
| 46 | {
|
| 47 | unsigned char valid; //0->disable !0->Enable
|
| 48 | unsigned int VID; //1~4093
|
| 49 | unsigned char FID; //0~15
|
| 50 | unsigned char member; // bit[5:0] -> P5~P0
|
| 51 | unsigned char AddTag; // bit[5:0] -> P5~P0
|
| 52 | unsigned char RmvTag; // bit[5:0] -> P5~P0
|
| 53 | unsigned char qos_enable;
|
| 54 | unsigned char queue;
|
| 55 | // unsigned int PVID; //1~4093
|
| 56 | };
|
| 57 |
|
| 58 | #define VLAN_CMD_TBASE 0x01
|
| 59 | #define VLAN_CMD_PBASE 0x00
|
| 60 | #define VLAN_CMD_MIX 0x02
|
| 61 |
|
| 62 | #define VLAN_MODE_ALL_TBASE 0x3f
|
| 63 | #define VLAN_MODE_ALL_PBASE 0x00
|
| 64 |
|
| 65 | #define VLAN_CMD_OKMASK 0x3f
|
| 66 | #define VLAN_CMD_OK 0x80
|
| 67 |
|
| 68 | struct _VLAN_setting
|
| 69 | {
|
| 70 | unsigned char cmd; //bit4->1:write 0:read , bit0->1:TagVLAN 0:PortBaseVLAN
|
| 71 | unsigned char vmode; //bit[5:0] in write mode:0->PortBaseVLAN !0->TagBase VLAN
|
| 72 | unsigned char cmode; //bit[5:0] in vlan mode: 0 - VID classification 1 - PVID classification
|
| 73 | unsigned int PVID[MAX_PORT_NUM];
|
| 74 | struct _VLAN_entry VLAN_entry[MAX_VLAN_NUM];
|
| 75 | };
|
| 76 |
|
| 77 |
|
| 78 | #define QoS_QUEUE_0 0x00
|
| 79 | #define QoS_QUEUE_1 0x01
|
| 80 | #define QoS_QUEUE_2 0x02
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| 81 | #define QoS_QUEUE_3 0x03
|
| 82 | #define QoS_MAX_QUEUE 4
|
| 83 | struct _protocol_entry
|
| 84 | {
|
| 85 | unsigned char enable; // 0: disable !0: enable
|
| 86 | unsigned short port; // TCP/UDP port number
|
| 87 | unsigned char queue; // queue0~3
|
| 88 | };
|
| 89 |
|
| 90 | struct _range_entry
|
| 91 | {
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| 92 | unsigned char enable; // 0: disable !0: enable
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| 93 | unsigned short s_port; // TCP/UDP port range start number
|
| 94 | unsigned short e_port; // TCP/UDP port range end number
|
| 95 | unsigned char queue; // queue0~3
|
| 96 | };
|
| 97 |
|
| 98 | #define QoS_CLASS_PORT0_ENABLE 0x1
|
| 99 | #define QoS_CLASS_PORT1_ENABLE 0x2
|
| 100 | #define QoS_CLASS_PORT2_ENABLE 0x4
|
| 101 | #define QoS_CLASS_PORT3_ENABLE 0x8
|
| 102 | #define QoS_CLASS_PORT4_ENABLE 0x10
|
| 103 | #define QoS_CLASS_PORT5_ENABLE 0x20
|
| 104 | #define QoS_CLASS_PORT_ALL_ENABLE 0x3f
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| 105 |
|
| 106 | #define QoS_CLASS_COS0_ENABLE 0x1
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| 107 | #define QoS_CLASS_COS1_ENABLE 0x2
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| 108 | #define QoS_CLASS_COS2_ENABLE 0x4
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| 109 | #define QoS_CLASS_COS3_ENABLE 0x8
|
| 110 | #define QoS_CLASS_COS4_ENABLE 0x10
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| 111 | #define QoS_CLASS_COS5_ENABLE 0x20
|
| 112 | #define QoS_CLASS_COS_ALL_ENABLE 0x3f
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| 113 |
|
| 114 | #define QoS_CLASS_ACL_ENABLE 0x1
|
| 115 | #define QoS_CLASS_VLAN_ENABLE 0x2
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| 116 | #define QoS_CLASS_LP_ENABLE 0x4
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| 117 | //#define QoS_CLASS_PORT_ALL_ENABLE 0x8
|
| 118 | //#define QoS_CLASS_COS_ALL_ENABLE 0x10
|
| 119 |
|
| 120 | #define QoS_TYPE_DISABLE 0x00
|
| 121 | #define QoS_TYPE_SOURCE 0x01
|
| 122 | #define QoS_TYPE_DESTINATION 0x02
|
| 123 | #define QoS_TYPE_SOURCEnDEST 0x03
|
| 124 |
|
| 125 | #define QoS_MODE_WRR 0x00
|
| 126 | #define QoS_MODE_WFQ 0x01
|
| 127 | #define QoS_MODE_SPM 0x02
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| 128 | #define QoS_MODE_SP 0x03
|
| 129 | #define QoS_MODE_HIGH_PASS QoS_MODE_SP
|
| 130 |
|
| 131 | #define MAX_PROTOCOL_NUM 4
|
| 132 | #define MAX_RANGE_NUM 2
|
| 133 | #define MAX_VLAN_PRI_NUM 8
|
| 134 | #define MAX_COS_PRI_NUM 64
|
| 135 |
|
| 136 | struct _QoS_setting
|
| 137 | {
|
| 138 | unsigned char cmd; //bit4->1:write 0:read
|
| 139 | unsigned char enable; // 0:disable !0:enable
|
| 140 | unsigned char pri_port_enable;//bit0~5 => for port0~5 1:enable 0:disable port-based priority
|
| 141 | unsigned char pri_cos_enable;//bit0~5 => for port0~5 1:enable 0:disable CoS priority
|
| 142 | /* priority_class:priority classification.for each bit 1:enable 0:disable
|
| 143 | * bit0:user-defined(ACL) priority/VLAN table priority
|
| 144 | * bit1:VLAN priority
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| 145 | * bit2:Logical-port priority
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| 146 | * bit3:port-based priority all port on/off
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| 147 | * bit4:COS-based priority all port on/off
|
| 148 | */
|
| 149 | unsigned char priority_class;
|
| 150 | unsigned char port_based_queue[MAX_PORT_NUM];
|
| 151 | unsigned char vlan_queue[MAX_VLAN_PRI_NUM];
|
| 152 | unsigned char cos_queue[MAX_COS_PRI_NUM];
|
| 153 | unsigned char type; // 0:disable 1:SA 2:DA 3:DA+SA
|
| 154 | unsigned char mode; // 0:WRR 3:High Priority first
|
| 155 | unsigned int queue_weight[QoS_MAX_QUEUE];//weight for q0(low)~q3(high) (unit:packet)
|
| 156 | unsigned int queue_rate[QoS_MAX_QUEUE];//WFQ:rate for q0(low)~q3(high) (unit:32 Kbps)
|
| 157 | struct _protocol_entry protocol[MAX_PROTOCOL_NUM];
|
| 158 | struct _range_entry range[MAX_RANGE_NUM];
|
| 159 | };
|
| 160 |
|
| 161 | #define MAC_LUT_ENABLE 0x1
|
| 162 | #define MAC_LUT_DISABLE 0x0
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| 163 |
|
| 164 | #define LUT_MAC_UNICAST 0x0
|
| 165 | #define LUT_MAC_MULTICAST 0x1
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| 166 | #define LUT_IGMP_MULTICAST 0x2
|
| 167 |
|
| 168 | #define LUT_STATIC_ENTRY 0x2
|
| 169 |
|
| 170 | #define MAC_LUT_PRI_DMAC 0x1
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| 171 | #define MAC_LUT_PRI_SMAC 0x2
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| 172 | #define MAC_LUT_PRI_BOTH 0x3
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| 173 |
|
| 174 | #define MAC_LUT_FILTER_SMAC 0x1
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| 175 | #define MAC_LUT_FILTER_IGNORE_VLAN 0x2
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| 176 | #define MAC_LUT_FILTER_MIRROR 0x3
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| 177 |
|
| 178 | struct _MAC_LUT_entry
|
| 179 | {
|
| 180 | unsigned char valid;// in unicast: set 1 for static entry, in mcast& igmp: set 1 for valid.
|
| 181 | unsigned char type;// 0:unicast 1:multicast 2:IGMP
|
| 182 | unsigned char entry;//bit 0~1: entry num(0~3)
|
| 183 | unsigned char fid;//0~15
|
| 184 | unsigned char MAC[6];
|
| 185 | unsigned char age;
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| 186 | unsigned char pri_function;//1:match DMAC 2:match SMAC 3:match either DMAC or SMAC
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| 187 | //filter_function - 1:drop if SA match 2:ignore VLAN member 3:copy to mirror port if DA match
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| 188 | unsigned char filter_function;
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| 189 | unsigned char queue;//0~3
|
| 190 | unsigned char phy_port;//unicast- 0:drop 1~6: forward to port0~5
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| 191 | //multicast- bit0~5: forward to port0~5 enable/disable
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| 192 | //IGMP - bit0~5: forward to port0~5 enable/disable
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| 193 | unsigned char timeout[MAX_PORT_NUM];
|
| 194 | };
|
| 195 |
|
| 196 | #define LUT_2K 0x0
|
| 197 | #define LUT_1K_1K 0x1
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| 198 |
|
| 199 | struct _LUT_setting
|
| 200 | {
|
| 201 | unsigned char lut_mode;
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| 202 | unsigned char cmd;
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| 203 | struct _MAC_LUT_entry lut_entry;
|
| 204 | };
|
| 205 |
|
| 206 | /*
|
| 207 | func:
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| 208 | bit 0 - HW IGMP snooping 1:en 0:dis
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| 209 | bit 1 - learn router port automatically 1:en 0:dis
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| 210 | bit 2 - learn router port even if sip=0.0.0.0 1:en 0:dis
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| 211 | bit 3 - broadcast "report pkt" to all ports 1:en 0:dis
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| 212 | bit 4 - discard "leave pkt" 1:en 0:dis
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| 213 | bit 5~6 - filter mode for unknown IP multicast data 0:discard 1:to CPU 2:flood pkt 3:to router port
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| 214 | bit 7 - broadcast IP multicast control pkt 1:en 0:dis
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| 215 | bit 8 - broadcast unknown IGMP pkt 1:en 0:dis
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| 216 | bit 9 - IP multicast data pkt forward to group member 1:en 0:dis
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| 217 | ports & router ports
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| 218 | bit10 - Fast leave 1:en 0:dis
|
| 219 | */
|
| 220 | void igmp_set_func(u16 func);
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| 221 | u16 igmp_get_func(void);
|
| 222 |
|
| 223 | /*
|
| 224 | ports:
|
| 225 | bit 0~5 - Default router ports,each bit refers to each port.
|
| 226 | */
|
| 227 | void igmp_set_router_port(u8 ports);
|
| 228 | u8 igmp_get_router_port(void);
|
| 229 |
|
| 230 | /*
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| 231 | Set timeout for router ports
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| 232 | timeout = timeout unit * timeout scale(unit:s)
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| 233 | bit 0~5 - Set to 0.
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| 234 | bit 6~7 - timeout unit 0:1s 1:2s 2:4s 3:8s
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| 235 | bit 8~15- timeout scale
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| 236 | */
|
| 237 | void igmp_set_router_timeout(u16 timeout);
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| 238 | u16 igmp_get_router_timeout(void);
|
| 239 | /*
|
| 240 | Set timeout for group ports
|
| 241 | timeout = timeout unit * timeout scale(unit:s)
|
| 242 | bit 0~1 - timeout unit 0:1s 1:2s 2:4s 3:8s
|
| 243 | bit 8~15- timeout scale
|
| 244 | */
|
| 245 | void igmp_set_group_timeout(u16 timeout);
|
| 246 | u16 igmp_get_group_timeout(void);
|
| 247 |
|
| 248 | struct _IGMP_setting
|
| 249 | {
|
| 250 | u8 cmd;
|
| 251 | u16 func;
|
| 252 | u8 router_port;
|
| 253 | u16 rp_timeout;
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| 254 | u16 group_timeout;
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| 255 | };
|
| 256 | #define IGMP_DEL_ENTRY 0
|
| 257 | #define IGMP_ADD_ENTRY 1
|
| 258 | struct _IGMP_entry
|
| 259 | {
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| 260 | u8 cmd;
|
| 261 | u8 type;
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| 262 | u8 mac[6];
|
| 263 | u8 port;
|
| 264 | };
|
| 265 |
|
| 266 | #define ACL_MAX_MULTI_ENTRY_NUM 8
|
| 267 | #define ACL_MAX_MACF_NUM 2048
|
| 268 |
|
| 269 | #define ACL_FILTER_PHYPORT_ENABLE 0x1
|
| 270 | #define ACL_FILTER_MAC_ENABLE 0x2
|
| 271 | #define ACL_FILTER_ETHTYPE_ENABLE 0x4
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| 272 | #define ACL_FILTER_IP_PROTOCOL_ENABLE 0x8
|
| 273 | #define ACL_FILTER_VLAN_ENABLE 0x10
|
| 274 | #define ACL_FILTER_COS_ENABLE 0x20
|
| 275 | #define ACL_FILTER_IP_ADDRESS_ENABLE 0x40
|
| 276 | #define ACL_FILTER_LOGICAL_PORT_ENABLE 0x80
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| 277 |
|
| 278 | #define ACL_ACTION_RATE_CONTROL 0x1
|
| 279 | #define ACL_ACTION_MONITOR_RATE 0x2
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| 280 | #define ACL_ACTION_QUEUE_SET 0x3
|
| 281 | #define ACL_ACTION_MIRROR_PORT 0x4
|
| 282 | #define ACL_ACTION_FORWARD_CPU 0x5
|
| 283 | #define ACL_ACTION_DROP 0x6
|
| 284 | #define ACL_ACTION_FORWARD 0x7
|
| 285 |
|
| 286 | #define ACL_QOS_QUEUE_DIABLE 0x0
|
| 287 | #define ACL_QOS_QUEUE0 0x4
|
| 288 | #define ACL_QOS_QUEUE1 0x5
|
| 289 | #define ACL_QOS_QUEUE2 0x6
|
| 290 | #define ACL_QOS_QUEUE3 0x7
|
| 291 |
|
| 292 | #define ACL_FILTER_IP_MAC_DISABLE 0x0
|
| 293 | #define ACL_FILTER_IP_SINGAL_SOURCE 0x1
|
| 294 | #define ACL_FILTER_IP_SINGAL_DESTINATION 0x2
|
| 295 | #define ACL_FILTER_IP_SINGAL_BOTH 0x3
|
| 296 | #define ACL_FILTER_IP_RANGE_SOURCE 0x4
|
| 297 | #define ACL_FILTER_IP_RANGE_DESTINATION 0x5
|
| 298 | #define ACL_FILTER_IP_RANGE_BOTH 0x6
|
| 299 | #define ACL_FILTER_MAC_SMAC_ENABLE 0x7
|
| 300 | #define ACL_FILTER_MAC_DMAC_ENABLE 0x8
|
| 301 | #define ACL_FILTER_MAC_BOTH_ENABLE 0x9
|
| 302 |
|
| 303 | #define ACL_PHY_PORT0_ENABLE 0x1
|
| 304 | #define ACL_PHY_PORT1_ENABLE 0x2
|
| 305 | #define ACL_PHY_PORT2_ENABLE 0x4
|
| 306 | #define ACL_PHY_PORT3_ENABLE 0x8
|
| 307 | #define ACL_PHY_PORT4_ENABLE 0x10
|
| 308 | #define ACL_PHY_PORT_ALL_ENABLE 0x1f
|
| 309 |
|
| 310 | /* for logical port protocol */
|
| 311 | #define ACL_FILTER_LP_STCP 0x1
|
| 312 | #define ACL_FILTER_LP_SUDP 0x2
|
| 313 | #define ACL_FILTER_LP_DTCP 0x3
|
| 314 | #define ACL_FILTER_LP_DUDP 0x4
|
| 315 | #define ACL_FILTER_LP_STCP_DTCP 0x5
|
| 316 | #define ACL_FILTER_LP_STCP_DUDP 0x6
|
| 317 | #define ACL_FILTER_LP_SUDP_DTCP 0x7
|
| 318 | #define ACL_FILTER_LP_SUDP_DUDP 0x8
|
| 319 | #define ACL_FILTER_LP_RANGE_STCP 0x9
|
| 320 | #define ACL_FILTER_LP_RANGE_SUDP 0xa
|
| 321 | #define ACL_FILTER_LP_RANGE_SBOTH 0xb
|
| 322 | #define ACL_FILTER_LP_RANGE_DTCP 0xc
|
| 323 | #define ACL_FILTER_LP_RANGE_DUDP 0xd
|
| 324 | #define ACL_FILTER_LP_RANGE_DBOTH 0xe
|
| 325 | #define ACL_FILTER_LP_RANGE_BOTH_TCP 0xf
|
| 326 | #define ACL_FILTER_LP_RANGE_BOTH_UDP 0x10
|
| 327 | #define ACL_FILTER_LP_RANGE_BOTH_BOTH 0x11
|
| 328 |
|
| 329 | struct _ACL_MF_entry
|
| 330 | {
|
| 331 | unsigned char index;
|
| 332 | unsigned char valid;
|
| 333 | /* function:This is for enable/disable each field 1:enable 0:disable
|
| 334 | * bit0:physical port bit1:MAC
|
| 335 | * bit2:ethernet type bit3:IP protocol
|
| 336 | * bit4:VLAN bit5:DSCP/TOS
|
| 337 | * bit6:IP Address bit7:Logical port
|
| 338 | */
|
| 339 | unsigned char function;
|
| 340 | unsigned char port_num;
|
| 341 | unsigned short ether_type;
|
| 342 | unsigned char ip_protocol;
|
| 343 |
|
| 344 | unsigned char action;
|
| 345 | unsigned char queue;
|
| 346 | unsigned short rate;// unit:8Kbps
|
| 347 | unsigned int traffic_count;// unit:Bytes
|
| 348 | unsigned char cos_type;//Class of Service Number:VLAN/DSCP/TOS
|
| 349 | unsigned short ip_mac_type;//0:disable 1:source 2:desination 3:both - singal IP mode
|
| 350 | //4:source 5:destination 6:both - ranged IP mode
|
| 351 | //7:source 8:destination 9:both - MAC mode
|
| 352 | unsigned char logical_port_protocol;
|
| 353 |
|
| 354 | unsigned char sMAC[6];
|
| 355 | unsigned char dMAC[6];
|
| 356 | unsigned char sip[4];
|
| 357 | unsigned char eip[4];
|
| 358 | unsigned short s_port;
|
| 359 | unsigned short e_port;
|
| 360 | };
|
| 361 |
|
| 362 | #define ACL_FUNC_PHYPORT 0x1
|
| 363 | #define ACL_FUNC_LOGICPORT 0x2
|
| 364 | #define ACL_FUNC_MULTIFIELD 0x3
|
| 365 |
|
| 366 | #define ACL_LP_USER0_DROP 0x1
|
| 367 | #define ACL_LP_USER1_DROP 0x2
|
| 368 | #define ACL_LP_PREDEF0_DROP 0x4
|
| 369 | #define ACL_LP_PREDEF1_DROP 0x8
|
| 370 | #define ACL_LP_PREDEF2_DROP 0x10
|
| 371 | #define ACL_LP_PREDEF3_DROP 0x20
|
| 372 | #define ACL_LP_ALL_DROP 0x3f
|
| 373 |
|
| 374 | #define ACL_TYPE_DISABLE 0x00
|
| 375 | #define ACL_TYPE_SOURCE 0x01
|
| 376 | #define ACL_TYPE_DESTINATION 0x02
|
| 377 | #define ACL_TYPE_SOURCEnDEST 0x03
|
| 378 |
|
| 379 | struct _ACL_setting
|
| 380 | {
|
| 381 | unsigned char cmd;
|
| 382 | unsigned char function;
|
| 383 | unsigned char port_state[MAX_PORT_NUM];//bit0:Forwarding bit1:Learning 1:enable 0:disable
|
| 384 | unsigned char type;
|
| 385 | unsigned char lp_drop;
|
| 386 | struct _protocol_entry protocol[MAX_PROTOCOL_NUM];
|
| 387 | struct _range_entry range[MAX_RANGE_NUM];
|
| 388 |
|
| 389 | struct _ACL_MF_entry acl_mf_entry[ACL_MAX_MULTI_ENTRY_NUM];
|
| 390 | };
|
| 391 |
|
| 392 |
|
| 393 | #define MAX_MIRROR_PORT MAX_PORT_NUM
|
| 394 |
|
| 395 | #define MIRROR_MODE_RX 0x0
|
| 396 | #define MIRROR_MODE_TX 0x1
|
| 397 | #define MIRROR_MODE_TX2RX 0x2
|
| 398 | #define MIRROR_MODE_TXnRX 0x3
|
| 399 | struct _Mirror_setting
|
| 400 | {
|
| 401 | unsigned char cmd; // bit4->1:write 0:read
|
| 402 | unsigned char enable; // 0:disable !0:enable
|
| 403 | unsigned char mode; // 0:rx 1:tx 2:tx_to_rx 3:tx nad rx
|
| 404 | unsigned char tx_from;// mirror from which port's Tx (p0~p5)
|
| 405 | unsigned char rx_from;// mirror from which port's Rx (p0~p5)
|
| 406 | unsigned char to; // mirror to which port p0~p5
|
| 407 | };
|
| 408 |
|
| 409 | #define DATARATE_MAX_RATE 3124
|
| 410 | struct _Datarate_setting
|
| 411 | {
|
| 412 | unsigned char cmd; // bit4->1:write 0:read
|
| 413 | unsigned short tx_rate[MAX_PORT_NUM];// per unit is 32Kbps (0~3124 0:full speed)
|
| 414 | unsigned short rx_rate[MAX_PORT_NUM];// per unit is 32Kbps (0~3124 0:full speed)
|
| 415 | };
|
| 416 |
|
| 417 | //------------------------------------------------------------------------------
|
| 418 |
|
| 419 | struct ip175d_priv {
|
| 420 | void (*VLAN_Set)(struct _VLAN_setting *VLAN_setting);
|
| 421 | void (*VLAN_Query)(struct _VLAN_setting *VLAN_setting);
|
| 422 | void (*QoS_Set)(struct _QoS_setting *QoS_setting);
|
| 423 | void (*QoS_Query)(struct _QoS_setting *QoS_setting);
|
| 424 | void (*Mirror_Set)(struct _Mirror_setting *Mirror_setting);
|
| 425 | void (*Mirror_Query)(struct _Mirror_setting *Mirror_setting);
|
| 426 | void (*Datarate_Set)(struct _Datarate_setting *Datarate_setting);
|
| 427 | void (*Datarate_Query)(struct _Datarate_setting *Datarate_setting);
|
| 428 | void (*LUT_Set)(struct _LUT_setting *lut);
|
| 429 | void (*ACL_Set)(struct _ACL_setting *ACL_setting);
|
| 430 | void (*IGMP_Set)(struct _IGMP_setting *igmp);
|
| 431 | void (*IGMP_Query)(struct _IGMP_setting *igmp);
|
| 432 | void (*IGMP_Set_Entry)(struct _IGMP_entry *igmp);
|
| 433 | unsigned char (*IGMP_Query_Entry)(struct _IGMP_entry *igmp);
|
| 434 | };
|
| 435 |
|
| 436 | void VLAN_Set(struct _VLAN_setting *VLAN_setting);
|
| 437 | void VLAN_Query(struct _VLAN_setting *VLAN_setting);
|
| 438 | void QoS_Set(struct _QoS_setting *QoS_setting);
|
| 439 | void QoS_Query(struct _QoS_setting *QoS_setting);
|
| 440 | void Mirror_Set(struct _Mirror_setting *Mirror_setting);
|
| 441 | void Mirror_Query(struct _Mirror_setting *Mirror_setting);
|
| 442 | void Datarate_Set(struct _Datarate_setting *Datarate_setting);
|
| 443 | void Datarate_Query(struct _Datarate_setting *Datarate_setting);
|
| 444 | void LUT_Set(struct _LUT_setting *lut);
|
| 445 | void ACL_Set(struct _ACL_setting *ACL_setting);
|
| 446 | void IGMP_Set(struct _IGMP_setting *igmp);
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| 447 | void IGMP_Query(struct _IGMP_setting *igmp);
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| 448 | void IGMP_Set_Entry(struct _IGMP_entry *igmp);
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| 449 | unsigned char IGMP_Query_Entry(struct _IGMP_entry *igmp);
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| 450 |
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| 451 | //////////////////////////under is switch ip175d register map/////////////
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| 452 |
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| 453 | //PHY Control
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| 454 | #define PHY0 0
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| 455 | #define PHY_CTRL 0
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| 456 | #define PHY_STATUS 1
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| 457 | #define PHY_AN_ADV 4
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| 458 | #define PHY_AN_LPA 5
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| 459 |
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| 460 |
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| 461 | //HU Table
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| 462 | #define PHY20 20
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| 463 | #define CONG_CTRL 5
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| 464 | #define PORT_STATE 6
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| 465 | #define LEARNING_CTRL_REG 13
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| 466 | #define BF_STM_CTRL 16
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| 467 | #define BF_STM_THR_0 17
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| 468 | #define PORT_MIRROR_0 20
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| 469 | #define PORT_MIRROR_1 21
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| 470 |
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| 471 | //Rate Control
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| 472 | #define PHY21 21//0x0B//21 original 0x11 for FPGA
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| 473 | #define IGMP_CTRL 5
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| 474 | #define IGMP_RP_TIME 6
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| 475 | #define IGMP_GROUP_TIME 7
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| 476 | #define BW_TI 8
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| 477 | #define BW_MBS 9
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| 478 | #define BW_CREDIT_SIZE 10
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| 479 | #define BW_TIME 11
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| 480 | #define BW_SETTING 12
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| 481 | #define LEARN_CONSTRAIN 13
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| 482 | #define MAC_COMMAND 14
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| 483 | #define MAC_ADDR0 15
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| 484 | #define MAC_ADDR1 16
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| 485 | #define MAC_ADDR2 17
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| 486 | #define MAC_CONTROL 18
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| 487 | #define MAC_STATIC 19
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| 488 | #define CRC_COUNTER 25
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| 489 | //VLAN Control
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| 490 | #define PHY22 22
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| 491 |
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| 492 | #define VLAN_CLASS 0
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| 493 | #define VLAN_INGRESS 1
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| 494 | #define VLAN_EGRESS 2
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| 495 | #define VLAN_INFO_0 4
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| 496 | #define VLAN_INFO_1 VLAN_INFO_0+1
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| 497 | #define VLAN_INFO_2 VLAN_INFO_0+2
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| 498 | #define VLAN_INFO_3 VLAN_INFO_0+3
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| 499 | #define VLAN_INFO_4 VLAN_INFO_0+4
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| 500 | #define VLAN_INFO_5 VLAN_INFO_0+5
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| 501 | #define VLAN_VALID 10
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| 502 | #define VLAN_QU_NUM_EN 11
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| 503 | #define VLAN_STP_IDX_EN 12
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| 504 | #define VLAN_REW_VALN_PRI_EN 13
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| 505 |
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| 506 | #define VLAN_FID_VID0 14
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| 507 | #define VLAN_FID_VID1 VLAN_FID_VID0+1
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| 508 | #define VLAN_FID_VID2 VLAN_FID_VID0+2
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| 509 | #define VLAN_FID_VID3 VLAN_FID_VID0+3
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| 510 | #define VLAN_FID_VID4 VLAN_FID_VID0+4
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| 511 | #define VLAN_FID_VID5 VLAN_FID_VID0+5
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| 512 | #define VLAN_FID_VID6 VLAN_FID_VID0+6
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| 513 | #define VLAN_FID_VID7 VLAN_FID_VID0+7
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| 514 | #define VLAN_FID_VID8 VLAN_FID_VID0+8
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| 515 | #define VLAN_FID_VID9 VLAN_FID_VID0+9
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| 516 | #define VLAN_FID_VID10 VLAN_FID_VID0+10
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| 517 | #define VLAN_FID_VID11 VLAN_FID_VID0+11
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| 518 | #define VLAN_FID_VID12 VLAN_FID_VID0+12
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| 519 | #define VLAN_FID_VID13 VLAN_FID_VID0+13
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| 520 | #define VLAN_FID_VID14 VLAN_FID_VID0+14
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| 521 | #define VLAN_FID_VID15 VLAN_FID_VID0+15
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| 522 |
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| 523 | #define PHY23 23
|
| 524 | #define VLAN_MEMBER_00 00
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| 525 | #define VLAN_MEMBER_02 VLAN_MEMBER_00+1
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| 526 | #define VLAN_MEMBER_04 VLAN_MEMBER_00+2
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| 527 | #define VLAN_MEMBER_06 VLAN_MEMBER_00+3
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| 528 | #define VLAN_MEMBER_08 VLAN_MEMBER_00+4
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| 529 | #define VLAN_MEMBER_10 VLAN_MEMBER_00+5
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| 530 | #define VLAN_MEMBER_12 VLAN_MEMBER_00+6
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| 531 | #define VLAN_MEMBER_14 VLAN_MEMBER_00+7
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| 532 | #define VLAN_ADDTAG_00 8
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| 533 | #define VLAN_ADDTAG_02 VLAN_ADDTAG_00+1
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| 534 | #define VLAN_ADDTAG_04 VLAN_ADDTAG_00+2
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| 535 | #define VLAN_ADDTAG_06 VLAN_ADDTAG_00+3
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| 536 | #define VLAN_ADDTAG_08 VLAN_ADDTAG_00+4
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| 537 | #define VLAN_ADDTAG_10 VLAN_ADDTAG_00+5
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| 538 | #define VLAN_ADDTAG_12 VLAN_ADDTAG_00+6
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| 539 | #define VLAN_ADDTAG_14 VLAN_ADDTAG_00+7
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| 540 | #define VLAN_REMOVETAG_00 16
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| 541 | #define VLAN_REMOVETAG_02 VLAN_REMOVETAG_00+1
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| 542 | #define VLAN_REMOVETAG_04 VLAN_REMOVETAG_00+2
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| 543 | #define VLAN_REMOVETAG_06 VLAN_REMOVETAG_00+3
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| 544 | #define VLAN_REMOVETAG_08 VLAN_REMOVETAG_00+4
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| 545 | #define VLAN_REMOVETAG_10 VLAN_REMOVETAG_00+5
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| 546 | #define VLAN_REMOVETAG_12 VLAN_REMOVETAG_00+6
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| 547 | #define VLAN_REMOVETAG_14 VLAN_REMOVETAG_00+7
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| 548 | #define VLAN_MISC_00 24
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| 549 | #define VLAN_MISC_02 VLAN_MISC_00+1
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| 550 | #define VLAN_MISC_04 VLAN_MISC_00+2
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| 551 | #define VLAN_MISC_06 VLAN_MISC_00+3
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| 552 | #define VLAN_MISC_08 VLAN_MISC_00+4
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| 553 | #define VLAN_MISC_10 VLAN_MISC_00+5
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| 554 | #define VLAN_MISC_12 VLAN_MISC_00+6
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| 555 | #define VLAN_MISC_14 VLAN_MISC_00+7
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| 556 |
|
| 557 | #define PHY25 25
|
| 558 | #define QOS_CTRL 0
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| 559 | #define QOS_PORT_PRI 1
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| 560 | #define QOS_TAG_PRI 2
|
| 561 | #define QOS_TOS_PRI_0 3
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| 562 | #define QOS_TOS_PRI_1 QOS_TOS_PRI_0+1
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| 563 | #define QOS_TOS_PRI_2 QOS_TOS_PRI_0+2
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| 564 | #define QOS_TOS_PRI_3 QOS_TOS_PRI_0+3
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| 565 | #define QOS_TOS_PRI_4 QOS_TOS_PRI_0+4
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| 566 | #define QOS_TOS_PRI_5 QOS_TOS_PRI_0+5
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| 567 | #define QOS_TOS_PRI_6 QOS_TOS_PRI_0+6
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| 568 | #define QOS_TOS_PRI_7 QOS_TOS_PRI_0+7
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| 569 | #define QOS_TCP_CTRL 11
|
| 570 | #define QOS_PRE_LOGI_0 12
|
| 571 | #define QOS_PRE_LOGI_1 QOS_PRE_LOGI_0+1
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| 572 | #define QOS_PRE_LOGI_2 QOS_PRE_LOGI_0+2
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| 573 | #define QOS_PRE_LOGI_3 QOS_PRE_LOGI_0+3
|
| 574 | #define QOS_USER_RG_LOW_0 16
|
| 575 | #define QOS_USER_RG_HI_0 17
|
| 576 | #define QOS_USER_RG_LOW_1 QOS_USER_RG_LOW_0+2
|
| 577 | #define QOS_USER_RG_HI_1 QOS_USER_RG_HI_0+2
|
| 578 | #define QOS_TCP_QU_MAP 20
|
| 579 | #define QOS_LP_DROP 21
|
| 580 | #define QOS_SCH_CONFIG 22
|
| 581 | #define QOS_SCH_WEIGHT 23
|
| 582 |
|
| 583 | #define PHY26 26
|
| 584 | #define MF_CTRL 0
|
| 585 | #define MF_CLASS 1
|
| 586 | #define MF_IM_SA0 2
|
| 587 | #define MF_IM_SA1 MF_IM_SA0+1
|
| 588 | #define MF_IM_SA2 MF_IM_SA0+2
|
| 589 | #define MF_IM_DA0 5
|
| 590 | #define MF_IM_DA1 MF_IM_DA0+1
|
| 591 | #define MF_IM_DA2 MF_IM_DA0+2
|
| 592 | #define MF_ET_VALUE 8
|
| 593 | #define MF_REG9 9
|
| 594 | #define MF_TCP_UDP 10
|
| 595 | #define MF_LG_SP_NUM 11
|
| 596 | #define MF_LG_DP_NUM 12
|
| 597 | #define MF_SP_PORTNUM 13
|
| 598 | #define MF_BEHAVIOR 14
|
| 599 | #define MF_TI 15
|
| 600 | #define MF_MBS 16
|
| 601 | #define MF_CREDIT_SIZE 17
|
| 602 | #define MF_TSEL 18
|
| 603 | #define MF_VALID 19
|
| 604 | #define MF_ACCESS_CTRL 20
|
| 605 | #define MF_CNT_LSB 21
|
| 606 | #define MF_CNT_MSB 22
|
| 607 | #define MF_OVERFLOW 23
|
| 608 |
|
| 609 | #define PHY27 27//0x23
|
| 610 | #define QUEUE_MONITOR 9
|
| 611 |
|
| 612 | #endif
|