blob: f24d3b3497641ecb2d432ba9529ae654da273197 [file] [log] [blame]
b.liue9582032025-04-17 19:18:16 +08001// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2023 ASR Microelectronics Co., Ltd.
4 */
5
6/dts-v1/;
7#include "asr1806.dtsi"
8
9/ {
10 model = "ASR 1806(FALCON-T) Board EVB";
11 compatible = "asr,1803-evb", "asr,1803";
12
13 chosen {
14 bootargs = "root=/dev/mtdblock5 rootfstype=squashfs init=/etc/preinit noinitrd console=ttyS0,115200 mem=128M";
15 };
16
17 memory {
18 reg = <0x00000000 0x10000000>;
19 };
20
21 firmware {
22 optee {
23 compatible = "linaro,optee-tz";
24 method = "smc";
25 };
26 };
27
28 soc {
29 axi@d4200000 { /* AXI */
30 usbphy: usbphy@d4207000 {
31 status = "okay";
32 };
33#ifdef CONFIG_USB_DWC2_ASR_OTG /* otg mode */
34 usb: usb@c0000000 {
35 dr_mode = "otg";
36 pinctrl-names = "default","sleep";
37 pinctrl-0 = <&usb_id_pinmux &usb_host_pinmux>;
38 pinctrl-1 = <&usb_id_pinmux_slp &usb_host_pinmux>;
39 usbid_gpio = <99>;
40 edge_detect_gpio = <99>;
41 otg,use-gpio-vbus;
42 gpio-num = <122>;
43 status = "okay";
44 };
45#else
46 usb: usb@c0000000 {
47 status = "okay";
48 };
49#endif
50
51 eth0: asr-eth@0xd4281800 {
52 compatible = "asr,asr-eth";
53 pinctrl-names = "default", "rgmii-pins";
54 pinctrl-0 = <&emac_pmx_func0 &emac_pmx_func2 &emac_pmx_func3>;
55 pinctrl-1 = <&emac_pmx_func0 &emac_pmx_func1 &emac_pmx_func2 &emac_pmx_func3>;
56 reg = <0xd4281800 0x200>;
57 interrupts = <10 11>;
58 lpm-qos = <PM_QOS_CPUIDLE_BLOCK_AXI>;
59 clocks = <&soc_clocks ASR1803_CLK_EMAC
60 &soc_clocks ASR1803_CLK_EMAC_PTP>;
61 clock-names = "emac-clk", "ptp-clk";
62 ptp-support;
63 ptp-clk-rate = <100000000>;
64 status = "okay";
b.liub17525e2025-05-14 17:22:29 +080065 enable-suspend;
hj.shaof72d6ff2025-06-10 04:34:26 -070066 // reset-gpio = <&gpio 42 0>;
67 // reset-active-low;
68 // reset-delays-us = <100000 100000 100000>;
69 local-mac-address = [02 00 00 00 10 01];
b.liub17525e2025-05-14 17:22:29 +080070 //ldo-gpio = <&gpio 40 0>;
71 //ldo-active-low;
72 // ldo-delays-us = <0 100000 100000>;
73 //vmmc-supply = <0x19>;
74 mdio-clk-div = <254>;
b.liue9582032025-04-17 19:18:16 +080075 flow-control-threshold = <60 90>;
76 clk-tuning-enable;
77 /* clk-config(32bit)
78 *
79 * clk_sel(clk-config[23:16])
80 * RGMII:
81 * tx | clk_sel: 0 - from external RX clock
82 * 1 - from inverted external RX clock
83 * rx | clk_sel: 0 - from external RX clock
84 * 1 - from inverted external RX clock
85 *
86 * RMII:
87 * tx | clk_sel: 0 - RMII clock
88 * 1 - Inverted RMII clock
89 * rx | clk_sel: 0 - RMII clock
90 * 1 - Inverted RMII clock
91 *
92 */
93#if 0
94 /* enable 1000M phy*/
95 3v3-enable = <0>; /* IO voltage, 1 - 3.3v, 0 - 1.8v */
b.liub17525e2025-05-14 17:22:29 +080096 phy-handle = <&phy3>;
b.liue9582032025-04-17 19:18:16 +080097#else
98 /* enable 100M phy*/
b.liub17525e2025-05-14 17:22:29 +080099 3v3-enable = <0>; /* IO voltage, 1 - 3.3v, 0 - 1.8v */
hj.shaofe1632a2025-06-05 00:19:33 -0700100 phy-handle = <&phy0>;
b.liue9582032025-04-17 19:18:16 +0800101#endif
102 /* enable fix link for ethernet switch */
103 /*
104 fixed-link {
105 speed = <100>;
106 full-duplex;
107 phy-mode = "rmii";
108 };
109 */
110
111 mdio: mdio-bus {
112 #address-cells = <0x1>;
113 #size-cells = <0x0>;
114 /* YT8521 10M/100M/100OM 1.8V RGMII PHY */
115 phy0: phy@0 {
116 compatible = "ethernet-phy-ieee802.3-c22";
117 device_type = "ethernet-phy";
118 reg = <0x0>; /* set phy address*/
hj.shaof72d6ff2025-06-10 04:34:26 -0700119 rst-gpio = <&gpio 42 0>;
b.liue9582032025-04-17 19:18:16 +0800120 phy-mode = "rgmii";
hj.shaofe1632a2025-06-05 00:19:33 -0700121 // tx_rx_delay = <0xb 0x0>; /* 150ps per step*/
b.liue9582032025-04-17 19:18:16 +0800122 };
123
124 /* YT8512B 10M/100M 3.3V RMII PHY */
b.liub17525e2025-05-14 17:22:29 +0800125 // phy3: phy@3 {
126 // compatible = "ethernet-phy-ieee802.3-c22";
127 // device_type = "ethernet-phy";
128 // reg = <0x3>; /* set phy address*/
129 // phy-mode = "rmii";
130 // driver_strength = <0x3>;
131 // };
b.liue9582032025-04-17 19:18:16 +0800132
133 /* IP175D 10M/100M 3.3V RMII SWITCH */
134 phy1: phy@1 {
135 compatible = "ethernet-phy-ieee802.3-c22";
136 device_type = "ethernet-phy";
137 reg = <0x1>; /* set phy address*/
138 phy-mode = "rmii";
139 };
b.liub17525e2025-05-14 17:22:29 +0800140
141
142 /* jl 3103 phy */
143 phy3: phy@3 {
144 compatible = "ethernet-phy-ieee802.3-c22";
145 device_type = "ethernet-phy";
146 reg = <0x3>; /* set phy address*/
147 phy-mode = "rgmii-id";
148 lynq,jl3103=<100 0>;
149 };
b.liue9582032025-04-17 19:18:16 +0800150 };
151 };
152 qspi: spi@0xd420b000 {
153 asr,qspi-freq = <78000000>;
154 status = "okay";
155 };
156 /* SD card */
157 sdh0: sdh@d4280000 {
158 pinctrl-names = "default", "slow", "fast", "sleep";
159 pinctrl-0 = <&sdh0_pmx_func1 &sdh0_pmx_func2 &sdh0_pmx_func3>;
160 pinctrl-1 = <&sdh0_pmx_func1_slow &sdh0_pmx_func2_slow &sdh0_pmx_func3>;
161 pinctrl-2 = <&sdh0_pmx_func1_fast &sdh0_pmx_func2_fast &sdh0_pmx_func3>;
162 pinctrl-3 = <&sdh0_pmx_cd_wakeup>;
163 /*
164 * Genernal use, juse set vmmc-supply and vqmmc-supply
165 * vmmc-supply = <&supply1>
166 * vqmmc-supply = <&supply2>
167 *
168 * For compatibility, to select one from two supply source
169 * vmmc-supply = <&supply1 &supply1_backup>;
170 * vqmmc-supply = <&supply2 &supply2_backup>;
171 * vmmc2-supply = <&supply1_backup &supply1>;
172 * vqmmc2-supply = <&supply2_backup &supply2>;
173 */
174 vmmc-supply = <&vcc_sdh1>;
zw.wang5deb3e82025-05-30 11:29:23 +0800175 vqmmc-supply = <&pm802ldo6 &pm803ldo8>;
b.liue9582032025-04-17 19:18:16 +0800176#ifndef CONFIG_ASR_DSDS
177 vmmc2-supply = <&vcc_sdh1 &pm802ldo4>;
178 vqmmc2-supply = <&pm803ldo8 &pm802ldo6>;
179#endif
180 bus-width = <4>;
181 no-mmc;
182 no-sdio;
183 /*non-removable;
184 broken-cd;*/
185 wp-inverted;
186 asr,sdh-pm-runtime-en;
187 asr,sdh-host-caps-disable = <(MMC_CAP_UHS_SDR104)>;
188#if 1 /* CD via gpio */
zw.wang5deb3e82025-05-30 11:29:23 +0800189 //cd-gpios = <&gpio 90 1>;
b.liue9582032025-04-17 19:18:16 +0800190 asr,sdh-quirks2 = <(
191 SDHCI_QUIRK2_SET_AIB_MMC |
192 SDHCI_QUIRK2_PRESET_VALUE_BROKEN
193 )>;
194 asr,sdh-host-caps = <(
195 MMC_CAP_CD_WAKE
196 )>;
197 asr,sdh-quirks = <(
198 SDHCI_QUIRK_BROKEN_CARD_DETECTION |
199 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
200 )>;
201#else /* CD via SDH */
202 asr,sdh-quirks = <(
203 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
204 )>;
205 asr,sdh-quirks2 = <(
206 SDHCI_QUIRK2_SET_AIB_MMC |
207 SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
208 SDHCI_QUIRK2_BASE_CLOCK_ALWAYS_ON
209 )>;
210#endif
211 /* prop "sdh-dtr-data":
212 <timing preset_rate src_rate tx_delay rx_delay tx_dline_reg rx_dline_reg> */
213 asr,sdh-dtr-data =
214 <PXA_MMC_TIMING_LEGACY PXA_SDH_DTR_26M PXA_SDH_DTR_104M 0 0 0 0>,
215 <PXA_MMC_TIMING_SD_HS PXA_SDH_DTR_52M PXA_SDH_DTR_104M 0 0 0 0>,
216 <PXA_MMC_TIMING_UHS_DDR50 PXA_SDH_DTR_52M PXA_SDH_DTR_104M 0 0 0 3>,
217 <PXA_MMC_TIMING_UHS_SDR50 PXA_SDH_DTR_104M PXA_SDH_DTR_208M 0 0 0 0>,
218 <PXA_MMC_TIMING_UHS_SDR104 PXA_SDH_DTR_208M PXA_SDH_DTR_208M 0 0 0 0>,
219 <PXA_MMC_TIMING_MAX PXA_SDH_DTR_PS_NONE PXA_SDH_DTR_104M 0 0 0 0>;
220 status = "okay";
221 };
222
223 /* SDIO */
224 sdh1: sdh@d4280800 {
225 pinctrl-names = "default", "fast", "sleep";
b.liub17525e2025-05-14 17:22:29 +0800226 pinctrl-0 = <&sdh1_pmx_func1 &sdh1_pmx_func2>;
227 pinctrl-1 = <&sdh1_pmx_func1_fast &sdh1_pmx_func2_fast>;
228 /* pinctrl-2 = <&sdh1_pmx_edge_wakeup>;*/
b.liue9582032025-04-17 19:18:16 +0800229 bus-width = <4>;
230 no-mmc;
231 no-sd;
232 non-removable;
233 keep-power-in-suspend;
234 enable-sdio-wakeup;
235 /* clk-scaling-config:
236 <up_threshold down_threshold polling_interval> */
237 clk-scaling-config = <25 12 200>;
238 min-ddr-qos = <156000 312000 400000>;
239 asr,sdh-pm-runtime-en;
240 asr,sdh-quirks = <(
241 SDHCI_QUIRK_BROKEN_CARD_DETECTION |
242 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
243 )>;
244 asr,sdh-quirks2 = <(
245 SDHCI_QUIRK2_NO_TIMER_RETUNING |
246 SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
247 SDHCI_QUIRK2_BASE_CLOCK_ALWAYS_ON
248 )>;
249 asr,sdh-pm-caps = <(MMC_PM_KEEP_POWER)>;
250 asr,sdh-host-caps2 = <(
251 MMC_CAP2_ONLY_1_8V |
252 MMC_CAP2_DISABLE_PROBE_CDSCAN |
253 MMC_CAP2_CLK_SCALE |
254 MMC_CAP2_BUS_CLK_NO_SCALE
255 )>;
256 /* prop "sdh-dtr-data":
257 <timing preset_rate src_rate tx_delay rx_delay tx_dline_reg rx_dline_reg> */
258 asr,sdh-dtr-data =
259 <PXA_MMC_TIMING_LEGACY PXA_SDH_DTR_26M PXA_SDH_DTR_104M 0 0 0 0>,
260 <PXA_MMC_TIMING_SD_HS PXA_SDH_DTR_45M PXA_SDH_DTR_89M 0 0 0 0>,
261 <PXA_MMC_TIMING_UHS_DDR50 PXA_SDH_DTR_52M PXA_SDH_DTR_104M 0 0 0 3>,
262 <PXA_MMC_TIMING_UHS_SDR50 PXA_SDH_DTR_83M PXA_SDH_DTR_83M 0 0 0 3>,
b.liub17525e2025-05-14 17:22:29 +0800263 //<PXA_MMC_TIMING_UHS_SDR104 PXA_SDH_DTR_208M PXA_SDH_DTR_208M 0 0 0 0>,
264 <PXA_MMC_TIMING_UHS_SDR104 PXA_SDH_DTR_52M PXA_SDH_DTR_52M 0 0 0 0>,
b.liue9582032025-04-17 19:18:16 +0800265 <PXA_MMC_TIMING_MAX PXA_SDH_DTR_PS_NONE PXA_SDH_DTR_89M 0 0 0 0>;
266 status = "okay";
267 };
268 pcie0: pcie@0xd4288000{
269 reset-gpios = <&gpio 42 0 >;
b.liub17525e2025-05-14 17:22:29 +0800270 status = "disbabled";
b.liue9582032025-04-17 19:18:16 +0800271 };
272 pciephy0: pcie-phy@d4206000 {
273 status = "okay";
274 };
275 };
276
277 apb@d4000000 {
278 ssp_dai1: pxa-ssp-dai@1 {
279 compatible = "asr,pxa-ssp-dai";
280 reg = <0x1 0x0>;
281
282 port = <&ssp1>;
283 pinctrl-names = "default","ssp";
284 pinctrl-0 = <&i2s_gpio>;
285 pinctrl-1 = <&i2s_func>;
286 ssp-gpio = <&gpio 25 0 &gpio 26 0 &gpio 27 0 &gpio 28 0>;
287
288 dmas = <&pdma0 54 1
289 &pdma0 55 1>;
290 dma-names = "rx", "tx";
291
292 platform_driver_name = "pdma_platform";
293 burst_size = <4>;
294 playback_period_bytes = <2048>;
295 playback_buffer_bytes = <4096>;
296 capture_period_bytes = <2048>;
297 capture_buffer_bytes = <4096>;
298 };
299 mfpr: mfpr@d401e000 {
300 status = "okay";
301 /* intend to replace lpm-board-cfg
302 no-apbsd-in-d1pp = <0x1>; //"wakeup-state-d1pp"
303 pin1:pin1@d401e01B0 {
304 offset = <0x1B0>;
305 udr-cfg = <0xA040>;
306 };
307 pin2:pin2@d401e01B4 {
308 offset = <0x1B4>;
309 udr-cfg = <0xA040>;
310 };
311 */
312 };
313 timer0: timer@d4014000 {
314 status = "okay";
315 };
316 uart1: uart@d4017000 { /* nezhas evb use ap uart */
317 pinctrl-names = "default","sleep";
318 pinctrl-0 = <&uart1_pmx_func1 &uart1_pmx_func2>;
319 pinctrl-1 = <&uart1_pmx_func1_sleep &uart1_pmx_func2>;
b.liub17525e2025-05-14 17:22:29 +0800320 //edge-wakeup-gpio = <&gpio 29 0>; /* GPIO29: AP UART rx pin */
b.liue9582032025-04-17 19:18:16 +0800321 status = "okay";
322 };
323 uart2: uart@d4036000 {
324 pinctrl-names = "default";
hj.shao9f48a912025-06-11 00:19:29 -0700325
326 //#LYNQ_MODFIY modify for task-1618 2025/6/11 start
327 pinctrl-0 = <&gps_pmx_uart_rxd &gps_pmx_uart_txd>; //&gps_pmx_func_cts_rts>;
328 //#LYNQ_MODFIY modify for task-1618 2025/6/11 end
b.liue9582032025-04-17 19:18:16 +0800329 status = "okay";
330 };
331 uart3: uart@d4018000 {
332 pinctrl-names = "default";
333 pinctrl-0 = <&uart3_pmx_func>;
b.liub17525e2025-05-14 17:22:29 +0800334 status = "okay";
b.liue9582032025-04-17 19:18:16 +0800335 };
336 uart4: uart@d401f000 {
337 pinctrl-names = "default";
b.liub17525e2025-05-14 17:22:29 +0800338 pinctrl-0 = <&uart4_pmx_func>; /*BAUD :9600*/
339 /*pinctrl-0 = <&uart4_pmx_func_rxd &uart4_pmx_func_txd &uart4_pmx_func_cts_rts>;*/
340 status = "okay";
b.liue9582032025-04-17 19:18:16 +0800341 };
342 rtc: rtc@d4010000 {
343 status = "okay";
344 };
345 pmx: pinmux@d401e000 {
346 /* pin base = base_addr / 4, nr pins & gpio function */
347 pinctrl-single,gpio-range = <
348 /*
349 * GPIO number is hardcoded for range at here.
350 * In gpio chip, GPIO number is not hardcoded for range.
351 * Since one gpio pin may be routed to multiple pins,
352 * define these gpio range in pxa910-dkb.dts not pxa910.dtsi.
353 */
354 /*&range 80 4 0 */ /* GPIO25 ~ GPIO28 */
355 &range 55 32 0 /* GPIO0 ~ GPIO31 */
356 &range 87 32 0 /* GPIO32 ~ GPIO63 */
357 &range 119 32 0 /* GPIO64 ~ GPIO95 */
358 &range 151 32 0 /* GPIO96 ~ GPIO127 */
359 >;
360
361 ssp0_pmx_func: ssp0_pmx_func {
362 pinctrl-single,pins = <
363 GPIO36 AF1 /* TXD */
364 GPIO35 AF1 /* RXD */
365 GPIO34 AF1 /* FRM */
366 /*GPIO34 AF0*/ /* FRM *//* DXS101 Use the config of Cs-gpios */
367 GPIO33 AF1 /* SCLK */
368 >;
b.liub17525e2025-05-14 17:22:29 +0800369 DS_SLOW0;PULL_NONE;EDGE_NONE;SL_NORMAL; //DS_MEDIUM modify for overvoltage
370 };
371 ssp2_pmx_func: ssp2_pmx_func {
372 pinctrl-single,pins = <
373 GPIO37 AF3 /* TXD */
374 GPIO38 AF3 /* SCLK */
375 GPIO39 AF3 /* FRM */
376 GPIO40 AF3 /* RXD */
377 >;
378 DS_SLOW0;PULL_NONE;EDGE_NONE;SL_NORMAL; //DS_MEDIUM modify for overvoltage
b.liue9582032025-04-17 19:18:16 +0800379 };
380 lcd_bl_func: lcd_bl_func {
381 pinctrl-single,pins = <
b.liub17525e2025-05-14 17:22:29 +0800382 /* VCXO_OUT AF1 GPIO126, lcd bl */
383 /* GPIO24 AF0 reset */
384 /* GPIO22 AF0 lcd d/c */
b.liue9582032025-04-17 19:18:16 +0800385 >;
386 MFP_DEFAULT;
387 };
388 uart1_pmx_func1: uart1_pmx_func1 {
389 pinctrl-single,pins = <
390 GPIO29 AF1
391 >;
392 MFP_DEFAULT;
393 };
394 uart1_pmx_func2: uart1_pmx_func2 {
395 pinctrl-single,pins = <
396 GPIO30 AF1
397 >;
398 MFP_DEFAULT;
399 };
400 uart1_pmx_func1_sleep: uart1_pmx_func1_sleep {
401 pinctrl-single,pins = <
402 GPIO29 AF1
403 >;
b.liub17525e2025-05-14 17:22:29 +0800404 DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL;
b.liue9582032025-04-17 19:18:16 +0800405 };
406 twsi0_pmx_func: twsi0_pmx_func {
407 pinctrl-single,pins = <
408 GPIO49 AF1
409 GPIO50 AF1
410 >;
b.liub17525e2025-05-14 17:22:29 +0800411 DS_MEDIUM;PULL_NONE;EDGE_NONE;LPM_FLOAT;
b.liue9582032025-04-17 19:18:16 +0800412 };
413 twsi0_pmx_gpio: twsi0_pmx_gpio {
414 pinctrl-single,pins = <
415 GPIO49 AF0
416 GPIO50 AF0
417 >;
b.liub17525e2025-05-14 17:22:29 +0800418 DS_MEDIUM;PULL_NONE;EDGE_NONE;LPM_FLOAT;
b.liue9582032025-04-17 19:18:16 +0800419 };
b.liub17525e2025-05-14 17:22:29 +0800420#if 1
b.liue9582032025-04-17 19:18:16 +0800421 twsi1_pmx_func: twsi1_pmx_func {
422 pinctrl-single,pins = <
423 GPIO10 AF1
424 GPIO11 AF1
425 >;
b.liub17525e2025-05-14 17:22:29 +0800426 DS_SLOW0;PULL_NONE;EDGE_NONE;LPM_FLOAT;
b.liue9582032025-04-17 19:18:16 +0800427 };
428 twsi1_pmx_gpio: twsi1_pmx_gpio {
429 pinctrl-single,pins = <
430 GPIO10 AF0
431 GPIO11 AF0
432 >;
b.liub17525e2025-05-14 17:22:29 +0800433 DS_SLOW0;PULL_NONE;EDGE_NONE;LPM_FLOAT;
b.liue9582032025-04-17 19:18:16 +0800434 };
435#endif
436 /* no pull, no LPM */
437 dvc_pmx_func: dvc_pmx_func {
438 /* hw-dvc */
439 pinctrl-single,pins = <
440 TDS_DIO0 AF0
441 TDS_DIO1 AF0
442 >;
443 DS_MEDIUM;PULL_FLOAT;EDGE_NONE;SL_NORMAL;
444 };
445 leds_pmx_func: leds_pmx_func {
446 pinctrl-single,pins = <
447 DF_IO10 AF1
448 DF_IO11 AF1
449 DF_IO12 AF1
450 >;
451 DS_MEDIUM;PULL_FLOAT;EDGE_NONE;SL_NORMAL;
452 };
453
454 gps_pmx_onoff: gps_pmx_onoff {
455 pinctrl-single,pins = <
456 TDS_TXREV AF1
457 >;
458 DS_MEDIUM;PULL_DOWN;EDGE_NONE;SL_NORMAL;
459 };
460 gps_pmx_reset: gps_pmx_reset {
461 pinctrl-single,pins = <
462 TDS_RXON AF1
463 >;
464 DS_MEDIUM;PULL_DOWN;EDGE_NONE;SL_NORMAL;
465 };
b.liub17525e2025-05-14 17:22:29 +0800466
467 //zqy
468 gnss_clk_on: gnss_clk_on {
469 pinctrl-single,pins = <
470 GPIO43 AF2 /*32K CLK */
471
472 /*VCXO_REQ AF1 GPIO[125] GPS_WAKE_HOST */
473 GPIO47 AF0 /* HOST_WAKE_GPS */
474 GPIO45 AF0 /*RESET */
475 CLK_REQ AF1 /*sleep en*/
476
477 >;
478 DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_LOW;
479 };
b.liue9582032025-04-17 19:18:16 +0800480 gps_pmx_uart_rxd: gps_pmx_uart_rxd {
481 /* gps dedicated uart */
482 pinctrl-single,pins = <
483 GPIO51 AF1
hj.shao9f48a912025-06-11 00:19:29 -0700484
485 //#LYNQ_MODFIY modify for task-1618 2025/6/11 start
486 /*GPIO32 AF1*/
487 //#LYNQ_MODFIY modify for task-1618 2025/6/11 end
b.liue9582032025-04-17 19:18:16 +0800488 >;
b.liub17525e2025-05-14 17:22:29 +0800489 DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL;
b.liue9582032025-04-17 19:18:16 +0800490 };
491 gps_pmx_uart_txd: gps_pmx_uart_txd {
492 /* gps dedicated uart */
493 pinctrl-single,pins = <
494 GPIO52 AF1
hj.shao9f48a912025-06-11 00:19:29 -0700495 //#LYNQ_MODFIY modify for task-1618 2025/6/11 start
496 /*GPIO31 AF1*/
497 //#LYNQ_MODFIY modify for task-1618 2025/6/11 end
b.liue9582032025-04-17 19:18:16 +0800498 >;
b.liub17525e2025-05-14 17:22:29 +0800499 DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL;
b.liue9582032025-04-17 19:18:16 +0800500 };
b.liub17525e2025-05-14 17:22:29 +0800501 gps_pmx_func_cts_rts: gps_pmx_func_cts_rts {
502 pinctrl-single,pins = <
503 GPIO31 AF1 /* cts */
504 GPIO32 AF1 /* rts */
505 >;
506 DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL;
507 };
508
b.liue9582032025-04-17 19:18:16 +0800509 uart3_pmx_func: uart3_pmx_func {
510 pinctrl-single,pins = <
511 GPIO53 AF1 /* RX */
yu.dongca721ca2025-06-04 07:21:21 -0700512 /* GPIO54 AF1 TX */
b.liue9582032025-04-17 19:18:16 +0800513 >;
514 MFP_DEFAULT;
515 };
b.liub17525e2025-05-14 17:22:29 +0800516
517
518 uart4_pmx_func_rxd: uart4_pmx_func_rxd {
519 pinctrl-single,pins = <
520 GPIO37 AF2
521 GPIO40 AF2
522 >;
523 DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL;
524 };
525 uart4_pmx_func_txd: uart4_pmx_func_txd {
526 pinctrl-single,pins = <
527 GPIO38 AF2
528 GPIO39 AF2
529 >;
530 DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL;
531 };
532
533 uart4_pmx_func_cts_rts: uart4_pmx_func_cts_rts {
534 pinctrl-single,pins = <
535 GPIO39 AF2
536 GPIO40 AF2
537 >;
538 DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL;
539 };
b.liue9582032025-04-17 19:18:16 +0800540 uart4_pmx_func: uart4_pmx_func {
541 pinctrl-single,pins = <
542 GPIO44 AF1 /* RX */
543 GPIO45 AF1 /* TX */
544 >;
b.liub17525e2025-05-14 17:22:29 +0800545 DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL;
b.liue9582032025-04-17 19:18:16 +0800546 };
547 panel_rst_func: panel_rst_func {
548 pinctrl-single,pins = <
549 DF_nCS1 AF1
550 >;
551 DS_MEDIUM;PULL_FLOAT;EDGE_NONE;SL_NORMAL;
552 };
553
554 sd_ldo_en: sd_ldo_en {
555 pinctrl-single,pins = <
556 GPIO45 AF0
557 >;
558 MFP_PULL_DOWN;
559 };
560 sdh0_pmx_func1: sdh0_pmx_func1 {
561 pinctrl-single,pins = <
562 MMC1_DAT3 AF0
563 MMC1_DAT2 AF0
564 MMC1_DAT1 AF0
565 MMC1_DAT0 AF0
566 MMC1_CMD AF0
567 >;
568 DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL;
569 };
570 sdh0_pmx_func2: sdh0_pmx_func2 {
571 pinctrl-single,pins = <
572 MMC1_CLK AF0
573 >;
574 DS_MEDIUM;PULL_NONE;EDGE_NONE;
575 };
576 sdh0_pmx_func3: sdh0_pmx_func3 {
577 pinctrl-single,pins = <
578 MMC1_CD AF1
579 >;
580 DS_MEDIUM;PULL_UP;EDGE_NONE;SL_NORMAL;
581 };
582 sdh0_pmx_cd_wakeup: sdh0_pmx_func1_cd_wakeup {
583 pinctrl-single,pins = <
584 MMC1_CD AF1
585 >;
586 DS_MEDIUM;PULL_UP;EDGE_BOTH;SL_NORMAL;
587 };
588 sdh0_pmx_func1_slow: sdh0_pmx_func1_slow {
589 pinctrl-single,pins = <
590 MMC1_DAT3 AF0
591 MMC1_DAT2 AF0
592 MMC1_DAT1 AF0
593 MMC1_DAT0 AF0
594 MMC1_CMD AF0
595 >;
596 DS_FAST0;PULL_NONE;EDGE_NONE;SL_NORMAL;
597 };
598 sdh0_pmx_func2_slow: sdh0_pmx_func2_slow {
599 pinctrl-single,pins = <
600 MMC1_CLK AF0
601 >;
602 DS_FAST0;PULL_NONE;EDGE_NONE;
603 };
604 sdh0_pmx_func1_fast: sdh0_pmx_func1_fast {
605 pinctrl-single,pins = <
606 MMC1_DAT3 AF0
607 MMC1_DAT2 AF0
608 MMC1_DAT1 AF0
609 MMC1_DAT0 AF0
610 MMC1_CMD AF0
611 >;
612 DS_FAST1;PULL_NONE;EDGE_NONE;SL_NORMAL;
613 };
614 sdh0_pmx_func2_fast: sdh0_pmx_func2_fast {
615 pinctrl-single,pins = <
616 MMC1_CLK AF0
617 >;
618 DS_FAST1;PULL_NONE;EDGE_NONE;
619 };
620 sdh1_pmx_func1_fast: sdh1_pmx_func1_fast {
621 pinctrl-single,pins = <
622 TDS_DIO13 AF0 /* WLAN_DAT3 */
623 TDS_DIO14 AF0 /* WLAN_DAT2 */
624 TDS_DIO15 AF0 /* WLAN_DAT1 */
625 TDS_DIO16 AF0 /* WLAN_DAT0 */
626 TDS_DIO17 AF0 /* WLAN_CMD */
627 >;
628 DS_FAST0;PULL_NONE;EDGE_NONE;SL_NORMAL;
629 };
630 sdh1_pmx_func2_fast: sdh1_pmx_func2_fast {
631 pinctrl-single,pins = <
632 TDS_DIO18 AF0 /* WLAN_CLK */
633 >;
634 DS_FAST0;PULL_DOWN;EDGE_NONE;SL_NORMAL;
635 };
636 sdh1_pmx_func1: sdh1_pmx_func1 {
637 pinctrl-single,pins = <
638 TDS_DIO13 AF0 /* WLAN_DAT3 */
639 TDS_DIO14 AF0 /* WLAN_DAT2 */
640 TDS_DIO15 AF0 /* WLAN_DAT1 */
641 TDS_DIO16 AF0 /* WLAN_DAT0 */
642 TDS_DIO17 AF0 /* WLAN_CMD */
643 >;
644 DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_LOW;
645 };
646 sdh1_pmx_func2: sdh1_pmx_func2 {
647 pinctrl-single,pins = <
648 TDS_DIO18 AF0 /* WLAN_CLK */
649 >;
650 DS_MEDIUM;PULL_DOWN;EDGE_NONE;SL_LOW;
651 };
652 sdh1_pmx_func3: sdh1_pmx_func3 {
653 pinctrl-single,pins = <
654 GPIO10 AF0 /* VCXO_REQ AF1 WLAN_WAKE_HOST */
655 >;
656 MFP_PULL_DOWN;
657 };
658 sdh1_pmx_edge_wakeup: sdh1_pmx_edge_wakeup {
659 pinctrl-single,pins = <
660 GPIO10 AF0 /* VCXO_REQ AF1 */
661 >;
662 DS_MEDIUM;PULL_DOWN;EDGE_RISE;SL_NORMAL;
663 };
664 sdh1_pmx_pd_rst_off: sdh1_pmx_pd_rst_off {
665 pinctrl-single,pins = <
b.liub17525e2025-05-14 17:22:29 +0800666 /* GPIO11 AF0 GPIO31 AF0 WLAN_PDn */
667 /* GPIO08 AF0 GPIO32 AF0 LDO_EN */
668 MMC1_CD AF1
b.liue9582032025-04-17 19:18:16 +0800669 >;
670 MFP_PULL_DOWN;
671 };
672 sdh1_pmx_pd_rst_on: sdh1_pmx_pd_rst_on {
673 pinctrl-single,pins = <
b.liub17525e2025-05-14 17:22:29 +0800674 /* GPIO11 AF0 GPIO31 AF0 WLAN_PDn */
675 /* GPIO08 AF0 GPIO32 AF0 LDO_EN */
676 MMC1_CD AF1
677 >;
678 MFP_PULL_UP;
679 };
680
681
682 mbtk_sdh_pmx_off: mbtk_sdh_pmx_off {
683 pinctrl-single,pins = <
684 VCXO_REQ AF1 //gpio125 wlan en
685 GPIO123 AF1 //wlan pwr en
you.chen9824a892025-06-04 20:23:26 +0800686 /*VCXO_OUT AF1 /*gpio127 wifi wake*/
b.liub17525e2025-05-14 17:22:29 +0800687 >;
688 MFP_PULL_DOWN;
689 };
690 mbtk_sdh_pmx_on: mbtk_sdh_pmx_on {
691 pinctrl-single,pins = <
692 VCXO_REQ AF1 //gpio125 wlan en
693 GPIO123 AF1 //wlan pwr en
you.chen9824a892025-06-04 20:23:26 +0800694 /*VCXO_OUT AF1 /*gpio127 wifi wake*/
b.liue9582032025-04-17 19:18:16 +0800695 >;
696 MFP_PULL_UP;
697 };
698 alc5616_pmx_func1: alc5616_pmx_func1 {
699 pinctrl-single,pins = <
b.liub17525e2025-05-14 17:22:29 +0800700 /* GPIO08 AF0 AP_UART1_DCD_N -> CODEC_IRQ */
b.liue9582032025-04-17 19:18:16 +0800701 GPIO20 AF7 /* MCLK:I2S_SYSCLK */
702 >;
703 MFP_DEFAULT;
704 };
705 alc5616_pmx_func2: alc5616_pmx_func2 {
706 pinctrl-single,pins = <
b.liub17525e2025-05-14 17:22:29 +0800707 /* GPIO08 AF0 AP_UART1_DCD_N -> CODEC_IRQ */
708 GPIO20 AF7 /* MCLK:I2S_SYSCLK */
709 >;
710 MFP_DEFAULT;
711 };
712
713 es8311_pa_func1: es8311_pa_func1 {
714 pinctrl-single,pins = <
715 GPIO20 AF7 /* MCLK:I2S_SYSCLK */
yu.dongca721ca2025-06-04 07:21:21 -0700716 GPIO54 AF0
717 GPIO24 AF0
b.liub17525e2025-05-14 17:22:29 +0800718 >;
719 MFP_DEFAULT;
720 };
721 es8311_pa_func2: es8311_pa_func2 {
722 pinctrl-single,pins = <
b.liue9582032025-04-17 19:18:16 +0800723 GPIO20 AF7 /* MCLK:I2S_SYSCLK */
yu.dongca721ca2025-06-04 07:21:21 -0700724 GPIO54 AF0
725 GPIO24 AF0
b.liue9582032025-04-17 19:18:16 +0800726 >;
727 MFP_DEFAULT;
728 };
729 audio_pa_pmx_func: audio_pa_pmx_func {
730 pinctrl-single,pins = <
731 GPIO14 AF0 /* PA */
732 >;
733 MFP_DEFAULT;
734 };
735 ecall_pmx_func: ecall_pmx_func {
736 pinctrl-single,pins = <
737 GPIO08 AF0 /* auto mode ecall */
738 GPIO09 AF0 /* manual mode ecall */
739 >;
740 MFP_DEFAULT;
741 };
742 slic_pmx_func1: slic_pmx_func1 {
743 pinctrl-single,pins = <
744 GPIO20 AF0 /* SLIC_INT, GPIO20 */
745 VCXO_OUT AF1 /* GPIO127, SLIC_3V3LDO_EN/LCD_BK_EN */
746 >;
747 MFP_DEFAULT;
748 };
749 slic_pmx_func2: slic_pmx_func2 {
750 pinctrl-single,pins = <
751 GPIO21 AF0 /* SLIC_RESET, GPIO21 */
752 >;
753 MFP_DEFAULT;
754 };
755 slic_pmx_func1_sleep: slic_pmx_func1_sleep {
756 pinctrl-single,pins = <
757 GPIO20 AF0 /* SLIC_INT, GPIO20 */
758 >;
759 DS_MEDIUM;PULL_UP;EDGE_BOTH;SL_NORMAL;
760 };
761
762 otg_vbus_func: otg_vbus_func {
763 pinctrl-single,pins = <
b.liub17525e2025-05-14 17:22:29 +0800764 /* VBUS_DRV AF1 GPIO[122] */
b.liue9582032025-04-17 19:18:16 +0800765 >;
766 DS_MEDIUM;PULL_DOWN;EDGE_NONE;
767 };
768
769 emac_pmx_func0: emac_pmx_func0 {
770 pinctrl-single,pins = <
771 GPIO00 AF1 /* GMAC1_RX_DV */
772 GPIO01 AF1 /* GMAC1_RX_D0 */
773 GPIO02 AF1 /* GMAC1_RX_D1 */
774 GPIO03 AF1 /* GMAC1_RX_CLK */
775 /* GPIO04 AF1 GMAC1_RX_D2 */
776 /* GPIO05 AF1 GMAC1_RX_D3 */
777 GPIO06 AF1 /* GMAC1_TX_D0 */
778 GPIO07 AF1 /* GMAC1_TX_D1 */
779 /* GPIO12 AF1 GMAC1_TX_CLK */
780 /* GPIO13 AF1 GMAC1_TX_D2 */
781 /* GPIO14 AF1 GMAC1_TX_D3 */
782 GPIO15 AF1 /* GMAC1_TX_EN */
783 GPIO16 AF1 /* GMAC1_TX_MDC */
784 /* GPIO17 AF1 GMAC1_TX_MDIO */
785 >;
786 DS_MEDIUM;PULL_DOWN;EDGE_NONE;SL_NORMAL;
787 };
788 emac_pmx_func1: emac_pmx_func1 {
789 pinctrl-single,pins = <
790 GPIO04 AF1 /* GMAC1_RX_D2 */
791 GPIO05 AF1 /* GMAC1_RX_D3 */
792 GPIO12 AF1 /* GMAC1_TX_CLK */
793 GPIO13 AF1 /* GMAC1_TX_D2 */
794 GPIO14 AF1 /* GMAC1_TX_D3 */
795 >;
796 DS_MEDIUM;PULL_DOWN;EDGE_NONE;SL_NORMAL;
797 };
798 emac_pmx_func2: emac_pmx_func2 {
799 pinctrl-single,pins = <
800 GPIO17 AF1 /* GMAC1_TX_MDIO */
801 GPIO18 AF1 /* GMAC1_TX_INT_N */
802 >;
803 DS_MEDIUM;PULL_UP;EDGE_NONE;SL_NORMAL;
804 };
805 emac_pmx_func3: emac_pmx_func3 {
806 pinctrl-single,pins = <
b.liub17525e2025-05-14 17:22:29 +0800807 GPIO42 AF0 /* RESET */
808 /* GPIO40 AF0 LDO_EN */
b.liue9582032025-04-17 19:18:16 +0800809 >;
810 DS_SLOW0;PULL_FLOAT;EDGE_NONE;SL_NORMAL;
811 };
812 usim1_pmx_func: usim1_pmx_func {
813 pinctrl-single,pins = <
yq.wang107f9862025-05-12 15:44:50 +0800814 PRI_TCK AF1
b.liue9582032025-04-17 19:18:16 +0800815 >;
816 DS_MEDIUM;PULL_UP;EDGE_NONE;SL_NORMAL;
817 };
818 usim1_pmx_func_sleep: usim1_pmx_func_sleep {
819 pinctrl-single,pins = <
yq.wang107f9862025-05-12 15:44:50 +0800820 PRI_TCK AF1
b.liue9582032025-04-17 19:18:16 +0800821 >;
822 DS_MEDIUM;PULL_UP;EDGE_BOTH;SL_NORMAL;
823 };
824 usim2_pmx_func: usim2_pmx_func {
825 pinctrl-single,pins = <
826 GPIO44 AF0
827 >;
828 DS_MEDIUM;PULL_UP;EDGE_NONE;SL_NORMAL;
829 };
830 usim2_pmx_func_sleep: usim2_pmx_func_sleep {
831 pinctrl-single,pins = <
832 GPIO44 AF0
833 >;
834 DS_MEDIUM;PULL_UP;EDGE_BOTH;SL_NORMAL;
835 };
836 pcie_pmx_pd_rst_off: pcie_pmx_pd_rst_off {
837 pinctrl-single,pins = <
838 GPIO42 AF0 /* PERST_N */
839 GPIO24 AF0 /* DC_EN */
840 >;
841 MFP_PULL_DOWN;
842 };
843 pcie_pmx_pd_rst_on: pcie_pmx_pd_rst_on {
844 pinctrl-single,pins = <
845 GPIO42 AF0 /* PERST_N */
846 GPIO24 AF0 /* DC_EN */
847 >;
848 MFP_PULL_UP;
849 };
b.liub17525e2025-05-14 17:22:29 +0800850 pin_func_work: pin_func_work {
851 pinctrl-single,pins = <
852
853 GPIO08 AF0 /*T108 status led* /
854
855 VBUS_DRV AF2 /*32k*/
856
857
858 GPIO46 AF0 /*wifi en*/
859
860 GPIO19 AF0 /*bt en*/
861
862 >;
863 MFP_DEFAULT;
864 };
865
866
867 sc_ext_int0: sc_ext_int0 {
868 pinctrl-single,pins = <
869 GPIO21 AF0
870 >;
871 DS_MEDIUM;PULL_NONE;EDGE_BOTH;SL_NORMAL;
872 };
873 sc_ext_int1: sc_ext_int1 {
874 pinctrl-single,pins = <
875 GPIO22 AF0
876 >;
877 MFP_DEFAULT;
878 };
879
880 sc_ext_int2: sc_ext_int2 {
881 pinctrl-single,pins = <
882 GPIO23 AF0
883 >;
884 MFP_DEFAULT;
885 };
886
887
888 sc_ext_int3: sc_ext_int3 {
889 pinctrl-single,pins = <
890 GPIO24 AF0
891 >;
892 MFP_DEFAULT;
893 };
894
895
896 mbtk_plat_irq_func: mbtk_plat_irq_func {
897 pinctrl-single,pins = <
898
you.chen9824a892025-06-04 20:23:26 +0800899 /*GPIO21 AF0
900 GPIO22 AF0 */
b.liub17525e2025-05-14 17:22:29 +0800901 GPIO23 AF0
yu.dongca721ca2025-06-04 07:21:21 -0700902 GPIO24 AF0
b.liub17525e2025-05-14 17:22:29 +0800903
904 >;
905 DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL;
906 };
907 mbtk_plat_irq_func_sleep: mbtk_plat_irq_func_sleep {
908 pinctrl-single,pins = <
you.chen9824a892025-06-04 20:23:26 +0800909 /*GPIO21 AF0
910 GPIO22 AF0*/
b.liub17525e2025-05-14 17:22:29 +0800911 GPIO23 AF0
yu.dongca721ca2025-06-04 07:21:21 -0700912 GPIO24 AF0
b.liub17525e2025-05-14 17:22:29 +0800913 >;
914 DS_MEDIUM;PULL_NONE;EDGE_BOTH;SL_NORMAL;
915 };
916
917
b.liue9582032025-04-17 19:18:16 +0800918 gpiokey_pmx_func: gpiokey_pmx_func {
919 pinctrl-single,pins = <
920 GPIO09 AF0
921 >;
922 DS_MEDIUM;PULL_UP;EDGE_NONE;SL_NORMAL;
923 };
b.liub17525e2025-05-14 17:22:29 +0800924
925 wake_pmx_func1: wake_pmx_func1 {
926 pinctrl-single,pins = <
927 USB_ID AF1
928 >;
929 DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL;
930 };
931
hong.liuf2416882025-05-23 20:41:06 -0700932 led_pmx_func1: led_pmx_func1 {
933 pinctrl-single,pins = <
934 GPIO08 AF0
935 >;
936 DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL;
937 };
938
b.liub17525e2025-05-14 17:22:29 +0800939
940 wake_pmx_func: wake_pmx_func {
941 pinctrl-single,pins = <
942 PRI_TDI AF1 /*GPIO117 WAKEUP_OUT*/
943
944 PRI_TMS AF1 /*GPIO118 WAKEUP_IN*/
945 GPIO41 AF0
946 PRI_TDO AF1 /*GPIO120*/
947
948
949 >;
950 DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL;
951 };
952 wake_pmx_func_sleep: wake_pmx_func_sleep {
953 pinctrl-single,pins = <
954 PRI_TDI AF1 /*GPIO117 WAKEUP_OUT*/
955
956 PRI_TMS AF1 /*GPIO118 WAKEUP_IN*/
957 GPIO41 AF0
958 PRI_TDO AF1 /*GPIO120*/
959
960 >;
961 DS_MEDIUM;PULL_NONE;EDGE_BOTH;SL_NORMAL;
962 };
963 usb_id_pinmux: usb_id_pinmux {
b.liue9582032025-04-17 19:18:16 +0800964 pinctrl-single,pins = <
965 USB_ID AF1/* usbid-gpio99 */
966 >;
967 DS_MEDIUM;PULL_UP;EDGE_NONE;LPM_NONE;
968 };
969 usb_id_pinmux_slp: usb_id_pinmux_slp {
970 pinctrl-single,pins = <
971 USB_ID AF1 /* usbid-gpio99 */
972 >;
973 DS_MEDIUM;PULL_UP;EDGE_BOTH;LPM_NONE;
974 };
975 usb_host_pinmux: usb_host_pinmux {
976 pinctrl-single,pins = <
977 VBUS_DRV AF1 /* gpio-122 */
978 >;
979 DS_MEDIUM;PULL_FLOAT;EDGE_NONE;LPM_NONE;
980 };
981 i2s_func: i2s_func {
982 pinctrl-single,pins = <
983 GPIO25 AF2
984 GPIO26 AF2
985 GPIO27 AF2
986 GPIO28 AF2
987 >;
988 MFP_DEFAULT;
989 };
990 i2s_gpio: i2s_gpio {
991 pinctrl-single,pins = <
992 GPIO25 AF0
993 GPIO26 AF0
994 GPIO27 AF0
995 GPIO28 AF0
996 >;
997 MFP_LPM_FLOAT;
998 };
you.chen9824a892025-06-04 20:23:26 +0800999 sensors_int:sensors_int {
1000 pinctrl-single,pins = <
1001 GPIO22 AF0
1002 >;
1003 MFP_PULL_DOWN;
1004 };
1005 sensors_csb:sensors_csb {
1006 pinctrl-single,pins = <
1007 VCXO_OUT AF1
1008 >;
1009 DS_MEDIUM;PULL_UP;EDGE_NONE;
1010 };
b.liue9582032025-04-17 19:18:16 +08001011 };
1012
1013 ssp0: spi@d401b000 {
1014 status = "okay";
1015 pinctrl-names = "default";
1016 pinctrl-0 = <&ssp0_pmx_func>;
1017 asr,spi-inc-mode;
1018#ifdef CONFIG_FB_SPI_LCD
1019 /* this enhancemnet feature is not suitable for
1020 3 line 9bits spi lcd. */
1021 /* asr,ssp-enhancement; */
1022
1023 lcd: spidev@0 {
1024 #address-cells = <1>;
1025 #size-cells = <1>;
1026 compatible = "spilcd";
b.liub17525e2025-05-14 17:22:29 +08001027 // pinctrl-names = "default";
1028 // pinctrl-0 = <&lcd_bl_func>;
b.liue9582032025-04-17 19:18:16 +08001029 reg = <0>;
1030 /* ST7735: need to set spi-max-frequency to 26M
1031 * ST7789V: can set spi-max-frequency to 52M
1032 */
1033 spi-max-frequency = <26000000>;
1034 xres = <128>;
1035 yres = <128>;
1036 bits = <8>; /* 8: 4line, 9: 3line */
1037 rst_gpio = <&gpio 24 0>;
b.liub17525e2025-05-14 17:22:29 +08001038 // bl_gpio = <&gpio 126 0>;
b.liue9582032025-04-17 19:18:16 +08001039 rs_gpio = <&gpio 22 0>;
1040 /* if comment the following statement, it means
1041 * the avdd is sit on the "always-on" ldo.
1042 */
1043 /* avdd-supply = <&LDO1>; */
1044 };
1045#else
1046 /*cs-gpios = <&gpio 34 0>;*//* DXS101 Use the config of Cs-gpios */
1047 slic: spidev@0{
1048 #address-cells = <1>;
1049 #size-cells = <1>;
1050 compatible = "asr,slic";
1051 reg = <0>;
1052 spi-cpol;
1053 spi-cpha;
1054 spi-max-frequency = <6500000>;
1055 };
1056#endif
1057 };
b.liub17525e2025-05-14 17:22:29 +08001058 ssp2: spi@d401c000{
1059 status = "okay";
1060 pinctrl-names = "default";
1061 pinctrl-0 = <&ssp2_pmx_func>;
1062 asr,spi-inc-mode;
1063 cs-gpios = <&gpio 39 0>;
1064 status = "okay";
1065 mbtk: spidev@0{
1066 compatible = "asr,spidev";
1067 reg = <0>;
1068 status = "okay";
1069 spi-cpol;
1070 spi-cpha;
1071 spi-max-frequency = <6500000>;
1072 };
1073 };
b.liue9582032025-04-17 19:18:16 +08001074 twsi0: i2c@d4011000 {
1075 status= "okay";
1076 alc5616@1b {
b.liub17525e2025-05-14 17:22:29 +08001077 status= "disabled";
b.liue9582032025-04-17 19:18:16 +08001078 compatible = "asrmicro,alc5616";
1079 reg = <0x1b>;
1080 pinctrl-names = "default", "sleep";
1081 pinctrl-0 = <&alc5616_pmx_func1>;
1082 pinctrl-1 = <&alc5616_pmx_func2>;
1083 clocks = <&soc_clocks ASR1803_CLK_I2S_SYSCLK>;
1084 clock-names = "i2s_sys_clk";
1085#if 0
1086 3V3-gpio = <&gpio 23 0>;/* CODEC_LDO_EN */
1087 irq-gpio = <&gpio 24 0>;/* CODEC_IRQ for headset detection */
1088#else
1089 irq-gpio = <&gpio 8 0>;/* CODEC_IRQ for headset detection */
1090#endif
1091 };
1092
b.liub17525e2025-05-14 17:22:29 +08001093 nau8810@1a {
1094 compatible = "marvell,nau8810";
1095 clocks = <&soc_clocks ASR1803_CLK_I2S_SYSCLK>;
1096 clock-names = "i2s_sys_clk";
1097
1098
1099 pinctrl-names = "default";
1100 pinctrl-0 = <&es8311_pa_func1>;
1101 pinctrl-1 = <&es8311_pa_func2>;
1102 reg = <0x1a>;
1103 status= "disabled";
1104 };
1105
1106 es8311@18 {
1107 compatible = "ambarella,es8311";
1108 reg = <0x18>;
1109 clocks = <&soc_clocks ASR1803_CLK_I2S_SYSCLK>;
1110 clock-names = "i2s_sys_clk";
1111
1112 pinctrl-names = "default";
1113 pinctrl-0 = <&es8311_pa_func1>;
1114 pinctrl-1 = <&es8311_pa_func2>;
1115
1116 // gpios = <&gpio 21 0>,
1117 // <&gpio 23 0>,
1118 // <&gpio 24 0>,
1119 // <&gpio 22 0>;
1120
1121 status= "okay";
1122 };
1123
you.chen9824a892025-06-04 20:23:26 +08001124 asm330lhhx-imu@0x6a {
1125 compatible = "st,asm330lhhx";
1126 reg = <0x6b>;
1127 pinctrl-names = "default";
1128 pinctrl-0 = <&sensors_int &sensors_csb>;
1129 interrupt-parent = <&gpio>;
1130 interrupts = <22 1>;
1131 //interrupts = <22>;
1132 vddio-supply = <&sensors_vddio>;
1133 //vdd-supply = <&sensors_vdd>;
1134 st,int-pin = <1>;
1135 //st,mlc-int-pin = <2>;
1136 mount-matrix = "1", "0", "0",
1137 "0", "1", "0",
1138 "0", "0", "1";
1139 };
yu.dongb39db3e2025-06-06 03:15:42 -07001140 /* AWINIC AW87XXX Smart K PA */
1141 aw87xxx_pa@58 {
1142 compatible = "awinic,aw87xxx_pa";
1143 reg = <0x58>;
1144 reset-gpio = <&gpio 24 0>;
1145 dev_index = < 0 >;
1146 status = "okay";
1147 };
1148 /* AWINIC AW87XXX Smart K PA End */
b.liue9582032025-04-17 19:18:16 +08001149 /*
1150 pmic4: 88pm805@38 {
1151 compatible = "marvell,88pm805";
1152 reg = <0x38>;
1153 };
1154 */
1155 };
1156 twsi1: i2c@d4010800 {
b.liub17525e2025-05-14 17:22:29 +08001157#if 1
b.liue9582032025-04-17 19:18:16 +08001158 pinctrl-names = "default","gpio";
1159 pinctrl-0 = <&twsi1_pmx_func>;
1160 pinctrl-1 = <&twsi1_pmx_gpio>;
1161 i2c-gpio = <&gpio 10 0 &gpio 11 0>;
1162#endif
b.liub17525e2025-05-14 17:22:29 +08001163 status= "okay";
1164 //nau8810@1a {
1165 // compatible = "marvell,nau8810";
1166 // reg = <0x1a>;
1167 //};
1168
1169
b.liue9582032025-04-17 19:18:16 +08001170 };
1171 twsi2: i2c@d4037000 {
1172 status = "okay";
1173
1174 pmic4: 88pm805@38 {
1175 compatible = "marvell,88pm805";
1176 reg = <0x38>;
1177 };
1178
1179 pmic5: pm802@0 {
1180 compatible = "asr,pm802";
1181 reg = <0x00>;
1182 interrupts = <4>;
1183 interrupt-parent = <&intc>;
1184 interrupt-controller;
1185 #interrupt-cells = <1>;
1186 chg_irq_from_exton;
1187 scs-int-active-high;
1188 battery {
1189 compatible = "asr,pm802-bat";
1190 status = "disabled";
1191
1192 online-gpadc = <1>;
1193 temperature-gpadc = <1>;
1194
1195 hi-volt-online = <1150>; /* mV */
1196 lo-volt-online = <20>; /* mV */
1197 hi-volt-temp = <1150>; /* mV */
1198 lo-volt-temp = <200>; /* mV */
1199
1200 sw-fg-use-ntc;
1201 full-capacity = <2050>; /* mAh */
1202 r1-resistor = <40>; /* mohm */
1203 r2-resistor = <30>; /* mohm */
1204 rs-resistor = <120>; /* mohm */
1205 roff-resistor = <0>; /* mohm */
1206 roff-initial-resistor = <0>; /* mohm */
1207
1208 times-in-zero-degree = <1>;
1209 offset-in-zero-degree = <0>;
1210
1211 times-in-ten-degree = <2>;
1212 offset-in-ten-degree = <100>;
1213
1214 power-off-threshold = <3350>; /* mV */
1215 safe-power-off-threshold = <3200>; /* mV */
1216
1217 online-gp-bias-curr = <11>; /* uA */
1218
1219 soc-ramp-up-interval = <150>; /* s */
1220 /* choose -20C, 0C, 10C, 40C, 45C, 55C as threshold */
1221 tbat-threshold = <20 0 10 40 45 55>; /* ohm */
1222 ntc-table-size = <88>;
1223 stop-chg-for-vbatmeas;
1224 /* -24C, -23C, ..., 62C, 63C */
1225 ntc-table = <
1226 89680 85130 80840 76790 72970 69360 65960 62740
1227 59700 56830 54130 51530 49100 46800 44610 42550
1228 40590 38730 36970 35300 33710 32210 30780 29420
1229 28130 26910 25750 24640 23590 22580 21630 20720
1230 19860 19030 18250 17500 16790 16110 15460 14840
1231 14250 13690 13150 12640 12150 11680 11230 10800
1232 10390 10000 9620 9270 8920 8590 8280 7980
1233 7690 7410 7150 6890 6650 6410 6190 5970
1234 5770 5570 5380 5190 5020 4850 4680 4530
1235 4380 4230 4100 3960 3830 3710 3590 3480
1236 3370 3260 3160 3060 2960 2870 2780 2700
1237 >;
1238 };
1239 usb {
1240 status = "disabled";
1241 vbus_gpio = <0xff>; /* set_vbus */
1242 id-gpadc = <0xff>; /* usb-id */
1243 vchg-from-exton = <1>;
1244 vbus-detect = <1>; /* vbus-irq */
1245 get-vbus = <1>; /* get-vbus */
1246 };
1247 };
1248 pmic6: pm803@30 {
1249 compatible = "asr,pm803";
1250 reg = <0x30>;
1251 interrupts = <4>;
1252 interrupt-parent = <&intc>;
1253 interrupt-controller;
1254 #interrupt-cells = <1>;
1255 chg_irq_from_exton;
1256 scs-int-active-high;
1257 battery {
1258 compatible = "asr,pm803-bat";
1259 status = "disabled";
1260
1261 online-gpadc = <1>;
1262 temperature-gpadc = <1>;
1263
1264 hi-volt-online = <1150>; /* mV */
1265 lo-volt-online = <20>; /* mV */
1266 hi-volt-temp = <1150>; /* mV */
1267 lo-volt-temp = <200>; /* mV */
1268
1269 sw-fg-use-ntc;
1270 full-capacity = <2050>; /* mAh */
1271 r1-resistor = <40>; /* mohm */
1272 r2-resistor = <30>; /* mohm */
1273 rs-resistor = <120>; /* mohm */
1274 roff-resistor = <0>; /* mohm */
1275 roff-initial-resistor = <0>; /* mohm */
1276
1277 times-in-zero-degree = <1>;
1278 offset-in-zero-degree = <0>;
1279
1280 times-in-ten-degree = <2>;
1281 offset-in-ten-degree = <100>;
1282
1283 power-off-threshold = <3350>; /* mV */
1284 safe-power-off-threshold = <3200>; /* mV */
1285
1286 online-gp-bias-curr = <11>; /* uA */
1287
1288 soc-ramp-up-interval = <150>; /* s */
1289 /* choose -20C, 0C, 10C, 40C, 45C, 55C as threshold */
1290 tbat-threshold = <20 0 10 40 45 55>; /* ohm */
1291 ntc-table-size = <88>;
1292 stop-chg-for-vbatmeas;
1293 /* -24C, -23C, ..., 62C, 63C */
1294 ntc-table = <
1295 89680 85130 80840 76790 72970 69360 65960 62740
1296 59700 56830 54130 51530 49100 46800 44610 42550
1297 40590 38730 36970 35300 33710 32210 30780 29420
1298 28130 26910 25750 24640 23590 22580 21630 20720
1299 19860 19030 18250 17500 16790 16110 15460 14840
1300 14250 13690 13150 12640 12150 11680 11230 10800
1301 10390 10000 9620 9270 8920 8590 8280 7980
1302 7690 7410 7150 6890 6650 6410 6190 5970
1303 5770 5570 5380 5190 5020 4850 4680 4530
1304 4380 4230 4100 3960 3830 3710 3590 3480
1305 3370 3260 3160 3060 2960 2870 2780 2700
1306 >;
1307 };
1308 usb {
1309 status = "disabled";
1310 vbus_gpio = <0xff>; /* set_vbus */
1311 id-gpadc = <0xff>; /* usb-id */
1312 vchg-from-exton = <1>;
1313 vbus-detect = <1>; /* vbus-irq */
1314 get-vbus = <1>; /* get-vbus */
1315 };
1316 };
1317 };
1318 };
1319 };
1320
1321 vcc_sdh1: sd-regulator {
1322 compatible = "regulator-fixed";
b.liub17525e2025-05-14 17:22:29 +08001323 /*pinctrl-names = "default";*/
1324 /*pinctrl-0 = <&sd_ldo_en>;*/
b.liue9582032025-04-17 19:18:16 +08001325 regulator-name = "SDH1 VCC";
1326 regulator-min-microvolt = <3300000>;
1327 regulator-max-microvolt = <3300000>;
b.liub17525e2025-05-14 17:22:29 +08001328 /* gpio = <&gpio 45 0>;*/
b.liue9582032025-04-17 19:18:16 +08001329 enable-active-high;
1330 status = "okay";
1331 };
1332
you.chen9824a892025-06-04 20:23:26 +08001333 sensors_vddio: imu-regulator {
1334 compatible = "regulator-fixed";
1335 /*pinctrl-names = "default";*/
1336 /*pinctrl-0 = <&sd_ldo_en>;*/
1337 regulator-name = "IMU VDDIO";
1338 gpio = <&gpio 21 0>;
1339 enable-active-high;
1340 status = "okay";
1341 };
1342
b.liue9582032025-04-17 19:18:16 +08001343 asr-rfkill {
1344 compatible = "asr,asr-rfkill";
1345 pinctrl-names = "off", "on";
1346 pinctrl-0 = <&sdh1_pmx_pd_rst_off>;
1347 pinctrl-1 = <&sdh1_pmx_pd_rst_on>;
b.liub17525e2025-05-14 17:22:29 +08001348 sd-host = <&sdh0>;
1349 //pd-gpio = <&gpio 90 0>;
1350 rst-gpio = <&gpio 90 0>;
1351
1352 /*3v3-ldo-gpio = <&gpio 8 0>;*/
1353 /*edge-wakeup-gpio = <&gpio 10 0>;*/
1354 status = "okay";
1355 };
1356
1357 mbtk-sdh{
1358 compatible = "mbtk,mbtk-sdh";
1359 pinctrl-names = "off", "on";
1360 pinctrl-0 = <&mbtk_sdh_pmx_off>;
1361 pinctrl-1 = <&mbtk_sdh_pmx_on>;
1362 sd-host = <&sdh1>;
1363 1v8-ldo-gpio = <&gpio 123 0>;
you.chen9824a892025-06-04 20:23:26 +08001364 //host-wakeup-wlan-gpio = <&gpio 127 0>;
b.liub17525e2025-05-14 17:22:29 +08001365 wlan_en_gpio = <&gpio 125 0>;
1366 status = "okay";
1367 };
1368
1369 asr-gps {
1370 compatible = "asr,asr-gnss";
1371 pinctrl-names = "default";
1372 pinctrl-0 = <&gnss_clk_on>;
1373 enable_vctcxo_out1;
1374 host-wakeup-gnss-gpio = <&gpio 47 0>;
1375 /*gnss-wakeup-host-gpio = <&gpio 47 0>;*/
1376 rst-gpio = <&gpio 45 0>;
b.liue9582032025-04-17 19:18:16 +08001377 status = "okay";
1378 };
1379
1380 pcie-rfkill {
1381 compatible = "mrvl,pcie-rfkill";
1382 pinctrl-names = "off", "on";
1383 pinctrl-0 = <&pcie_pmx_pd_rst_off>;
1384 pinctrl-1 = <&pcie_pmx_pd_rst_on>;
1385 rst-gpio = <&gpio 42 0>;
1386 3v3-ldo-gpio = <&gpio 24 0>;
b.liub17525e2025-05-14 17:22:29 +08001387 status = "disabled";
b.liue9582032025-04-17 19:18:16 +08001388 };
1389
1390 sound {
1391 compatible = "ASRMICRO,asrmicro-snd-card";
1392 ssp-controllers = <&ssp_dai1>;
1393 };
1394
b.liub17525e2025-05-14 17:22:29 +08001395 asr-adc {
1396 compatible = "asr,adc";
1397 //pinctrl-names = "default";
1398 //pinctrl-0 = <&pin_func_work>;
1399 status = "okay";
1400 };
1401
1402#if 0
1403
1404 mbtk_PlatIrq{
1405 compatible = "mbtk,plat-irq";
1406 pinctrl-names = "sc_irq0", "sc_irq1", "sc_irq2", "sc_irq3";
1407
1408 pinctrl-0 = <&sc_ext_int0>;
1409 pinctrl-1 = <&sc_ext_int1>;
1410 pinctrl-2 = <&sc_ext_int2>;
1411 pinctrl-3 = <&sc_ext_int3>;
yu.dongca721ca2025-06-04 07:21:21 -07001412 status = "disabled";
b.liub17525e2025-05-14 17:22:29 +08001413 };
1414
1415#else
1416
1417 mbtk_PlatIrq{
1418 compatible = "mbtk,plat-irq";
1419 pinctrl-names = "default", "sleep";
1420 pinctrl-0 = <&mbtk_plat_irq_func>;
1421 pinctrl-1 = <&mbtk_plat_irq_func_sleep>;
you.chen9824a892025-06-04 20:23:26 +08001422 //gpio_irq0 = <&gpio 21 0>;
1423 //gpio_irq1 = <&gpio 22 0>;
b.liub17525e2025-05-14 17:22:29 +08001424 gpio_irq2 = <&gpio 23 0>;
1425 gpio_irq3 = <&gpio 24 0>;
yu.dongca721ca2025-06-04 07:21:21 -07001426 status = "disabled";
b.liub17525e2025-05-14 17:22:29 +08001427 };
1428
1429#endif
1430
b.liue9582032025-04-17 19:18:16 +08001431 ecall {
1432 compatible = "asr,ecall-event";
1433 pinctrl-names = "default";
1434 pinctrl-0 = <&ecall_pmx_func>;
1435 gpio-auto-ecall = <8>;
1436 gpio-manual-ecall = <9>;
1437 status = "disabled";
1438 };
1439
1440 usim1: usim1 {
1441 compatible = "asr,usim1";
1442 pinctrl-names = "default", "sleep";
1443 pinctrl-0 = <&usim1_pmx_func>;
1444 pinctrl-1 = <&usim1_pmx_func_sleep>;
yq.wang107f9862025-05-12 15:44:50 +08001445 edge_detect_gpio = <119>; /* GPIO19: SIM detect pin */
b.liue9582032025-04-17 19:18:16 +08001446 status = "okay";
1447 };
1448 /* set okay for this node if usim2 is needed */
1449 usim2: usim2 {
1450 compatible = "asr,usim2";
1451 pinctrl-names = "default", "sleep";
1452 pinctrl-0 = <&usim2_pmx_func>;
1453 pinctrl-1 = <&usim2_pmx_func_sleep>;
1454 edge_detect_gpio = <44>; /* GPIO44: SIM detect pin */
1455#ifdef CONFIG_ASR_DSDS
1456 status = "okay";
1457#else
1458 status = "disabled";
1459#endif
1460 };
1461 gpio_keys {
1462 compatible = "gpio-keys";
1463 #address-cells = <1>;
1464 #size-cells = <0>;
1465 /* autorepeat; */
1466 pinctrl-names = "default";
1467 pinctrl-0 = <&gpiokey_pmx_func>;
1468 button@1 {
1469 label = "qrcode-key";
1470 linux,code = <139>; /* KEY_MENU, refer to linux/input.h */
1471 /* NOTE:
1472 * We use the FORCE DOWNLOAD key to implement the qrcode key in DKB.
1473 * Customer SHOULD change it to any other gpios.
1474 * Because user may do the misoperation that
1475 * powerup with FDL key pressed,
1476 * then the borad will enter force download mode.
1477 */
1478 gpios = <&gpio 9 1>;
1479 gpio-key,wakeup;
1480 };
1481 };
1482
1483 audio_pa {
1484 compatible = "asrmicro,audio-pa";
1485 pinctrl-names = "default";
1486 pinctrl-0 = <&audio_pa_pmx_func>;
1487 pa-gpio = <&gpio 14 0>;
b.liub17525e2025-05-14 17:22:29 +08001488 status = "disabled";
b.liue9582032025-04-17 19:18:16 +08001489 };
b.liub17525e2025-05-14 17:22:29 +08001490 mbtk_GpioWakeUp {
1491 compatible = "mbtk,GpioWakeUp";
1492 pinctrl-names = "default", "sleep";
1493 pinctrl-0 = <&wake_pmx_func &wake_pmx_func1>;
1494 pinctrl-1 = <&wake_pmx_func_sleep>;
1495 wakeup-in-gpio = <&gpio 118 0>;
1496 wakeup-out-gpio = <&gpio 117 0>;
1497 status = "okay";
1498 };
b.liue9582032025-04-17 19:18:16 +08001499
hong.liuf2416882025-05-23 20:41:06 -07001500
1501 dtsleds{
1502 compatible = "gpio-leds";
1503 pinctrl-names = "default";
1504 pinctrl-0 = <&led_pmx_func1>;
1505 status = "okay";
1506 led0{
1507 label = "red";
1508 gpios = <&gpio 8 0>;
1509 linux,default-trigger = "pattern";
1510 led-pattern = "100:100:100";
1511 default-state = "on";
1512
1513 };
1514
1515 // led1{
1516 // label = "blue";
1517 // gpios = <&gpio 99 0>;
1518 // linux,default-trigger = "timer";
1519 // timer-delay-on = <100>;
1520 // timer-delay-off = <100>;
1521 // brightness-levels = <100>;
1522 // brightness-max = <100>;
1523 // default-state = "on";
1524 // };
1525
1526 };
1527
b.liue9582032025-04-17 19:18:16 +08001528 audio_regs {
1529 compatible = "ASRMICRO,audio-registers";
1530 reg = <0xD4050044 0x4>;
1531 status = "okay";
1532 };
1533
1534 nz3-slic {
1535 compatible = "asr,nz3-slic";
1536 pinctrl-names = "default", "sleep";
1537 pinctrl-0 = <&slic_pmx_func1 &slic_pmx_func2>;
1538 pinctrl-1 = <&slic_pmx_func1_sleep &slic_pmx_func2>;
1539 rst-gpio = <&gpio 21 0>;
1540 edge-wakeup-gpio = <&gpio 20 0>;
1541 vdd-3v3-gpio = <&gpio 127 0>;
1542 status = "disabled";
1543 };
1544 microsemi-slic {
1545 compatible = "asr,microsemi-slic";
1546 pinctrl-names = "default", "sleep";
1547 pinctrl-0 = <&slic_pmx_func1>;
1548 pinctrl-1 = <&slic_pmx_func1_sleep>;
1549 edge-wakeup-gpio = <&gpio 20 0>;
1550 vdd-3v3-gpio = <&gpio 127 0>;
1551 status = "disabled";
1552 };
1553 maxlinear-slic {
1554 compatible = "asr,maxlinear-slic";
1555 pinctrl-names = "default", "sleep";
1556 pinctrl-0 = <&slic_pmx_func1 &slic_pmx_func2>;
1557 pinctrl-1 = <&slic_pmx_func1_sleep &slic_pmx_func2>;
1558 rst-gpio = <&gpio 21 0>;
1559 edge-wakeup-gpio = <&gpio 20 0>;
1560 vdd-3v3-gpio = <&gpio 127 0>;
1561 status = "disabled";
1562 };
1563 /* deprecated, move to mfpr@d401e000
1564 lpm-board-cfg {
1565 compatible = "asr,lpm-board-cfg";
1566 wakeup-state-d1pp = <0x1>;
1567 udr-mfpr-config = <0x1B0 0xA040 0x0
1568 0x1B4 0xA040 0x0>;
1569 };
1570 */
1571};
1572#ifdef CONFIG_ASR_DSDS
1573#include "asr_pm802_2usim.dtsi"
1574#include "88pm805.dtsi"
1575#include "asr_pm803_2usim.dtsi"
1576#else
1577#include "asr_pm802.dtsi"
1578#include "88pm805.dtsi"
1579#include "asr_pm803.dtsi"
1580#endif
1581
1582#ifdef CONFIG_AB_SYSTEM
1583#include "asr1806_ab_flash_layout.dtsi"
1584#else
1585#include "asr1806_flash_layout.dtsi"
1586#endif