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b.liue9582032025-04-17 19:18:16 +08001// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2023 ASR Microelectronics Co., Ltd.
4 */
5
6/dts-v1/;
7#include "asr1806.dtsi"
8
9/ {
10 model = "ASR 1806(FALCON-T) Board EVB";
11 compatible = "asr,1803-evb", "asr,1803";
12
13 chosen {
14 bootargs = "root=/dev/mtdblock5 rootfstype=squashfs init=/etc/preinit noinitrd console=ttyS0,115200 mem=128M";
15 };
16
17 memory {
18 reg = <0x00000000 0x10000000>;
19 };
20
21 firmware {
22 optee {
23 compatible = "linaro,optee-tz";
24 method = "smc";
25 };
26 };
27
28 soc {
29 axi@d4200000 { /* AXI */
30 usbphy: usbphy@d4207000 {
31 status = "okay";
32 };
33#ifdef CONFIG_USB_DWC2_ASR_OTG /* otg mode */
34 usb: usb@c0000000 {
35 dr_mode = "otg";
36 pinctrl-names = "default","sleep";
37 pinctrl-0 = <&usb_id_pinmux &usb_host_pinmux>;
38 pinctrl-1 = <&usb_id_pinmux_slp &usb_host_pinmux>;
39 usbid_gpio = <99>;
40 edge_detect_gpio = <99>;
41 otg,use-gpio-vbus;
42 gpio-num = <122>;
43 status = "okay";
44 };
45#else
46 usb: usb@c0000000 {
47 status = "okay";
48 };
49#endif
50
51 eth0: asr-eth@0xd4281800 {
52 compatible = "asr,asr-eth";
53 pinctrl-names = "default", "rgmii-pins";
54 pinctrl-0 = <&emac_pmx_func0 &emac_pmx_func2 &emac_pmx_func3>;
55 pinctrl-1 = <&emac_pmx_func0 &emac_pmx_func1 &emac_pmx_func2 &emac_pmx_func3>;
56 reg = <0xd4281800 0x200>;
57 interrupts = <10 11>;
58 lpm-qos = <PM_QOS_CPUIDLE_BLOCK_AXI>;
59 clocks = <&soc_clocks ASR1803_CLK_EMAC
60 &soc_clocks ASR1803_CLK_EMAC_PTP>;
61 clock-names = "emac-clk", "ptp-clk";
62 ptp-support;
63 ptp-clk-rate = <100000000>;
64 status = "okay";
b.liub17525e2025-05-14 17:22:29 +080065 enable-suspend;
hj.shaof72d6ff2025-06-10 04:34:26 -070066 // reset-gpio = <&gpio 42 0>;
67 // reset-active-low;
68 // reset-delays-us = <100000 100000 100000>;
69 local-mac-address = [02 00 00 00 10 01];
b.liub17525e2025-05-14 17:22:29 +080070 //ldo-gpio = <&gpio 40 0>;
71 //ldo-active-low;
72 // ldo-delays-us = <0 100000 100000>;
73 //vmmc-supply = <0x19>;
74 mdio-clk-div = <254>;
b.liue9582032025-04-17 19:18:16 +080075 flow-control-threshold = <60 90>;
76 clk-tuning-enable;
77 /* clk-config(32bit)
78 *
79 * clk_sel(clk-config[23:16])
80 * RGMII:
81 * tx | clk_sel: 0 - from external RX clock
82 * 1 - from inverted external RX clock
83 * rx | clk_sel: 0 - from external RX clock
84 * 1 - from inverted external RX clock
85 *
86 * RMII:
87 * tx | clk_sel: 0 - RMII clock
88 * 1 - Inverted RMII clock
89 * rx | clk_sel: 0 - RMII clock
90 * 1 - Inverted RMII clock
91 *
92 */
93#if 0
94 /* enable 1000M phy*/
95 3v3-enable = <0>; /* IO voltage, 1 - 3.3v, 0 - 1.8v */
b.liub17525e2025-05-14 17:22:29 +080096 phy-handle = <&phy3>;
b.liue9582032025-04-17 19:18:16 +080097#else
98 /* enable 100M phy*/
b.liub17525e2025-05-14 17:22:29 +080099 3v3-enable = <0>; /* IO voltage, 1 - 3.3v, 0 - 1.8v */
hj.shaofe1632a2025-06-05 00:19:33 -0700100 phy-handle = <&phy0>;
b.liue9582032025-04-17 19:18:16 +0800101#endif
102 /* enable fix link for ethernet switch */
103 /*
104 fixed-link {
105 speed = <100>;
106 full-duplex;
107 phy-mode = "rmii";
108 };
109 */
110
111 mdio: mdio-bus {
112 #address-cells = <0x1>;
113 #size-cells = <0x0>;
114 /* YT8521 10M/100M/100OM 1.8V RGMII PHY */
115 phy0: phy@0 {
116 compatible = "ethernet-phy-ieee802.3-c22";
117 device_type = "ethernet-phy";
118 reg = <0x0>; /* set phy address*/
hj.shaof72d6ff2025-06-10 04:34:26 -0700119 rst-gpio = <&gpio 42 0>;
hj.shaofb3ba9b2025-06-19 02:53:56 -0700120 //#LYNQ_MODFIY modify for task-1618 2025/6/19 start
121 power-en-gpio = <&gpio 32 1>;
122 //#LYNQ_MODFIY modify for task-1618 2025/6/19 end
b.liue9582032025-04-17 19:18:16 +0800123 phy-mode = "rgmii";
hj.shaofe1632a2025-06-05 00:19:33 -0700124 // tx_rx_delay = <0xb 0x0>; /* 150ps per step*/
b.liue9582032025-04-17 19:18:16 +0800125 };
126
127 /* YT8512B 10M/100M 3.3V RMII PHY */
b.liub17525e2025-05-14 17:22:29 +0800128 // phy3: phy@3 {
129 // compatible = "ethernet-phy-ieee802.3-c22";
130 // device_type = "ethernet-phy";
131 // reg = <0x3>; /* set phy address*/
132 // phy-mode = "rmii";
133 // driver_strength = <0x3>;
134 // };
b.liue9582032025-04-17 19:18:16 +0800135
136 /* IP175D 10M/100M 3.3V RMII SWITCH */
137 phy1: phy@1 {
138 compatible = "ethernet-phy-ieee802.3-c22";
139 device_type = "ethernet-phy";
140 reg = <0x1>; /* set phy address*/
141 phy-mode = "rmii";
142 };
b.liub17525e2025-05-14 17:22:29 +0800143
144
145 /* jl 3103 phy */
146 phy3: phy@3 {
147 compatible = "ethernet-phy-ieee802.3-c22";
148 device_type = "ethernet-phy";
149 reg = <0x3>; /* set phy address*/
150 phy-mode = "rgmii-id";
151 lynq,jl3103=<100 0>;
152 };
b.liue9582032025-04-17 19:18:16 +0800153 };
154 };
155 qspi: spi@0xd420b000 {
156 asr,qspi-freq = <78000000>;
157 status = "okay";
158 };
zw.wang3ef3a312025-06-13 16:21:25 +0800159
160#if 0
b.liue9582032025-04-17 19:18:16 +0800161 /* SD card */
162 sdh0: sdh@d4280000 {
163 pinctrl-names = "default", "slow", "fast", "sleep";
164 pinctrl-0 = <&sdh0_pmx_func1 &sdh0_pmx_func2 &sdh0_pmx_func3>;
165 pinctrl-1 = <&sdh0_pmx_func1_slow &sdh0_pmx_func2_slow &sdh0_pmx_func3>;
166 pinctrl-2 = <&sdh0_pmx_func1_fast &sdh0_pmx_func2_fast &sdh0_pmx_func3>;
167 pinctrl-3 = <&sdh0_pmx_cd_wakeup>;
168 /*
169 * Genernal use, juse set vmmc-supply and vqmmc-supply
170 * vmmc-supply = <&supply1>
171 * vqmmc-supply = <&supply2>
172 *
173 * For compatibility, to select one from two supply source
174 * vmmc-supply = <&supply1 &supply1_backup>;
175 * vqmmc-supply = <&supply2 &supply2_backup>;
176 * vmmc2-supply = <&supply1_backup &supply1>;
177 * vqmmc2-supply = <&supply2_backup &supply2>;
178 */
179 vmmc-supply = <&vcc_sdh1>;
zw.wang5deb3e82025-05-30 11:29:23 +0800180 vqmmc-supply = <&pm802ldo6 &pm803ldo8>;
b.liue9582032025-04-17 19:18:16 +0800181#ifndef CONFIG_ASR_DSDS
182 vmmc2-supply = <&vcc_sdh1 &pm802ldo4>;
183 vqmmc2-supply = <&pm803ldo8 &pm802ldo6>;
184#endif
185 bus-width = <4>;
186 no-mmc;
187 no-sdio;
188 /*non-removable;
189 broken-cd;*/
190 wp-inverted;
191 asr,sdh-pm-runtime-en;
192 asr,sdh-host-caps-disable = <(MMC_CAP_UHS_SDR104)>;
193#if 1 /* CD via gpio */
zw.wang5deb3e82025-05-30 11:29:23 +0800194 //cd-gpios = <&gpio 90 1>;
b.liue9582032025-04-17 19:18:16 +0800195 asr,sdh-quirks2 = <(
196 SDHCI_QUIRK2_SET_AIB_MMC |
197 SDHCI_QUIRK2_PRESET_VALUE_BROKEN
198 )>;
199 asr,sdh-host-caps = <(
200 MMC_CAP_CD_WAKE
201 )>;
202 asr,sdh-quirks = <(
203 SDHCI_QUIRK_BROKEN_CARD_DETECTION |
204 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
205 )>;
206#else /* CD via SDH */
207 asr,sdh-quirks = <(
208 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
209 )>;
210 asr,sdh-quirks2 = <(
211 SDHCI_QUIRK2_SET_AIB_MMC |
212 SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
213 SDHCI_QUIRK2_BASE_CLOCK_ALWAYS_ON
214 )>;
215#endif
216 /* prop "sdh-dtr-data":
217 <timing preset_rate src_rate tx_delay rx_delay tx_dline_reg rx_dline_reg> */
218 asr,sdh-dtr-data =
219 <PXA_MMC_TIMING_LEGACY PXA_SDH_DTR_26M PXA_SDH_DTR_104M 0 0 0 0>,
220 <PXA_MMC_TIMING_SD_HS PXA_SDH_DTR_52M PXA_SDH_DTR_104M 0 0 0 0>,
221 <PXA_MMC_TIMING_UHS_DDR50 PXA_SDH_DTR_52M PXA_SDH_DTR_104M 0 0 0 3>,
222 <PXA_MMC_TIMING_UHS_SDR50 PXA_SDH_DTR_104M PXA_SDH_DTR_208M 0 0 0 0>,
223 <PXA_MMC_TIMING_UHS_SDR104 PXA_SDH_DTR_208M PXA_SDH_DTR_208M 0 0 0 0>,
224 <PXA_MMC_TIMING_MAX PXA_SDH_DTR_PS_NONE PXA_SDH_DTR_104M 0 0 0 0>;
225 status = "okay";
226 };
zw.wang3ef3a312025-06-13 16:21:25 +0800227#endif
228 /* EMMC*/
229 sdh0: sdh@d4280000 {
230 pinctrl-names = "default", "slow", "fast";
231 pinctrl-0 = <&sdh0_pmx_func1 &sdh0_pmx_func2 &sdh0_pmx_func3>;
232 pinctrl-1 = <&sdh0_pmx_func1_slow &sdh0_pmx_func2_slow &sdh0_pmx_func3>;
233 pinctrl-2 = <&sdh0_pmx_func1_fast &sdh0_pmx_func2_fast &sdh0_pmx_func3>;
234 vmmc-supply = <&pm803ldo6 &pm803ldo8>;
235 bus-width = <4>;
236 no-sdio;
237 no-sd;
238 non-removable;
239 broken-cd;
240 wp-inverted;
241 asr,sdh-pm-runtime-en;
242 cap-mmc-highspeed;
243 mmc-ddr-1_8v;
244 asr,sdh-host-caps-disable = <(MMC_CAP_1_2V_DDR)>;
245 asr,sdh-host-caps2-disable = <(MMC_CAP2_HSX00_1_2V | MMC_CAP2_HS400 |MMC_CAP2_HS200)>;
246 asr,sdh-host-caps2 = <(
247 MMC_CAP2_ONLY_1_8V
248 )>;
249 asr,sdh-quirks = <(
250 SDHCI_QUIRK_BROKEN_CARD_DETECTION |
251 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
252 )>;
253 asr,sdh-quirks2 = <(
254 SDHCI_QUIRK2_SET_AIB_MMC |
255 SDHCI_QUIRK2_PRESET_VALUE_BROKEN
256 )>;
257 /* prop "sdh-dtr-data":
258 <timing preset_rate src_rate tx_delay rx_delay tx_dline_reg rx_dline_reg> */
259 asr,sdh-dtr-data =
260 <PXA_MMC_TIMING_LEGACY PXA_SDH_DTR_26M PXA_SDH_DTR_104M 0 0 0 0>,
261 <PXA_MMC_TIMING_MMC_HS PXA_SDH_DTR_52M PXA_SDH_DTR_104M 0 0 0 0>,
262 <PXA_MMC_TIMING_MMC_DDR52 PXA_SDH_DTR_52M PXA_SDH_DTR_104M 0 0 0 3>,
263 <PXA_MMC_TIMING_MMC_HS200 PXA_SDH_DTR_208M PXA_SDH_DTR_208M 53 0 0 0>,
264 <PXA_MMC_TIMING_MAX PXA_SDH_DTR_PS_NONE PXA_SDH_DTR_89M 0 0 0 0>;
265 status = "okay";
266 };
b.liue9582032025-04-17 19:18:16 +0800267
268 /* SDIO */
269 sdh1: sdh@d4280800 {
zw.wangad00beb2025-06-24 16:54:39 +0800270 pinctrl-names = "default", "fast", "sleep_sdio";
b.liub17525e2025-05-14 17:22:29 +0800271 pinctrl-0 = <&sdh1_pmx_func1 &sdh1_pmx_func2>;
272 pinctrl-1 = <&sdh1_pmx_func1_fast &sdh1_pmx_func2_fast>;
zw.wangad00beb2025-06-24 16:54:39 +0800273 pinctrl-2 = <&sdh1_pmx_func1_sleep_sdio &sdh1_pmx_func2_sleep_sdio>;
b.liub17525e2025-05-14 17:22:29 +0800274 /* pinctrl-2 = <&sdh1_pmx_edge_wakeup>;*/
b.liue9582032025-04-17 19:18:16 +0800275 bus-width = <4>;
276 no-mmc;
277 no-sd;
278 non-removable;
279 keep-power-in-suspend;
280 enable-sdio-wakeup;
281 /* clk-scaling-config:
282 <up_threshold down_threshold polling_interval> */
283 clk-scaling-config = <25 12 200>;
284 min-ddr-qos = <156000 312000 400000>;
285 asr,sdh-pm-runtime-en;
286 asr,sdh-quirks = <(
287 SDHCI_QUIRK_BROKEN_CARD_DETECTION |
288 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
289 )>;
290 asr,sdh-quirks2 = <(
291 SDHCI_QUIRK2_NO_TIMER_RETUNING |
292 SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
293 SDHCI_QUIRK2_BASE_CLOCK_ALWAYS_ON
294 )>;
295 asr,sdh-pm-caps = <(MMC_PM_KEEP_POWER)>;
296 asr,sdh-host-caps2 = <(
297 MMC_CAP2_ONLY_1_8V |
298 MMC_CAP2_DISABLE_PROBE_CDSCAN |
299 MMC_CAP2_CLK_SCALE |
300 MMC_CAP2_BUS_CLK_NO_SCALE
301 )>;
302 /* prop "sdh-dtr-data":
303 <timing preset_rate src_rate tx_delay rx_delay tx_dline_reg rx_dline_reg> */
304 asr,sdh-dtr-data =
305 <PXA_MMC_TIMING_LEGACY PXA_SDH_DTR_26M PXA_SDH_DTR_104M 0 0 0 0>,
306 <PXA_MMC_TIMING_SD_HS PXA_SDH_DTR_45M PXA_SDH_DTR_89M 0 0 0 0>,
307 <PXA_MMC_TIMING_UHS_DDR50 PXA_SDH_DTR_52M PXA_SDH_DTR_104M 0 0 0 3>,
308 <PXA_MMC_TIMING_UHS_SDR50 PXA_SDH_DTR_83M PXA_SDH_DTR_83M 0 0 0 3>,
b.liub17525e2025-05-14 17:22:29 +0800309 //<PXA_MMC_TIMING_UHS_SDR104 PXA_SDH_DTR_208M PXA_SDH_DTR_208M 0 0 0 0>,
310 <PXA_MMC_TIMING_UHS_SDR104 PXA_SDH_DTR_52M PXA_SDH_DTR_52M 0 0 0 0>,
b.liue9582032025-04-17 19:18:16 +0800311 <PXA_MMC_TIMING_MAX PXA_SDH_DTR_PS_NONE PXA_SDH_DTR_89M 0 0 0 0>;
312 status = "okay";
313 };
314 pcie0: pcie@0xd4288000{
315 reset-gpios = <&gpio 42 0 >;
b.liub17525e2025-05-14 17:22:29 +0800316 status = "disbabled";
b.liue9582032025-04-17 19:18:16 +0800317 };
318 pciephy0: pcie-phy@d4206000 {
319 status = "okay";
320 };
321 };
322
323 apb@d4000000 {
324 ssp_dai1: pxa-ssp-dai@1 {
325 compatible = "asr,pxa-ssp-dai";
326 reg = <0x1 0x0>;
327
328 port = <&ssp1>;
329 pinctrl-names = "default","ssp";
330 pinctrl-0 = <&i2s_gpio>;
331 pinctrl-1 = <&i2s_func>;
332 ssp-gpio = <&gpio 25 0 &gpio 26 0 &gpio 27 0 &gpio 28 0>;
333
334 dmas = <&pdma0 54 1
335 &pdma0 55 1>;
336 dma-names = "rx", "tx";
337
338 platform_driver_name = "pdma_platform";
339 burst_size = <4>;
340 playback_period_bytes = <2048>;
341 playback_buffer_bytes = <4096>;
342 capture_period_bytes = <2048>;
343 capture_buffer_bytes = <4096>;
344 };
345 mfpr: mfpr@d401e000 {
346 status = "okay";
347 /* intend to replace lpm-board-cfg
348 no-apbsd-in-d1pp = <0x1>; //"wakeup-state-d1pp"
349 pin1:pin1@d401e01B0 {
350 offset = <0x1B0>;
351 udr-cfg = <0xA040>;
352 };
353 pin2:pin2@d401e01B4 {
354 offset = <0x1B4>;
355 udr-cfg = <0xA040>;
356 };
357 */
358 };
359 timer0: timer@d4014000 {
360 status = "okay";
361 };
362 uart1: uart@d4017000 { /* nezhas evb use ap uart */
363 pinctrl-names = "default","sleep";
364 pinctrl-0 = <&uart1_pmx_func1 &uart1_pmx_func2>;
365 pinctrl-1 = <&uart1_pmx_func1_sleep &uart1_pmx_func2>;
b.liub17525e2025-05-14 17:22:29 +0800366 //edge-wakeup-gpio = <&gpio 29 0>; /* GPIO29: AP UART rx pin */
b.liue9582032025-04-17 19:18:16 +0800367 status = "okay";
368 };
369 uart2: uart@d4036000 {
370 pinctrl-names = "default";
hj.shao9f48a912025-06-11 00:19:29 -0700371
372 //#LYNQ_MODFIY modify for task-1618 2025/6/11 start
373 pinctrl-0 = <&gps_pmx_uart_rxd &gps_pmx_uart_txd>; //&gps_pmx_func_cts_rts>;
374 //#LYNQ_MODFIY modify for task-1618 2025/6/11 end
b.liue9582032025-04-17 19:18:16 +0800375 status = "okay";
376 };
377 uart3: uart@d4018000 {
378 pinctrl-names = "default";
379 pinctrl-0 = <&uart3_pmx_func>;
b.liub17525e2025-05-14 17:22:29 +0800380 status = "okay";
b.liue9582032025-04-17 19:18:16 +0800381 };
382 uart4: uart@d401f000 {
zw.wangad00beb2025-06-24 16:54:39 +0800383 pinctrl-names = "default","sleep";
b.liub17525e2025-05-14 17:22:29 +0800384 pinctrl-0 = <&uart4_pmx_func>; /*BAUD :9600*/
zw.wangad00beb2025-06-24 16:54:39 +0800385 pinctrl-1 = <&uart4_pmx_func_sleep>;
b.liub17525e2025-05-14 17:22:29 +0800386 /*pinctrl-0 = <&uart4_pmx_func_rxd &uart4_pmx_func_txd &uart4_pmx_func_cts_rts>;*/
387 status = "okay";
b.liue9582032025-04-17 19:18:16 +0800388 };
389 rtc: rtc@d4010000 {
390 status = "okay";
391 };
392 pmx: pinmux@d401e000 {
393 /* pin base = base_addr / 4, nr pins & gpio function */
394 pinctrl-single,gpio-range = <
395 /*
396 * GPIO number is hardcoded for range at here.
397 * In gpio chip, GPIO number is not hardcoded for range.
398 * Since one gpio pin may be routed to multiple pins,
399 * define these gpio range in pxa910-dkb.dts not pxa910.dtsi.
400 */
401 /*&range 80 4 0 */ /* GPIO25 ~ GPIO28 */
402 &range 55 32 0 /* GPIO0 ~ GPIO31 */
403 &range 87 32 0 /* GPIO32 ~ GPIO63 */
404 &range 119 32 0 /* GPIO64 ~ GPIO95 */
405 &range 151 32 0 /* GPIO96 ~ GPIO127 */
406 >;
407
408 ssp0_pmx_func: ssp0_pmx_func {
409 pinctrl-single,pins = <
410 GPIO36 AF1 /* TXD */
411 GPIO35 AF1 /* RXD */
412 GPIO34 AF1 /* FRM */
413 /*GPIO34 AF0*/ /* FRM *//* DXS101 Use the config of Cs-gpios */
414 GPIO33 AF1 /* SCLK */
415 >;
b.liub17525e2025-05-14 17:22:29 +0800416 DS_SLOW0;PULL_NONE;EDGE_NONE;SL_NORMAL; //DS_MEDIUM modify for overvoltage
417 };
418 ssp2_pmx_func: ssp2_pmx_func {
419 pinctrl-single,pins = <
420 GPIO37 AF3 /* TXD */
421 GPIO38 AF3 /* SCLK */
422 GPIO39 AF3 /* FRM */
423 GPIO40 AF3 /* RXD */
424 >;
425 DS_SLOW0;PULL_NONE;EDGE_NONE;SL_NORMAL; //DS_MEDIUM modify for overvoltage
b.liue9582032025-04-17 19:18:16 +0800426 };
427 lcd_bl_func: lcd_bl_func {
428 pinctrl-single,pins = <
b.liub17525e2025-05-14 17:22:29 +0800429 /* VCXO_OUT AF1 GPIO126, lcd bl */
430 /* GPIO24 AF0 reset */
431 /* GPIO22 AF0 lcd d/c */
b.liue9582032025-04-17 19:18:16 +0800432 >;
433 MFP_DEFAULT;
434 };
435 uart1_pmx_func1: uart1_pmx_func1 {
436 pinctrl-single,pins = <
437 GPIO29 AF1
438 >;
439 MFP_DEFAULT;
440 };
441 uart1_pmx_func2: uart1_pmx_func2 {
442 pinctrl-single,pins = <
443 GPIO30 AF1
444 >;
445 MFP_DEFAULT;
446 };
447 uart1_pmx_func1_sleep: uart1_pmx_func1_sleep {
448 pinctrl-single,pins = <
449 GPIO29 AF1
450 >;
b.liub17525e2025-05-14 17:22:29 +0800451 DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL;
b.liue9582032025-04-17 19:18:16 +0800452 };
453 twsi0_pmx_func: twsi0_pmx_func {
454 pinctrl-single,pins = <
455 GPIO49 AF1
456 GPIO50 AF1
457 >;
b.liub17525e2025-05-14 17:22:29 +0800458 DS_MEDIUM;PULL_NONE;EDGE_NONE;LPM_FLOAT;
b.liue9582032025-04-17 19:18:16 +0800459 };
460 twsi0_pmx_gpio: twsi0_pmx_gpio {
461 pinctrl-single,pins = <
462 GPIO49 AF0
463 GPIO50 AF0
464 >;
b.liub17525e2025-05-14 17:22:29 +0800465 DS_MEDIUM;PULL_NONE;EDGE_NONE;LPM_FLOAT;
b.liue9582032025-04-17 19:18:16 +0800466 };
b.liub17525e2025-05-14 17:22:29 +0800467#if 1
b.liue9582032025-04-17 19:18:16 +0800468 twsi1_pmx_func: twsi1_pmx_func {
469 pinctrl-single,pins = <
470 GPIO10 AF1
471 GPIO11 AF1
472 >;
b.liub17525e2025-05-14 17:22:29 +0800473 DS_SLOW0;PULL_NONE;EDGE_NONE;LPM_FLOAT;
b.liue9582032025-04-17 19:18:16 +0800474 };
475 twsi1_pmx_gpio: twsi1_pmx_gpio {
476 pinctrl-single,pins = <
477 GPIO10 AF0
478 GPIO11 AF0
479 >;
b.liub17525e2025-05-14 17:22:29 +0800480 DS_SLOW0;PULL_NONE;EDGE_NONE;LPM_FLOAT;
b.liue9582032025-04-17 19:18:16 +0800481 };
482#endif
483 /* no pull, no LPM */
484 dvc_pmx_func: dvc_pmx_func {
485 /* hw-dvc */
486 pinctrl-single,pins = <
487 TDS_DIO0 AF0
488 TDS_DIO1 AF0
489 >;
490 DS_MEDIUM;PULL_FLOAT;EDGE_NONE;SL_NORMAL;
491 };
492 leds_pmx_func: leds_pmx_func {
493 pinctrl-single,pins = <
494 DF_IO10 AF1
495 DF_IO11 AF1
496 DF_IO12 AF1
497 >;
498 DS_MEDIUM;PULL_FLOAT;EDGE_NONE;SL_NORMAL;
499 };
500
501 gps_pmx_onoff: gps_pmx_onoff {
502 pinctrl-single,pins = <
503 TDS_TXREV AF1
504 >;
505 DS_MEDIUM;PULL_DOWN;EDGE_NONE;SL_NORMAL;
506 };
507 gps_pmx_reset: gps_pmx_reset {
508 pinctrl-single,pins = <
509 TDS_RXON AF1
510 >;
511 DS_MEDIUM;PULL_DOWN;EDGE_NONE;SL_NORMAL;
512 };
b.liub17525e2025-05-14 17:22:29 +0800513
514 //zqy
515 gnss_clk_on: gnss_clk_on {
516 pinctrl-single,pins = <
517 GPIO43 AF2 /*32K CLK */
518
519 /*VCXO_REQ AF1 GPIO[125] GPS_WAKE_HOST */
520 GPIO47 AF0 /* HOST_WAKE_GPS */
521 GPIO45 AF0 /*RESET */
522 CLK_REQ AF1 /*sleep en*/
523
524 >;
525 DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_LOW;
526 };
b.liue9582032025-04-17 19:18:16 +0800527 gps_pmx_uart_rxd: gps_pmx_uart_rxd {
528 /* gps dedicated uart */
529 pinctrl-single,pins = <
530 GPIO51 AF1
hj.shao9f48a912025-06-11 00:19:29 -0700531
532 //#LYNQ_MODFIY modify for task-1618 2025/6/11 start
533 /*GPIO32 AF1*/
534 //#LYNQ_MODFIY modify for task-1618 2025/6/11 end
b.liue9582032025-04-17 19:18:16 +0800535 >;
b.liub17525e2025-05-14 17:22:29 +0800536 DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL;
b.liue9582032025-04-17 19:18:16 +0800537 };
538 gps_pmx_uart_txd: gps_pmx_uart_txd {
539 /* gps dedicated uart */
540 pinctrl-single,pins = <
541 GPIO52 AF1
hj.shao9f48a912025-06-11 00:19:29 -0700542 //#LYNQ_MODFIY modify for task-1618 2025/6/11 start
543 /*GPIO31 AF1*/
544 //#LYNQ_MODFIY modify for task-1618 2025/6/11 end
b.liue9582032025-04-17 19:18:16 +0800545 >;
b.liub17525e2025-05-14 17:22:29 +0800546 DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL;
b.liue9582032025-04-17 19:18:16 +0800547 };
b.liub17525e2025-05-14 17:22:29 +0800548 gps_pmx_func_cts_rts: gps_pmx_func_cts_rts {
549 pinctrl-single,pins = <
550 GPIO31 AF1 /* cts */
551 GPIO32 AF1 /* rts */
552 >;
553 DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL;
554 };
555
b.liue9582032025-04-17 19:18:16 +0800556 uart3_pmx_func: uart3_pmx_func {
557 pinctrl-single,pins = <
558 GPIO53 AF1 /* RX */
yu.dongca721ca2025-06-04 07:21:21 -0700559 /* GPIO54 AF1 TX */
b.liue9582032025-04-17 19:18:16 +0800560 >;
lichengzhangb746a892025-06-24 15:41:08 +0800561 MFP_PULL_DOWN;
b.liue9582032025-04-17 19:18:16 +0800562 };
b.liub17525e2025-05-14 17:22:29 +0800563
564
565 uart4_pmx_func_rxd: uart4_pmx_func_rxd {
566 pinctrl-single,pins = <
567 GPIO37 AF2
568 GPIO40 AF2
569 >;
570 DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL;
571 };
572 uart4_pmx_func_txd: uart4_pmx_func_txd {
573 pinctrl-single,pins = <
574 GPIO38 AF2
575 GPIO39 AF2
576 >;
577 DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL;
578 };
579
580 uart4_pmx_func_cts_rts: uart4_pmx_func_cts_rts {
581 pinctrl-single,pins = <
582 GPIO39 AF2
583 GPIO40 AF2
584 >;
585 DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL;
586 };
b.liue9582032025-04-17 19:18:16 +0800587 uart4_pmx_func: uart4_pmx_func {
588 pinctrl-single,pins = <
589 GPIO44 AF1 /* RX */
590 GPIO45 AF1 /* TX */
591 >;
b.liub17525e2025-05-14 17:22:29 +0800592 DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL;
b.liue9582032025-04-17 19:18:16 +0800593 };
zw.wangad00beb2025-06-24 16:54:39 +0800594 uart4_pmx_func_sleep: uart4_pmx_func_sleep {
595 pinctrl-single,pins = <
596 GPIO44 AF0 /* RX */
597 GPIO45 AF0 /* TX */
598 >;
599 MFP_PULL_DOWN;
600 };
b.liue9582032025-04-17 19:18:16 +0800601 panel_rst_func: panel_rst_func {
602 pinctrl-single,pins = <
603 DF_nCS1 AF1
604 >;
605 DS_MEDIUM;PULL_FLOAT;EDGE_NONE;SL_NORMAL;
606 };
607
608 sd_ldo_en: sd_ldo_en {
609 pinctrl-single,pins = <
610 GPIO45 AF0
611 >;
612 MFP_PULL_DOWN;
613 };
614 sdh0_pmx_func1: sdh0_pmx_func1 {
615 pinctrl-single,pins = <
616 MMC1_DAT3 AF0
617 MMC1_DAT2 AF0
618 MMC1_DAT1 AF0
619 MMC1_DAT0 AF0
620 MMC1_CMD AF0
621 >;
622 DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL;
623 };
624 sdh0_pmx_func2: sdh0_pmx_func2 {
625 pinctrl-single,pins = <
626 MMC1_CLK AF0
627 >;
628 DS_MEDIUM;PULL_NONE;EDGE_NONE;
629 };
630 sdh0_pmx_func3: sdh0_pmx_func3 {
631 pinctrl-single,pins = <
632 MMC1_CD AF1
633 >;
634 DS_MEDIUM;PULL_UP;EDGE_NONE;SL_NORMAL;
635 };
636 sdh0_pmx_cd_wakeup: sdh0_pmx_func1_cd_wakeup {
637 pinctrl-single,pins = <
638 MMC1_CD AF1
639 >;
640 DS_MEDIUM;PULL_UP;EDGE_BOTH;SL_NORMAL;
641 };
642 sdh0_pmx_func1_slow: sdh0_pmx_func1_slow {
643 pinctrl-single,pins = <
644 MMC1_DAT3 AF0
645 MMC1_DAT2 AF0
646 MMC1_DAT1 AF0
647 MMC1_DAT0 AF0
648 MMC1_CMD AF0
649 >;
650 DS_FAST0;PULL_NONE;EDGE_NONE;SL_NORMAL;
651 };
652 sdh0_pmx_func2_slow: sdh0_pmx_func2_slow {
653 pinctrl-single,pins = <
654 MMC1_CLK AF0
655 >;
656 DS_FAST0;PULL_NONE;EDGE_NONE;
657 };
658 sdh0_pmx_func1_fast: sdh0_pmx_func1_fast {
659 pinctrl-single,pins = <
660 MMC1_DAT3 AF0
661 MMC1_DAT2 AF0
662 MMC1_DAT1 AF0
663 MMC1_DAT0 AF0
664 MMC1_CMD AF0
665 >;
666 DS_FAST1;PULL_NONE;EDGE_NONE;SL_NORMAL;
667 };
668 sdh0_pmx_func2_fast: sdh0_pmx_func2_fast {
669 pinctrl-single,pins = <
670 MMC1_CLK AF0
671 >;
672 DS_FAST1;PULL_NONE;EDGE_NONE;
673 };
674 sdh1_pmx_func1_fast: sdh1_pmx_func1_fast {
675 pinctrl-single,pins = <
676 TDS_DIO13 AF0 /* WLAN_DAT3 */
677 TDS_DIO14 AF0 /* WLAN_DAT2 */
678 TDS_DIO15 AF0 /* WLAN_DAT1 */
679 TDS_DIO16 AF0 /* WLAN_DAT0 */
680 TDS_DIO17 AF0 /* WLAN_CMD */
681 >;
682 DS_FAST0;PULL_NONE;EDGE_NONE;SL_NORMAL;
683 };
684 sdh1_pmx_func2_fast: sdh1_pmx_func2_fast {
685 pinctrl-single,pins = <
686 TDS_DIO18 AF0 /* WLAN_CLK */
687 >;
688 DS_FAST0;PULL_DOWN;EDGE_NONE;SL_NORMAL;
689 };
690 sdh1_pmx_func1: sdh1_pmx_func1 {
691 pinctrl-single,pins = <
692 TDS_DIO13 AF0 /* WLAN_DAT3 */
693 TDS_DIO14 AF0 /* WLAN_DAT2 */
694 TDS_DIO15 AF0 /* WLAN_DAT1 */
695 TDS_DIO16 AF0 /* WLAN_DAT0 */
696 TDS_DIO17 AF0 /* WLAN_CMD */
697 >;
698 DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_LOW;
699 };
700 sdh1_pmx_func2: sdh1_pmx_func2 {
701 pinctrl-single,pins = <
702 TDS_DIO18 AF0 /* WLAN_CLK */
703 >;
704 DS_MEDIUM;PULL_DOWN;EDGE_NONE;SL_LOW;
705 };
zw.wangad00beb2025-06-24 16:54:39 +0800706 sdh1_pmx_func1_sleep_sdio: sdh1_pmx_func1_sleep_sdio {
707 pinctrl-single,pins = <
708 TDS_DIO13 AF1
709 TDS_DIO14 AF1
710 TDS_DIO15 AF1
711 TDS_DIO16 AF1
712 TDS_DIO17 AF1
713 >;
714 MFP_PULL_DOWN;
715 };
716 sdh1_pmx_func2_sleep_sdio: sdh1_pmx_func2_sleep_sdio {
717 pinctrl-single,pins = <
718 TDS_DIO18 AF1
719 >;
720 MFP_PULL_DOWN;
721 };
b.liue9582032025-04-17 19:18:16 +0800722 sdh1_pmx_func3: sdh1_pmx_func3 {
723 pinctrl-single,pins = <
724 GPIO10 AF0 /* VCXO_REQ AF1 WLAN_WAKE_HOST */
725 >;
726 MFP_PULL_DOWN;
727 };
728 sdh1_pmx_edge_wakeup: sdh1_pmx_edge_wakeup {
729 pinctrl-single,pins = <
730 GPIO10 AF0 /* VCXO_REQ AF1 */
731 >;
732 DS_MEDIUM;PULL_DOWN;EDGE_RISE;SL_NORMAL;
733 };
734 sdh1_pmx_pd_rst_off: sdh1_pmx_pd_rst_off {
735 pinctrl-single,pins = <
b.liub17525e2025-05-14 17:22:29 +0800736 /* GPIO11 AF0 GPIO31 AF0 WLAN_PDn */
737 /* GPIO08 AF0 GPIO32 AF0 LDO_EN */
738 MMC1_CD AF1
b.liue9582032025-04-17 19:18:16 +0800739 >;
740 MFP_PULL_DOWN;
741 };
742 sdh1_pmx_pd_rst_on: sdh1_pmx_pd_rst_on {
743 pinctrl-single,pins = <
b.liub17525e2025-05-14 17:22:29 +0800744 /* GPIO11 AF0 GPIO31 AF0 WLAN_PDn */
745 /* GPIO08 AF0 GPIO32 AF0 LDO_EN */
746 MMC1_CD AF1
747 >;
748 MFP_PULL_UP;
749 };
750
751
752 mbtk_sdh_pmx_off: mbtk_sdh_pmx_off {
753 pinctrl-single,pins = <
754 VCXO_REQ AF1 //gpio125 wlan en
755 GPIO123 AF1 //wlan pwr en
you.chen9824a892025-06-04 20:23:26 +0800756 /*VCXO_OUT AF1 /*gpio127 wifi wake*/
b.liub17525e2025-05-14 17:22:29 +0800757 >;
758 MFP_PULL_DOWN;
759 };
760 mbtk_sdh_pmx_on: mbtk_sdh_pmx_on {
761 pinctrl-single,pins = <
762 VCXO_REQ AF1 //gpio125 wlan en
763 GPIO123 AF1 //wlan pwr en
you.chen9824a892025-06-04 20:23:26 +0800764 /*VCXO_OUT AF1 /*gpio127 wifi wake*/
b.liue9582032025-04-17 19:18:16 +0800765 >;
766 MFP_PULL_UP;
767 };
768 alc5616_pmx_func1: alc5616_pmx_func1 {
769 pinctrl-single,pins = <
b.liub17525e2025-05-14 17:22:29 +0800770 /* GPIO08 AF0 AP_UART1_DCD_N -> CODEC_IRQ */
b.liue9582032025-04-17 19:18:16 +0800771 GPIO20 AF7 /* MCLK:I2S_SYSCLK */
772 >;
773 MFP_DEFAULT;
774 };
775 alc5616_pmx_func2: alc5616_pmx_func2 {
776 pinctrl-single,pins = <
b.liub17525e2025-05-14 17:22:29 +0800777 /* GPIO08 AF0 AP_UART1_DCD_N -> CODEC_IRQ */
778 GPIO20 AF7 /* MCLK:I2S_SYSCLK */
779 >;
780 MFP_DEFAULT;
781 };
782
783 es8311_pa_func1: es8311_pa_func1 {
784 pinctrl-single,pins = <
785 GPIO20 AF7 /* MCLK:I2S_SYSCLK */
yu.dongb3e49372025-06-23 23:57:56 -0700786 GPIO54 AF0 /* CODEC_VDDD_EN */
787 GPIO24 AF0 /* NAD_PA_PWR_EN */
b.liub17525e2025-05-14 17:22:29 +0800788 >;
789 MFP_DEFAULT;
790 };
791 es8311_pa_func2: es8311_pa_func2 {
792 pinctrl-single,pins = <
b.liue9582032025-04-17 19:18:16 +0800793 GPIO20 AF7 /* MCLK:I2S_SYSCLK */
yu.dongb3e49372025-06-23 23:57:56 -0700794 GPIO54 AF0 /* CODEC_VDDD_EN */
795 GPIO24 AF0 /* NAD_PA_PWR_EN */
b.liue9582032025-04-17 19:18:16 +0800796 >;
797 MFP_DEFAULT;
798 };
799 audio_pa_pmx_func: audio_pa_pmx_func {
800 pinctrl-single,pins = <
801 GPIO14 AF0 /* PA */
802 >;
803 MFP_DEFAULT;
804 };
805 ecall_pmx_func: ecall_pmx_func {
806 pinctrl-single,pins = <
807 GPIO08 AF0 /* auto mode ecall */
808 GPIO09 AF0 /* manual mode ecall */
809 >;
810 MFP_DEFAULT;
811 };
812 slic_pmx_func1: slic_pmx_func1 {
813 pinctrl-single,pins = <
814 GPIO20 AF0 /* SLIC_INT, GPIO20 */
815 VCXO_OUT AF1 /* GPIO127, SLIC_3V3LDO_EN/LCD_BK_EN */
816 >;
817 MFP_DEFAULT;
818 };
819 slic_pmx_func2: slic_pmx_func2 {
820 pinctrl-single,pins = <
821 GPIO21 AF0 /* SLIC_RESET, GPIO21 */
822 >;
823 MFP_DEFAULT;
824 };
825 slic_pmx_func1_sleep: slic_pmx_func1_sleep {
826 pinctrl-single,pins = <
827 GPIO20 AF0 /* SLIC_INT, GPIO20 */
828 >;
829 DS_MEDIUM;PULL_UP;EDGE_BOTH;SL_NORMAL;
830 };
831
832 otg_vbus_func: otg_vbus_func {
833 pinctrl-single,pins = <
b.liub17525e2025-05-14 17:22:29 +0800834 /* VBUS_DRV AF1 GPIO[122] */
b.liue9582032025-04-17 19:18:16 +0800835 >;
836 DS_MEDIUM;PULL_DOWN;EDGE_NONE;
837 };
838
839 emac_pmx_func0: emac_pmx_func0 {
840 pinctrl-single,pins = <
841 GPIO00 AF1 /* GMAC1_RX_DV */
842 GPIO01 AF1 /* GMAC1_RX_D0 */
843 GPIO02 AF1 /* GMAC1_RX_D1 */
844 GPIO03 AF1 /* GMAC1_RX_CLK */
845 /* GPIO04 AF1 GMAC1_RX_D2 */
846 /* GPIO05 AF1 GMAC1_RX_D3 */
847 GPIO06 AF1 /* GMAC1_TX_D0 */
848 GPIO07 AF1 /* GMAC1_TX_D1 */
849 /* GPIO12 AF1 GMAC1_TX_CLK */
850 /* GPIO13 AF1 GMAC1_TX_D2 */
851 /* GPIO14 AF1 GMAC1_TX_D3 */
852 GPIO15 AF1 /* GMAC1_TX_EN */
853 GPIO16 AF1 /* GMAC1_TX_MDC */
854 /* GPIO17 AF1 GMAC1_TX_MDIO */
855 >;
856 DS_MEDIUM;PULL_DOWN;EDGE_NONE;SL_NORMAL;
857 };
858 emac_pmx_func1: emac_pmx_func1 {
859 pinctrl-single,pins = <
860 GPIO04 AF1 /* GMAC1_RX_D2 */
861 GPIO05 AF1 /* GMAC1_RX_D3 */
862 GPIO12 AF1 /* GMAC1_TX_CLK */
863 GPIO13 AF1 /* GMAC1_TX_D2 */
864 GPIO14 AF1 /* GMAC1_TX_D3 */
865 >;
866 DS_MEDIUM;PULL_DOWN;EDGE_NONE;SL_NORMAL;
867 };
868 emac_pmx_func2: emac_pmx_func2 {
869 pinctrl-single,pins = <
870 GPIO17 AF1 /* GMAC1_TX_MDIO */
871 GPIO18 AF1 /* GMAC1_TX_INT_N */
872 >;
873 DS_MEDIUM;PULL_UP;EDGE_NONE;SL_NORMAL;
874 };
875 emac_pmx_func3: emac_pmx_func3 {
876 pinctrl-single,pins = <
b.liub17525e2025-05-14 17:22:29 +0800877 GPIO42 AF0 /* RESET */
hj.shaofb3ba9b2025-06-19 02:53:56 -0700878 //#LYNQ_MODFIY modify for task-1618 2025/6/19 start
879 GPIO32 AF0 /* POWER EN */
880 //#LYNQ_MODFIY modify for task-1618 2025/6/19 end
b.liub17525e2025-05-14 17:22:29 +0800881 /* GPIO40 AF0 LDO_EN */
b.liue9582032025-04-17 19:18:16 +0800882 >;
883 DS_SLOW0;PULL_FLOAT;EDGE_NONE;SL_NORMAL;
884 };
885 usim1_pmx_func: usim1_pmx_func {
886 pinctrl-single,pins = <
yq.wang107f9862025-05-12 15:44:50 +0800887 PRI_TCK AF1
b.liue9582032025-04-17 19:18:16 +0800888 >;
889 DS_MEDIUM;PULL_UP;EDGE_NONE;SL_NORMAL;
890 };
891 usim1_pmx_func_sleep: usim1_pmx_func_sleep {
892 pinctrl-single,pins = <
yq.wang107f9862025-05-12 15:44:50 +0800893 PRI_TCK AF1
b.liue9582032025-04-17 19:18:16 +0800894 >;
895 DS_MEDIUM;PULL_UP;EDGE_BOTH;SL_NORMAL;
896 };
897 usim2_pmx_func: usim2_pmx_func {
898 pinctrl-single,pins = <
899 GPIO44 AF0
900 >;
901 DS_MEDIUM;PULL_UP;EDGE_NONE;SL_NORMAL;
902 };
903 usim2_pmx_func_sleep: usim2_pmx_func_sleep {
904 pinctrl-single,pins = <
905 GPIO44 AF0
906 >;
907 DS_MEDIUM;PULL_UP;EDGE_BOTH;SL_NORMAL;
908 };
909 pcie_pmx_pd_rst_off: pcie_pmx_pd_rst_off {
910 pinctrl-single,pins = <
911 GPIO42 AF0 /* PERST_N */
912 GPIO24 AF0 /* DC_EN */
913 >;
914 MFP_PULL_DOWN;
915 };
916 pcie_pmx_pd_rst_on: pcie_pmx_pd_rst_on {
917 pinctrl-single,pins = <
918 GPIO42 AF0 /* PERST_N */
919 GPIO24 AF0 /* DC_EN */
920 >;
921 MFP_PULL_UP;
922 };
b.liub17525e2025-05-14 17:22:29 +0800923 pin_func_work: pin_func_work {
924 pinctrl-single,pins = <
925
926 GPIO08 AF0 /*T108 status led* /
927
928 VBUS_DRV AF2 /*32k*/
929
930
931 GPIO46 AF0 /*wifi en*/
932
933 GPIO19 AF0 /*bt en*/
934
935 >;
936 MFP_DEFAULT;
937 };
938
939
940 sc_ext_int0: sc_ext_int0 {
941 pinctrl-single,pins = <
942 GPIO21 AF0
943 >;
944 DS_MEDIUM;PULL_NONE;EDGE_BOTH;SL_NORMAL;
945 };
946 sc_ext_int1: sc_ext_int1 {
947 pinctrl-single,pins = <
948 GPIO22 AF0
949 >;
950 MFP_DEFAULT;
951 };
952
953 sc_ext_int2: sc_ext_int2 {
954 pinctrl-single,pins = <
955 GPIO23 AF0
956 >;
957 MFP_DEFAULT;
958 };
959
960
961 sc_ext_int3: sc_ext_int3 {
962 pinctrl-single,pins = <
963 GPIO24 AF0
964 >;
965 MFP_DEFAULT;
966 };
967
968
969 mbtk_plat_irq_func: mbtk_plat_irq_func {
970 pinctrl-single,pins = <
971
you.chen9824a892025-06-04 20:23:26 +0800972 /*GPIO21 AF0
973 GPIO22 AF0 */
b.liub17525e2025-05-14 17:22:29 +0800974 GPIO23 AF0
yu.dongca721ca2025-06-04 07:21:21 -0700975 GPIO24 AF0
b.liub17525e2025-05-14 17:22:29 +0800976
977 >;
978 DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL;
979 };
980 mbtk_plat_irq_func_sleep: mbtk_plat_irq_func_sleep {
981 pinctrl-single,pins = <
you.chen9824a892025-06-04 20:23:26 +0800982 /*GPIO21 AF0
983 GPIO22 AF0*/
b.liub17525e2025-05-14 17:22:29 +0800984 GPIO23 AF0
yu.dongca721ca2025-06-04 07:21:21 -0700985 GPIO24 AF0
b.liub17525e2025-05-14 17:22:29 +0800986 >;
987 DS_MEDIUM;PULL_NONE;EDGE_BOTH;SL_NORMAL;
988 };
989
990
b.liue9582032025-04-17 19:18:16 +0800991 gpiokey_pmx_func: gpiokey_pmx_func {
992 pinctrl-single,pins = <
993 GPIO09 AF0
994 >;
995 DS_MEDIUM;PULL_UP;EDGE_NONE;SL_NORMAL;
996 };
b.liub17525e2025-05-14 17:22:29 +0800997
lichengzhangb746a892025-06-24 15:41:08 +0800998 /*for ssp2 is not in use, it needs to be used as a regular gpio,default state is input and low*/
999 gpiokey_ssp2_func: gpiokey_ssp2_func {
1000 pinctrl-single,pins = <
1001 GPIO37 AF0 /* TXD */
1002 GPIO38 AF0 /* SCLK */
1003 GPIO39 AF0 /* FRM */
1004 GPIO40 AF0 /* RXD */
1005 >;
1006 DS_MEDIUM;PULL_DOWN;EDGE_NONE;SL_NORMAL;
1007 };
1008
b.liub17525e2025-05-14 17:22:29 +08001009 wake_pmx_func1: wake_pmx_func1 {
1010 pinctrl-single,pins = <
1011 USB_ID AF1
1012 >;
1013 DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL;
1014 };
1015
hong.liuf2416882025-05-23 20:41:06 -07001016 led_pmx_func1: led_pmx_func1 {
1017 pinctrl-single,pins = <
1018 GPIO08 AF0
1019 >;
1020 DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL;
1021 };
1022
b.liub17525e2025-05-14 17:22:29 +08001023
1024 wake_pmx_func: wake_pmx_func {
1025 pinctrl-single,pins = <
1026 PRI_TDI AF1 /*GPIO117 WAKEUP_OUT*/
1027
1028 PRI_TMS AF1 /*GPIO118 WAKEUP_IN*/
1029 GPIO41 AF0
1030 PRI_TDO AF1 /*GPIO120*/
1031
1032
1033 >;
1034 DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL;
1035 };
1036 wake_pmx_func_sleep: wake_pmx_func_sleep {
1037 pinctrl-single,pins = <
1038 PRI_TDI AF1 /*GPIO117 WAKEUP_OUT*/
1039
1040 PRI_TMS AF1 /*GPIO118 WAKEUP_IN*/
1041 GPIO41 AF0
1042 PRI_TDO AF1 /*GPIO120*/
1043
1044 >;
1045 DS_MEDIUM;PULL_NONE;EDGE_BOTH;SL_NORMAL;
1046 };
1047 usb_id_pinmux: usb_id_pinmux {
b.liue9582032025-04-17 19:18:16 +08001048 pinctrl-single,pins = <
1049 USB_ID AF1/* usbid-gpio99 */
1050 >;
1051 DS_MEDIUM;PULL_UP;EDGE_NONE;LPM_NONE;
1052 };
1053 usb_id_pinmux_slp: usb_id_pinmux_slp {
1054 pinctrl-single,pins = <
1055 USB_ID AF1 /* usbid-gpio99 */
1056 >;
1057 DS_MEDIUM;PULL_UP;EDGE_BOTH;LPM_NONE;
1058 };
1059 usb_host_pinmux: usb_host_pinmux {
1060 pinctrl-single,pins = <
1061 VBUS_DRV AF1 /* gpio-122 */
1062 >;
1063 DS_MEDIUM;PULL_FLOAT;EDGE_NONE;LPM_NONE;
1064 };
1065 i2s_func: i2s_func {
1066 pinctrl-single,pins = <
1067 GPIO25 AF2
1068 GPIO26 AF2
1069 GPIO27 AF2
1070 GPIO28 AF2
1071 >;
1072 MFP_DEFAULT;
1073 };
1074 i2s_gpio: i2s_gpio {
1075 pinctrl-single,pins = <
1076 GPIO25 AF0
1077 GPIO26 AF0
1078 GPIO27 AF0
1079 GPIO28 AF0
1080 >;
1081 MFP_LPM_FLOAT;
1082 };
you.chen9824a892025-06-04 20:23:26 +08001083 sensors_int:sensors_int {
1084 pinctrl-single,pins = <
1085 GPIO22 AF0
1086 >;
1087 MFP_PULL_DOWN;
1088 };
1089 sensors_csb:sensors_csb {
1090 pinctrl-single,pins = <
1091 VCXO_OUT AF1
1092 >;
1093 DS_MEDIUM;PULL_UP;EDGE_NONE;
1094 };
b.liue9582032025-04-17 19:18:16 +08001095 };
1096
1097 ssp0: spi@d401b000 {
1098 status = "okay";
1099 pinctrl-names = "default";
1100 pinctrl-0 = <&ssp0_pmx_func>;
1101 asr,spi-inc-mode;
1102#ifdef CONFIG_FB_SPI_LCD
1103 /* this enhancemnet feature is not suitable for
1104 3 line 9bits spi lcd. */
1105 /* asr,ssp-enhancement; */
1106
1107 lcd: spidev@0 {
1108 #address-cells = <1>;
1109 #size-cells = <1>;
1110 compatible = "spilcd";
b.liub17525e2025-05-14 17:22:29 +08001111 // pinctrl-names = "default";
1112 // pinctrl-0 = <&lcd_bl_func>;
b.liue9582032025-04-17 19:18:16 +08001113 reg = <0>;
1114 /* ST7735: need to set spi-max-frequency to 26M
1115 * ST7789V: can set spi-max-frequency to 52M
1116 */
1117 spi-max-frequency = <26000000>;
1118 xres = <128>;
1119 yres = <128>;
1120 bits = <8>; /* 8: 4line, 9: 3line */
1121 rst_gpio = <&gpio 24 0>;
b.liub17525e2025-05-14 17:22:29 +08001122 // bl_gpio = <&gpio 126 0>;
b.liue9582032025-04-17 19:18:16 +08001123 rs_gpio = <&gpio 22 0>;
1124 /* if comment the following statement, it means
1125 * the avdd is sit on the "always-on" ldo.
1126 */
1127 /* avdd-supply = <&LDO1>; */
1128 };
1129#else
1130 /*cs-gpios = <&gpio 34 0>;*//* DXS101 Use the config of Cs-gpios */
1131 slic: spidev@0{
1132 #address-cells = <1>;
1133 #size-cells = <1>;
1134 compatible = "asr,slic";
1135 reg = <0>;
1136 spi-cpol;
1137 spi-cpha;
1138 spi-max-frequency = <6500000>;
1139 };
1140#endif
1141 };
b.liub17525e2025-05-14 17:22:29 +08001142 ssp2: spi@d401c000{
lichengzhangb746a892025-06-24 15:41:08 +08001143 status = "disabled";
b.liub17525e2025-05-14 17:22:29 +08001144 pinctrl-names = "default";
1145 pinctrl-0 = <&ssp2_pmx_func>;
1146 asr,spi-inc-mode;
1147 cs-gpios = <&gpio 39 0>;
b.liub17525e2025-05-14 17:22:29 +08001148 mbtk: spidev@0{
1149 compatible = "asr,spidev";
1150 reg = <0>;
1151 status = "okay";
1152 spi-cpol;
1153 spi-cpha;
1154 spi-max-frequency = <6500000>;
1155 };
1156 };
b.liue9582032025-04-17 19:18:16 +08001157 twsi0: i2c@d4011000 {
1158 status= "okay";
1159 alc5616@1b {
b.liub17525e2025-05-14 17:22:29 +08001160 status= "disabled";
b.liue9582032025-04-17 19:18:16 +08001161 compatible = "asrmicro,alc5616";
1162 reg = <0x1b>;
1163 pinctrl-names = "default", "sleep";
1164 pinctrl-0 = <&alc5616_pmx_func1>;
1165 pinctrl-1 = <&alc5616_pmx_func2>;
1166 clocks = <&soc_clocks ASR1803_CLK_I2S_SYSCLK>;
1167 clock-names = "i2s_sys_clk";
1168#if 0
1169 3V3-gpio = <&gpio 23 0>;/* CODEC_LDO_EN */
1170 irq-gpio = <&gpio 24 0>;/* CODEC_IRQ for headset detection */
1171#else
1172 irq-gpio = <&gpio 8 0>;/* CODEC_IRQ for headset detection */
1173#endif
1174 };
1175
b.liub17525e2025-05-14 17:22:29 +08001176 nau8810@1a {
1177 compatible = "marvell,nau8810";
1178 clocks = <&soc_clocks ASR1803_CLK_I2S_SYSCLK>;
1179 clock-names = "i2s_sys_clk";
1180
1181
1182 pinctrl-names = "default";
1183 pinctrl-0 = <&es8311_pa_func1>;
1184 pinctrl-1 = <&es8311_pa_func2>;
1185 reg = <0x1a>;
1186 status= "disabled";
1187 };
1188
1189 es8311@18 {
1190 compatible = "ambarella,es8311";
1191 reg = <0x18>;
1192 clocks = <&soc_clocks ASR1803_CLK_I2S_SYSCLK>;
1193 clock-names = "i2s_sys_clk";
1194
1195 pinctrl-names = "default";
1196 pinctrl-0 = <&es8311_pa_func1>;
1197 pinctrl-1 = <&es8311_pa_func2>;
yu.dongb3e49372025-06-23 23:57:56 -07001198 gpios = <&gpio 54 0>;
b.liub17525e2025-05-14 17:22:29 +08001199
1200 // gpios = <&gpio 21 0>,
1201 // <&gpio 23 0>,
1202 // <&gpio 24 0>,
1203 // <&gpio 22 0>;
1204
1205 status= "okay";
1206 };
1207
you.chen9824a892025-06-04 20:23:26 +08001208 asm330lhhx-imu@0x6a {
1209 compatible = "st,asm330lhhx";
1210 reg = <0x6b>;
1211 pinctrl-names = "default";
1212 pinctrl-0 = <&sensors_int &sensors_csb>;
1213 interrupt-parent = <&gpio>;
1214 interrupts = <22 1>;
1215 //interrupts = <22>;
1216 vddio-supply = <&sensors_vddio>;
1217 //vdd-supply = <&sensors_vdd>;
1218 st,int-pin = <1>;
1219 //st,mlc-int-pin = <2>;
1220 mount-matrix = "1", "0", "0",
1221 "0", "1", "0",
1222 "0", "0", "1";
1223 };
yu.dongb39db3e2025-06-06 03:15:42 -07001224 /* AWINIC AW87XXX Smart K PA */
1225 aw87xxx_pa@58 {
1226 compatible = "awinic,aw87xxx_pa";
1227 reg = <0x58>;
1228 reset-gpio = <&gpio 24 0>;
1229 dev_index = < 0 >;
1230 status = "okay";
1231 };
1232 /* AWINIC AW87XXX Smart K PA End */
b.liue9582032025-04-17 19:18:16 +08001233 /*
1234 pmic4: 88pm805@38 {
1235 compatible = "marvell,88pm805";
1236 reg = <0x38>;
1237 };
1238 */
1239 };
1240 twsi1: i2c@d4010800 {
b.liub17525e2025-05-14 17:22:29 +08001241#if 1
b.liue9582032025-04-17 19:18:16 +08001242 pinctrl-names = "default","gpio";
1243 pinctrl-0 = <&twsi1_pmx_func>;
1244 pinctrl-1 = <&twsi1_pmx_gpio>;
1245 i2c-gpio = <&gpio 10 0 &gpio 11 0>;
1246#endif
b.liub17525e2025-05-14 17:22:29 +08001247 status= "okay";
1248 //nau8810@1a {
1249 // compatible = "marvell,nau8810";
1250 // reg = <0x1a>;
1251 //};
1252
1253
b.liue9582032025-04-17 19:18:16 +08001254 };
1255 twsi2: i2c@d4037000 {
1256 status = "okay";
1257
1258 pmic4: 88pm805@38 {
1259 compatible = "marvell,88pm805";
1260 reg = <0x38>;
1261 };
1262
1263 pmic5: pm802@0 {
1264 compatible = "asr,pm802";
1265 reg = <0x00>;
1266 interrupts = <4>;
1267 interrupt-parent = <&intc>;
1268 interrupt-controller;
1269 #interrupt-cells = <1>;
1270 chg_irq_from_exton;
1271 scs-int-active-high;
1272 battery {
1273 compatible = "asr,pm802-bat";
1274 status = "disabled";
1275
1276 online-gpadc = <1>;
1277 temperature-gpadc = <1>;
1278
1279 hi-volt-online = <1150>; /* mV */
1280 lo-volt-online = <20>; /* mV */
1281 hi-volt-temp = <1150>; /* mV */
1282 lo-volt-temp = <200>; /* mV */
1283
1284 sw-fg-use-ntc;
1285 full-capacity = <2050>; /* mAh */
1286 r1-resistor = <40>; /* mohm */
1287 r2-resistor = <30>; /* mohm */
1288 rs-resistor = <120>; /* mohm */
1289 roff-resistor = <0>; /* mohm */
1290 roff-initial-resistor = <0>; /* mohm */
1291
1292 times-in-zero-degree = <1>;
1293 offset-in-zero-degree = <0>;
1294
1295 times-in-ten-degree = <2>;
1296 offset-in-ten-degree = <100>;
1297
1298 power-off-threshold = <3350>; /* mV */
1299 safe-power-off-threshold = <3200>; /* mV */
1300
1301 online-gp-bias-curr = <11>; /* uA */
1302
1303 soc-ramp-up-interval = <150>; /* s */
1304 /* choose -20C, 0C, 10C, 40C, 45C, 55C as threshold */
1305 tbat-threshold = <20 0 10 40 45 55>; /* ohm */
1306 ntc-table-size = <88>;
1307 stop-chg-for-vbatmeas;
1308 /* -24C, -23C, ..., 62C, 63C */
1309 ntc-table = <
1310 89680 85130 80840 76790 72970 69360 65960 62740
1311 59700 56830 54130 51530 49100 46800 44610 42550
1312 40590 38730 36970 35300 33710 32210 30780 29420
1313 28130 26910 25750 24640 23590 22580 21630 20720
1314 19860 19030 18250 17500 16790 16110 15460 14840
1315 14250 13690 13150 12640 12150 11680 11230 10800
1316 10390 10000 9620 9270 8920 8590 8280 7980
1317 7690 7410 7150 6890 6650 6410 6190 5970
1318 5770 5570 5380 5190 5020 4850 4680 4530
1319 4380 4230 4100 3960 3830 3710 3590 3480
1320 3370 3260 3160 3060 2960 2870 2780 2700
1321 >;
1322 };
1323 usb {
1324 status = "disabled";
1325 vbus_gpio = <0xff>; /* set_vbus */
1326 id-gpadc = <0xff>; /* usb-id */
1327 vchg-from-exton = <1>;
1328 vbus-detect = <1>; /* vbus-irq */
1329 get-vbus = <1>; /* get-vbus */
1330 };
1331 };
1332 pmic6: pm803@30 {
1333 compatible = "asr,pm803";
1334 reg = <0x30>;
1335 interrupts = <4>;
1336 interrupt-parent = <&intc>;
1337 interrupt-controller;
1338 #interrupt-cells = <1>;
1339 chg_irq_from_exton;
1340 scs-int-active-high;
1341 battery {
1342 compatible = "asr,pm803-bat";
1343 status = "disabled";
1344
1345 online-gpadc = <1>;
1346 temperature-gpadc = <1>;
1347
1348 hi-volt-online = <1150>; /* mV */
1349 lo-volt-online = <20>; /* mV */
1350 hi-volt-temp = <1150>; /* mV */
1351 lo-volt-temp = <200>; /* mV */
1352
1353 sw-fg-use-ntc;
1354 full-capacity = <2050>; /* mAh */
1355 r1-resistor = <40>; /* mohm */
1356 r2-resistor = <30>; /* mohm */
1357 rs-resistor = <120>; /* mohm */
1358 roff-resistor = <0>; /* mohm */
1359 roff-initial-resistor = <0>; /* mohm */
1360
1361 times-in-zero-degree = <1>;
1362 offset-in-zero-degree = <0>;
1363
1364 times-in-ten-degree = <2>;
1365 offset-in-ten-degree = <100>;
1366
1367 power-off-threshold = <3350>; /* mV */
1368 safe-power-off-threshold = <3200>; /* mV */
1369
1370 online-gp-bias-curr = <11>; /* uA */
1371
1372 soc-ramp-up-interval = <150>; /* s */
1373 /* choose -20C, 0C, 10C, 40C, 45C, 55C as threshold */
1374 tbat-threshold = <20 0 10 40 45 55>; /* ohm */
1375 ntc-table-size = <88>;
1376 stop-chg-for-vbatmeas;
1377 /* -24C, -23C, ..., 62C, 63C */
1378 ntc-table = <
1379 89680 85130 80840 76790 72970 69360 65960 62740
1380 59700 56830 54130 51530 49100 46800 44610 42550
1381 40590 38730 36970 35300 33710 32210 30780 29420
1382 28130 26910 25750 24640 23590 22580 21630 20720
1383 19860 19030 18250 17500 16790 16110 15460 14840
1384 14250 13690 13150 12640 12150 11680 11230 10800
1385 10390 10000 9620 9270 8920 8590 8280 7980
1386 7690 7410 7150 6890 6650 6410 6190 5970
1387 5770 5570 5380 5190 5020 4850 4680 4530
1388 4380 4230 4100 3960 3830 3710 3590 3480
1389 3370 3260 3160 3060 2960 2870 2780 2700
1390 >;
1391 };
1392 usb {
1393 status = "disabled";
1394 vbus_gpio = <0xff>; /* set_vbus */
1395 id-gpadc = <0xff>; /* usb-id */
1396 vchg-from-exton = <1>;
1397 vbus-detect = <1>; /* vbus-irq */
1398 get-vbus = <1>; /* get-vbus */
1399 };
1400 };
1401 };
1402 };
1403 };
1404
1405 vcc_sdh1: sd-regulator {
1406 compatible = "regulator-fixed";
b.liub17525e2025-05-14 17:22:29 +08001407 /*pinctrl-names = "default";*/
1408 /*pinctrl-0 = <&sd_ldo_en>;*/
b.liue9582032025-04-17 19:18:16 +08001409 regulator-name = "SDH1 VCC";
1410 regulator-min-microvolt = <3300000>;
1411 regulator-max-microvolt = <3300000>;
b.liub17525e2025-05-14 17:22:29 +08001412 /* gpio = <&gpio 45 0>;*/
b.liue9582032025-04-17 19:18:16 +08001413 enable-active-high;
1414 status = "okay";
1415 };
1416
you.chen9824a892025-06-04 20:23:26 +08001417 sensors_vddio: imu-regulator {
1418 compatible = "regulator-fixed";
1419 /*pinctrl-names = "default";*/
1420 /*pinctrl-0 = <&sd_ldo_en>;*/
1421 regulator-name = "IMU VDDIO";
1422 gpio = <&gpio 21 0>;
1423 enable-active-high;
1424 status = "okay";
1425 };
1426
b.liue9582032025-04-17 19:18:16 +08001427 asr-rfkill {
1428 compatible = "asr,asr-rfkill";
1429 pinctrl-names = "off", "on";
1430 pinctrl-0 = <&sdh1_pmx_pd_rst_off>;
1431 pinctrl-1 = <&sdh1_pmx_pd_rst_on>;
b.liub17525e2025-05-14 17:22:29 +08001432 sd-host = <&sdh0>;
1433 //pd-gpio = <&gpio 90 0>;
1434 rst-gpio = <&gpio 90 0>;
1435
1436 /*3v3-ldo-gpio = <&gpio 8 0>;*/
1437 /*edge-wakeup-gpio = <&gpio 10 0>;*/
1438 status = "okay";
1439 };
1440
1441 mbtk-sdh{
1442 compatible = "mbtk,mbtk-sdh";
1443 pinctrl-names = "off", "on";
1444 pinctrl-0 = <&mbtk_sdh_pmx_off>;
1445 pinctrl-1 = <&mbtk_sdh_pmx_on>;
1446 sd-host = <&sdh1>;
1447 1v8-ldo-gpio = <&gpio 123 0>;
you.chen9824a892025-06-04 20:23:26 +08001448 //host-wakeup-wlan-gpio = <&gpio 127 0>;
b.liub17525e2025-05-14 17:22:29 +08001449 wlan_en_gpio = <&gpio 125 0>;
1450 status = "okay";
1451 };
1452
1453 asr-gps {
1454 compatible = "asr,asr-gnss";
1455 pinctrl-names = "default";
1456 pinctrl-0 = <&gnss_clk_on>;
1457 enable_vctcxo_out1;
1458 host-wakeup-gnss-gpio = <&gpio 47 0>;
1459 /*gnss-wakeup-host-gpio = <&gpio 47 0>;*/
1460 rst-gpio = <&gpio 45 0>;
b.liue9582032025-04-17 19:18:16 +08001461 status = "okay";
1462 };
1463
1464 pcie-rfkill {
1465 compatible = "mrvl,pcie-rfkill";
1466 pinctrl-names = "off", "on";
1467 pinctrl-0 = <&pcie_pmx_pd_rst_off>;
1468 pinctrl-1 = <&pcie_pmx_pd_rst_on>;
1469 rst-gpio = <&gpio 42 0>;
1470 3v3-ldo-gpio = <&gpio 24 0>;
b.liub17525e2025-05-14 17:22:29 +08001471 status = "disabled";
b.liue9582032025-04-17 19:18:16 +08001472 };
1473
1474 sound {
1475 compatible = "ASRMICRO,asrmicro-snd-card";
1476 ssp-controllers = <&ssp_dai1>;
1477 };
1478
b.liub17525e2025-05-14 17:22:29 +08001479 asr-adc {
1480 compatible = "asr,adc";
1481 //pinctrl-names = "default";
1482 //pinctrl-0 = <&pin_func_work>;
1483 status = "okay";
1484 };
1485
1486#if 0
1487
1488 mbtk_PlatIrq{
1489 compatible = "mbtk,plat-irq";
1490 pinctrl-names = "sc_irq0", "sc_irq1", "sc_irq2", "sc_irq3";
1491
1492 pinctrl-0 = <&sc_ext_int0>;
1493 pinctrl-1 = <&sc_ext_int1>;
1494 pinctrl-2 = <&sc_ext_int2>;
1495 pinctrl-3 = <&sc_ext_int3>;
yu.dongca721ca2025-06-04 07:21:21 -07001496 status = "disabled";
b.liub17525e2025-05-14 17:22:29 +08001497 };
1498
1499#else
1500
1501 mbtk_PlatIrq{
1502 compatible = "mbtk,plat-irq";
1503 pinctrl-names = "default", "sleep";
1504 pinctrl-0 = <&mbtk_plat_irq_func>;
1505 pinctrl-1 = <&mbtk_plat_irq_func_sleep>;
you.chen9824a892025-06-04 20:23:26 +08001506 //gpio_irq0 = <&gpio 21 0>;
1507 //gpio_irq1 = <&gpio 22 0>;
b.liub17525e2025-05-14 17:22:29 +08001508 gpio_irq2 = <&gpio 23 0>;
1509 gpio_irq3 = <&gpio 24 0>;
yu.dongca721ca2025-06-04 07:21:21 -07001510 status = "disabled";
b.liub17525e2025-05-14 17:22:29 +08001511 };
1512
1513#endif
1514
b.liue9582032025-04-17 19:18:16 +08001515 ecall {
1516 compatible = "asr,ecall-event";
1517 pinctrl-names = "default";
1518 pinctrl-0 = <&ecall_pmx_func>;
1519 gpio-auto-ecall = <8>;
1520 gpio-manual-ecall = <9>;
1521 status = "disabled";
1522 };
1523
1524 usim1: usim1 {
1525 compatible = "asr,usim1";
1526 pinctrl-names = "default", "sleep";
1527 pinctrl-0 = <&usim1_pmx_func>;
1528 pinctrl-1 = <&usim1_pmx_func_sleep>;
yq.wang107f9862025-05-12 15:44:50 +08001529 edge_detect_gpio = <119>; /* GPIO19: SIM detect pin */
b.liue9582032025-04-17 19:18:16 +08001530 status = "okay";
1531 };
1532 /* set okay for this node if usim2 is needed */
1533 usim2: usim2 {
1534 compatible = "asr,usim2";
1535 pinctrl-names = "default", "sleep";
1536 pinctrl-0 = <&usim2_pmx_func>;
1537 pinctrl-1 = <&usim2_pmx_func_sleep>;
1538 edge_detect_gpio = <44>; /* GPIO44: SIM detect pin */
1539#ifdef CONFIG_ASR_DSDS
1540 status = "okay";
1541#else
1542 status = "disabled";
1543#endif
1544 };
1545 gpio_keys {
1546 compatible = "gpio-keys";
1547 #address-cells = <1>;
1548 #size-cells = <0>;
1549 /* autorepeat; */
1550 pinctrl-names = "default";
lichengzhangb746a892025-06-24 15:41:08 +08001551 pinctrl-0 = <&gpiokey_pmx_func &gpiokey_ssp2_func>;
b.liue9582032025-04-17 19:18:16 +08001552 button@1 {
1553 label = "qrcode-key";
1554 linux,code = <139>; /* KEY_MENU, refer to linux/input.h */
1555 /* NOTE:
1556 * We use the FORCE DOWNLOAD key to implement the qrcode key in DKB.
1557 * Customer SHOULD change it to any other gpios.
1558 * Because user may do the misoperation that
1559 * powerup with FDL key pressed,
1560 * then the borad will enter force download mode.
1561 */
1562 gpios = <&gpio 9 1>;
1563 gpio-key,wakeup;
1564 };
1565 };
1566
1567 audio_pa {
1568 compatible = "asrmicro,audio-pa";
1569 pinctrl-names = "default";
1570 pinctrl-0 = <&audio_pa_pmx_func>;
1571 pa-gpio = <&gpio 14 0>;
b.liub17525e2025-05-14 17:22:29 +08001572 status = "disabled";
b.liue9582032025-04-17 19:18:16 +08001573 };
b.liub17525e2025-05-14 17:22:29 +08001574 mbtk_GpioWakeUp {
1575 compatible = "mbtk,GpioWakeUp";
1576 pinctrl-names = "default", "sleep";
1577 pinctrl-0 = <&wake_pmx_func &wake_pmx_func1>;
1578 pinctrl-1 = <&wake_pmx_func_sleep>;
1579 wakeup-in-gpio = <&gpio 118 0>;
1580 wakeup-out-gpio = <&gpio 117 0>;
1581 status = "okay";
1582 };
b.liue9582032025-04-17 19:18:16 +08001583
hong.liuf2416882025-05-23 20:41:06 -07001584
1585 dtsleds{
1586 compatible = "gpio-leds";
1587 pinctrl-names = "default";
1588 pinctrl-0 = <&led_pmx_func1>;
1589 status = "okay";
1590 led0{
1591 label = "red";
1592 gpios = <&gpio 8 0>;
1593 linux,default-trigger = "pattern";
1594 led-pattern = "100:100:100";
1595 default-state = "on";
1596
1597 };
1598
1599 // led1{
1600 // label = "blue";
1601 // gpios = <&gpio 99 0>;
1602 // linux,default-trigger = "timer";
1603 // timer-delay-on = <100>;
1604 // timer-delay-off = <100>;
1605 // brightness-levels = <100>;
1606 // brightness-max = <100>;
1607 // default-state = "on";
1608 // };
1609
1610 };
1611
b.liue9582032025-04-17 19:18:16 +08001612 audio_regs {
1613 compatible = "ASRMICRO,audio-registers";
1614 reg = <0xD4050044 0x4>;
1615 status = "okay";
1616 };
1617
1618 nz3-slic {
1619 compatible = "asr,nz3-slic";
1620 pinctrl-names = "default", "sleep";
1621 pinctrl-0 = <&slic_pmx_func1 &slic_pmx_func2>;
1622 pinctrl-1 = <&slic_pmx_func1_sleep &slic_pmx_func2>;
1623 rst-gpio = <&gpio 21 0>;
1624 edge-wakeup-gpio = <&gpio 20 0>;
1625 vdd-3v3-gpio = <&gpio 127 0>;
1626 status = "disabled";
1627 };
1628 microsemi-slic {
1629 compatible = "asr,microsemi-slic";
1630 pinctrl-names = "default", "sleep";
1631 pinctrl-0 = <&slic_pmx_func1>;
1632 pinctrl-1 = <&slic_pmx_func1_sleep>;
1633 edge-wakeup-gpio = <&gpio 20 0>;
1634 vdd-3v3-gpio = <&gpio 127 0>;
1635 status = "disabled";
1636 };
1637 maxlinear-slic {
1638 compatible = "asr,maxlinear-slic";
1639 pinctrl-names = "default", "sleep";
1640 pinctrl-0 = <&slic_pmx_func1 &slic_pmx_func2>;
1641 pinctrl-1 = <&slic_pmx_func1_sleep &slic_pmx_func2>;
1642 rst-gpio = <&gpio 21 0>;
1643 edge-wakeup-gpio = <&gpio 20 0>;
1644 vdd-3v3-gpio = <&gpio 127 0>;
1645 status = "disabled";
1646 };
1647 /* deprecated, move to mfpr@d401e000
1648 lpm-board-cfg {
1649 compatible = "asr,lpm-board-cfg";
1650 wakeup-state-d1pp = <0x1>;
1651 udr-mfpr-config = <0x1B0 0xA040 0x0
1652 0x1B4 0xA040 0x0>;
1653 };
1654 */
1655};
1656#ifdef CONFIG_ASR_DSDS
1657#include "asr_pm802_2usim.dtsi"
1658#include "88pm805.dtsi"
1659#include "asr_pm803_2usim.dtsi"
1660#else
1661#include "asr_pm802.dtsi"
1662#include "88pm805.dtsi"
1663#include "asr_pm803.dtsi"
1664#endif
1665
1666#ifdef CONFIG_AB_SYSTEM
1667#include "asr1806_ab_flash_layout.dtsi"
1668#else
1669#include "asr1806_flash_layout.dtsi"
1670#endif