b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 1 | ============== |
| 2 | BPF Design Q&A |
| 3 | ============== |
| 4 | |
| 5 | BPF extensibility and applicability to networking, tracing, security |
| 6 | in the linux kernel and several user space implementations of BPF |
| 7 | virtual machine led to a number of misunderstanding on what BPF actually is. |
| 8 | This short QA is an attempt to address that and outline a direction |
| 9 | of where BPF is heading long term. |
| 10 | |
| 11 | .. contents:: |
| 12 | :local: |
| 13 | :depth: 3 |
| 14 | |
| 15 | Questions and Answers |
| 16 | ===================== |
| 17 | |
| 18 | Q: Is BPF a generic instruction set similar to x64 and arm64? |
| 19 | ------------------------------------------------------------- |
| 20 | A: NO. |
| 21 | |
| 22 | Q: Is BPF a generic virtual machine ? |
| 23 | ------------------------------------- |
| 24 | A: NO. |
| 25 | |
| 26 | BPF is generic instruction set *with* C calling convention. |
| 27 | ----------------------------------------------------------- |
| 28 | |
| 29 | Q: Why C calling convention was chosen? |
| 30 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 31 | |
| 32 | A: Because BPF programs are designed to run in the linux kernel |
| 33 | which is written in C, hence BPF defines instruction set compatible |
| 34 | with two most used architectures x64 and arm64 (and takes into |
| 35 | consideration important quirks of other architectures) and |
| 36 | defines calling convention that is compatible with C calling |
| 37 | convention of the linux kernel on those architectures. |
| 38 | |
| 39 | Q: Can multiple return values be supported in the future? |
| 40 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 41 | A: NO. BPF allows only register R0 to be used as return value. |
| 42 | |
| 43 | Q: Can more than 5 function arguments be supported in the future? |
| 44 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 45 | A: NO. BPF calling convention only allows registers R1-R5 to be used |
| 46 | as arguments. BPF is not a standalone instruction set. |
| 47 | (unlike x64 ISA that allows msft, cdecl and other conventions) |
| 48 | |
| 49 | Q: Can BPF programs access instruction pointer or return address? |
| 50 | ----------------------------------------------------------------- |
| 51 | A: NO. |
| 52 | |
| 53 | Q: Can BPF programs access stack pointer ? |
| 54 | ------------------------------------------ |
| 55 | A: NO. |
| 56 | |
| 57 | Only frame pointer (register R10) is accessible. |
| 58 | From compiler point of view it's necessary to have stack pointer. |
| 59 | For example, LLVM defines register R11 as stack pointer in its |
| 60 | BPF backend, but it makes sure that generated code never uses it. |
| 61 | |
| 62 | Q: Does C-calling convention diminishes possible use cases? |
| 63 | ----------------------------------------------------------- |
| 64 | A: YES. |
| 65 | |
| 66 | BPF design forces addition of major functionality in the form |
| 67 | of kernel helper functions and kernel objects like BPF maps with |
| 68 | seamless interoperability between them. It lets kernel call into |
| 69 | BPF programs and programs call kernel helpers with zero overhead, |
| 70 | as all of them were native C code. That is particularly the case |
| 71 | for JITed BPF programs that are indistinguishable from |
| 72 | native kernel C code. |
| 73 | |
| 74 | Q: Does it mean that 'innovative' extensions to BPF code are disallowed? |
| 75 | ------------------------------------------------------------------------ |
| 76 | A: Soft yes. |
| 77 | |
| 78 | At least for now, until BPF core has support for |
| 79 | bpf-to-bpf calls, indirect calls, loops, global variables, |
| 80 | jump tables, read-only sections, and all other normal constructs |
| 81 | that C code can produce. |
| 82 | |
| 83 | Q: Can loops be supported in a safe way? |
| 84 | ---------------------------------------- |
| 85 | A: It's not clear yet. |
| 86 | |
| 87 | BPF developers are trying to find a way to |
| 88 | support bounded loops. |
| 89 | |
| 90 | Q: What are the verifier limits? |
| 91 | -------------------------------- |
| 92 | A: The only limit known to the user space is BPF_MAXINSNS (4096). |
| 93 | It's the maximum number of instructions that the unprivileged bpf |
| 94 | program can have. The verifier has various internal limits. |
| 95 | Like the maximum number of instructions that can be explored during |
| 96 | program analysis. Currently, that limit is set to 1 million. |
| 97 | Which essentially means that the largest program can consist |
| 98 | of 1 million NOP instructions. There is a limit to the maximum number |
| 99 | of subsequent branches, a limit to the number of nested bpf-to-bpf |
| 100 | calls, a limit to the number of the verifier states per instruction, |
| 101 | a limit to the number of maps used by the program. |
| 102 | All these limits can be hit with a sufficiently complex program. |
| 103 | There are also non-numerical limits that can cause the program |
| 104 | to be rejected. The verifier used to recognize only pointer + constant |
| 105 | expressions. Now it can recognize pointer + bounded_register. |
| 106 | bpf_lookup_map_elem(key) had a requirement that 'key' must be |
| 107 | a pointer to the stack. Now, 'key' can be a pointer to map value. |
| 108 | The verifier is steadily getting 'smarter'. The limits are |
| 109 | being removed. The only way to know that the program is going to |
| 110 | be accepted by the verifier is to try to load it. |
| 111 | The bpf development process guarantees that the future kernel |
| 112 | versions will accept all bpf programs that were accepted by |
| 113 | the earlier versions. |
| 114 | |
| 115 | |
| 116 | Instruction level questions |
| 117 | --------------------------- |
| 118 | |
| 119 | Q: LD_ABS and LD_IND instructions vs C code |
| 120 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 121 | |
| 122 | Q: How come LD_ABS and LD_IND instruction are present in BPF whereas |
| 123 | C code cannot express them and has to use builtin intrinsics? |
| 124 | |
| 125 | A: This is artifact of compatibility with classic BPF. Modern |
| 126 | networking code in BPF performs better without them. |
| 127 | See 'direct packet access'. |
| 128 | |
| 129 | Q: BPF instructions mapping not one-to-one to native CPU |
| 130 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 131 | Q: It seems not all BPF instructions are one-to-one to native CPU. |
| 132 | For example why BPF_JNE and other compare and jumps are not cpu-like? |
| 133 | |
| 134 | A: This was necessary to avoid introducing flags into ISA which are |
| 135 | impossible to make generic and efficient across CPU architectures. |
| 136 | |
| 137 | Q: Why BPF_DIV instruction doesn't map to x64 div? |
| 138 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 139 | A: Because if we picked one-to-one relationship to x64 it would have made |
| 140 | it more complicated to support on arm64 and other archs. Also it |
| 141 | needs div-by-zero runtime check. |
| 142 | |
| 143 | Q: Why there is no BPF_SDIV for signed divide operation? |
| 144 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 145 | A: Because it would be rarely used. llvm errors in such case and |
| 146 | prints a suggestion to use unsigned divide instead. |
| 147 | |
| 148 | Q: Why BPF has implicit prologue and epilogue? |
| 149 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 150 | A: Because architectures like sparc have register windows and in general |
| 151 | there are enough subtle differences between architectures, so naive |
| 152 | store return address into stack won't work. Another reason is BPF has |
| 153 | to be safe from division by zero (and legacy exception path |
| 154 | of LD_ABS insn). Those instructions need to invoke epilogue and |
| 155 | return implicitly. |
| 156 | |
| 157 | Q: Why BPF_JLT and BPF_JLE instructions were not introduced in the beginning? |
| 158 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 159 | A: Because classic BPF didn't have them and BPF authors felt that compiler |
| 160 | workaround would be acceptable. Turned out that programs lose performance |
| 161 | due to lack of these compare instructions and they were added. |
| 162 | These two instructions is a perfect example what kind of new BPF |
| 163 | instructions are acceptable and can be added in the future. |
| 164 | These two already had equivalent instructions in native CPUs. |
| 165 | New instructions that don't have one-to-one mapping to HW instructions |
| 166 | will not be accepted. |
| 167 | |
| 168 | Q: BPF 32-bit subregister requirements |
| 169 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 170 | Q: BPF 32-bit subregisters have a requirement to zero upper 32-bits of BPF |
| 171 | registers which makes BPF inefficient virtual machine for 32-bit |
| 172 | CPU architectures and 32-bit HW accelerators. Can true 32-bit registers |
| 173 | be added to BPF in the future? |
| 174 | |
| 175 | A: NO. |
| 176 | |
| 177 | But some optimizations on zero-ing the upper 32 bits for BPF registers are |
| 178 | available, and can be leveraged to improve the performance of JITed BPF |
| 179 | programs for 32-bit architectures. |
| 180 | |
| 181 | Starting with version 7, LLVM is able to generate instructions that operate |
| 182 | on 32-bit subregisters, provided the option -mattr=+alu32 is passed for |
| 183 | compiling a program. Furthermore, the verifier can now mark the |
| 184 | instructions for which zero-ing the upper bits of the destination register |
| 185 | is required, and insert an explicit zero-extension (zext) instruction |
| 186 | (a mov32 variant). This means that for architectures without zext hardware |
| 187 | support, the JIT back-ends do not need to clear the upper bits for |
| 188 | subregisters written by alu32 instructions or narrow loads. Instead, the |
| 189 | back-ends simply need to support code generation for that mov32 variant, |
| 190 | and to overwrite bpf_jit_needs_zext() to make it return "true" (in order to |
| 191 | enable zext insertion in the verifier). |
| 192 | |
| 193 | Note that it is possible for a JIT back-end to have partial hardware |
| 194 | support for zext. In that case, if verifier zext insertion is enabled, |
| 195 | it could lead to the insertion of unnecessary zext instructions. Such |
| 196 | instructions could be removed by creating a simple peephole inside the JIT |
| 197 | back-end: if one instruction has hardware support for zext and if the next |
| 198 | instruction is an explicit zext, then the latter can be skipped when doing |
| 199 | the code generation. |
| 200 | |
| 201 | Q: Does BPF have a stable ABI? |
| 202 | ------------------------------ |
| 203 | A: YES. BPF instructions, arguments to BPF programs, set of helper |
| 204 | functions and their arguments, recognized return codes are all part |
| 205 | of ABI. However there is one specific exception to tracing programs |
| 206 | which are using helpers like bpf_probe_read() to walk kernel internal |
| 207 | data structures and compile with kernel internal headers. Both of these |
| 208 | kernel internals are subject to change and can break with newer kernels |
| 209 | such that the program needs to be adapted accordingly. |
| 210 | |
| 211 | Q: How much stack space a BPF program uses? |
| 212 | ------------------------------------------- |
| 213 | A: Currently all program types are limited to 512 bytes of stack |
| 214 | space, but the verifier computes the actual amount of stack used |
| 215 | and both interpreter and most JITed code consume necessary amount. |
| 216 | |
| 217 | Q: Can BPF be offloaded to HW? |
| 218 | ------------------------------ |
| 219 | A: YES. BPF HW offload is supported by NFP driver. |
| 220 | |
| 221 | Q: Does classic BPF interpreter still exist? |
| 222 | -------------------------------------------- |
| 223 | A: NO. Classic BPF programs are converted into extend BPF instructions. |
| 224 | |
| 225 | Q: Can BPF call arbitrary kernel functions? |
| 226 | ------------------------------------------- |
| 227 | A: NO. BPF programs can only call a set of helper functions which |
| 228 | is defined for every program type. |
| 229 | |
| 230 | Q: Can BPF overwrite arbitrary kernel memory? |
| 231 | --------------------------------------------- |
| 232 | A: NO. |
| 233 | |
| 234 | Tracing bpf programs can *read* arbitrary memory with bpf_probe_read() |
| 235 | and bpf_probe_read_str() helpers. Networking programs cannot read |
| 236 | arbitrary memory, since they don't have access to these helpers. |
| 237 | Programs can never read or write arbitrary memory directly. |
| 238 | |
| 239 | Q: Can BPF overwrite arbitrary user memory? |
| 240 | ------------------------------------------- |
| 241 | A: Sort-of. |
| 242 | |
| 243 | Tracing BPF programs can overwrite the user memory |
| 244 | of the current task with bpf_probe_write_user(). Every time such |
| 245 | program is loaded the kernel will print warning message, so |
| 246 | this helper is only useful for experiments and prototypes. |
| 247 | Tracing BPF programs are root only. |
| 248 | |
| 249 | Q: bpf_trace_printk() helper warning |
| 250 | ------------------------------------ |
| 251 | Q: When bpf_trace_printk() helper is used the kernel prints nasty |
| 252 | warning message. Why is that? |
| 253 | |
| 254 | A: This is done to nudge program authors into better interfaces when |
| 255 | programs need to pass data to user space. Like bpf_perf_event_output() |
| 256 | can be used to efficiently stream data via perf ring buffer. |
| 257 | BPF maps can be used for asynchronous data sharing between kernel |
| 258 | and user space. bpf_trace_printk() should only be used for debugging. |
| 259 | |
| 260 | Q: New functionality via kernel modules? |
| 261 | ---------------------------------------- |
| 262 | Q: Can BPF functionality such as new program or map types, new |
| 263 | helpers, etc be added out of kernel module code? |
| 264 | |
| 265 | A: NO. |