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192.168.1.100 / T108 / c2023d5d03be91dbb983606f0ec5e9e4ea36c8c2 / . / marvell / linux / arch / arm / boot / dts / aspeed-g4.dtsi
blob: 679d04d585a4a7a8260f44adec96467775c1706e [file] [log] [blame]
b.liue9582032025-04-17 19:18:16 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2#include <dt-bindings/clock/aspeed-clock.h>
3
4/ {
5 model = "Aspeed BMC";
6 compatible = "aspeed,ast2400";
7 #address-cells = <1>;
8 #size-cells = <1>;
9 interrupt-parent = <&vic>;
10
11 aliases {
12 i2c0 = &i2c0;
13 i2c1 = &i2c1;
14 i2c2 = &i2c2;
15 i2c3 = &i2c3;
16 i2c4 = &i2c4;
17 i2c5 = &i2c5;
18 i2c6 = &i2c6;
19 i2c7 = &i2c7;
20 i2c8 = &i2c8;
21 i2c9 = &i2c9;
22 i2c10 = &i2c10;
23 i2c11 = &i2c11;
24 i2c12 = &i2c12;
25 i2c13 = &i2c13;
26 serial0 = &uart1;
27 serial1 = &uart2;
28 serial2 = &uart3;
29 serial3 = &uart4;
30 serial4 = &uart5;
31 serial5 = &vuart;
32 };
33
34 cpus {
35 #address-cells = <1>;
36 #size-cells = <0>;
37
38 cpu@0 {
39 compatible = "arm,arm926ej-s";
40 device_type = "cpu";
41 reg = <0>;
42 };
43 };
44
45 memory@40000000 {
46 device_type = "memory";
47 reg = <0x40000000 0>;
48 };
49
50 ahb {
51 compatible = "simple-bus";
52 #address-cells = <1>;
53 #size-cells = <1>;
54 ranges;
55
56 fmc: spi@1e620000 {
57 reg = < 0x1e620000 0x94
58 0x20000000 0x10000000 >;
59 #address-cells = <1>;
60 #size-cells = <0>;
61 compatible = "aspeed,ast2400-fmc";
62 clocks = <&syscon ASPEED_CLK_AHB>;
63 status = "disabled";
64 interrupts = <19>;
65 flash@0 {
66 reg = < 0 >;
67 compatible = "jedec,spi-nor";
68 status = "disabled";
69 };
70 flash@1 {
71 reg = < 1 >;
72 compatible = "jedec,spi-nor";
73 status = "disabled";
74 };
75 flash@2 {
76 reg = < 2 >;
77 compatible = "jedec,spi-nor";
78 status = "disabled";
79 };
80 flash@3 {
81 reg = < 3 >;
82 compatible = "jedec,spi-nor";
83 status = "disabled";
84 };
85 flash@4 {
86 reg = < 4 >;
87 compatible = "jedec,spi-nor";
88 status = "disabled";
89 };
90 };
91
92 spi: spi@1e630000 {
93 reg = < 0x1e630000 0x18
94 0x30000000 0x10000000 >;
95 #address-cells = <1>;
96 #size-cells = <0>;
97 compatible = "aspeed,ast2400-spi";
98 clocks = <&syscon ASPEED_CLK_AHB>;
99 status = "disabled";
100 flash@0 {
101 reg = < 0 >;
102 compatible = "jedec,spi-nor";
103 status = "disabled";
104 };
105 };
106
107 vic: interrupt-controller@1e6c0080 {
108 compatible = "aspeed,ast2400-vic";
109 interrupt-controller;
110 #interrupt-cells = <1>;
111 valid-sources = <0xffffffff 0x0007ffff>;
112 reg = <0x1e6c0080 0x80>;
113 };
114
115 cvic: copro-interrupt-controller@1e6c2000 {
116 compatible = "aspeed,ast2400-cvic", "aspeed-cvic";
117 valid-sources = <0x7fffffff>;
118 reg = <0x1e6c2000 0x80>;
119 };
120
121 mac0: ethernet@1e660000 {
122 compatible = "aspeed,ast2400-mac", "faraday,ftgmac100";
123 reg = <0x1e660000 0x180>;
124 interrupts = <2>;
125 clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>;
126 status = "disabled";
127 };
128
129 mac1: ethernet@1e680000 {
130 compatible = "aspeed,ast2400-mac", "faraday,ftgmac100";
131 reg = <0x1e680000 0x180>;
132 interrupts = <3>;
133 clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>;
134 status = "disabled";
135 };
136
137 ehci0: usb@1e6a1000 {
138 compatible = "aspeed,ast2400-ehci", "generic-ehci";
139 reg = <0x1e6a1000 0x100>;
140 interrupts = <5>;
141 clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
142 pinctrl-names = "default";
143 pinctrl-0 = <&pinctrl_usb2h_default>;
144 status = "disabled";
145 };
146
147 uhci: usb@1e6b0000 {
148 compatible = "aspeed,ast2400-uhci", "generic-uhci";
149 reg = <0x1e6b0000 0x100>;
150 interrupts = <14>;
151 #ports = <3>;
152 clocks = <&syscon ASPEED_CLK_GATE_USBUHCICLK>;
153 status = "disabled";
154 /*
155 * No default pinmux, it will follow EHCI, use an explicit pinmux
156 * override if you don't enable EHCI
157 */
158 };
159
160 vhub: usb-vhub@1e6a0000 {
161 compatible = "aspeed,ast2400-usb-vhub";
162 reg = <0x1e6a0000 0x300>;
163 interrupts = <5>;
164 clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
165 pinctrl-names = "default";
166 pinctrl-0 = <&pinctrl_usb2d_default>;
167 status = "disabled";
168 };
169
170 apb {
171 compatible = "simple-bus";
172 #address-cells = <1>;
173 #size-cells = <1>;
174 ranges;
175
176 syscon: syscon@1e6e2000 {
177 compatible = "aspeed,ast2400-scu", "syscon", "simple-mfd";
178 reg = <0x1e6e2000 0x1a8>;
179 #address-cells = <1>;
180 #size-cells = <0>;
181 #clock-cells = <1>;
182 #reset-cells = <1>;
183
184 pinctrl: pinctrl {
185 compatible = "aspeed,g4-pinctrl";
186 };
187
188 p2a: p2a-control {
189 compatible = "aspeed,ast2400-p2a-ctrl";
190 status = "disabled";
191 };
192 };
193
194 rng: hwrng@1e6e2078 {
195 compatible = "timeriomem_rng";
196 reg = <0x1e6e2078 0x4>;
197 period = <1>;
198 quality = <100>;
199 };
200
201 adc: adc@1e6e9000 {
202 compatible = "aspeed,ast2400-adc";
203 reg = <0x1e6e9000 0xb0>;
204 clocks = <&syscon ASPEED_CLK_APB>;
205 resets = <&syscon ASPEED_RESET_ADC>;
206 #io-channel-cells = <1>;
207 status = "disabled";
208 };
209
210 sram: sram@1e720000 {
211 compatible = "mmio-sram";
212 reg = <0x1e720000 0x8000>; // 32K
213 };
214
215 sdmmc: sd-controller@1e740000 {
216 compatible = "aspeed,ast2400-sd-controller";
217 reg = <0x1e740000 0x100>;
218 #address-cells = <1>;
219 #size-cells = <1>;
220 ranges = <0 0x1e740000 0x10000>;
221 clocks = <&syscon ASPEED_CLK_GATE_SDCLK>;
222 status = "disabled";
223
224 sdhci0: sdhci@100 {
225 compatible = "aspeed,ast2400-sdhci";
226 reg = <0x100 0x100>;
227 interrupts = <26>;
228 sdhci,auto-cmd12;
229 clocks = <&syscon ASPEED_CLK_SDIO>;
230 status = "disabled";
231 };
232
233 sdhci1: sdhci@200 {
234 compatible = "aspeed,ast2400-sdhci";
235 reg = <0x200 0x100>;
236 interrupts = <26>;
237 sdhci,auto-cmd12;
238 clocks = <&syscon ASPEED_CLK_SDIO>;
239 status = "disabled";
240 };
241 };
242
243 gpio: gpio@1e780000 {
244 #gpio-cells = <2>;
245 gpio-controller;
246 compatible = "aspeed,ast2400-gpio";
247 reg = <0x1e780000 0x1000>;
248 interrupts = <20>;
249 gpio-ranges = <&pinctrl 0 0 220>;
250 clocks = <&syscon ASPEED_CLK_APB>;
251 interrupt-controller;
252 #interrupt-cells = <2>;
253 };
254
255 timer: timer@1e782000 {
256 /* This timer is a Faraday FTTMR010 derivative */
257 compatible = "aspeed,ast2400-timer";
258 reg = <0x1e782000 0x90>;
259 interrupts = <16 17 18 35 36 37 38 39>;
260 clocks = <&syscon ASPEED_CLK_APB>;
261 clock-names = "PCLK";
262 };
263
264 rtc: rtc@1e781000 {
265 compatible = "aspeed,ast2400-rtc";
266 reg = <0x1e781000 0x18>;
267 status = "disabled";
268 };
269
270 uart1: serial@1e783000 {
271 compatible = "ns16550a";
272 reg = <0x1e783000 0x20>;
273 reg-shift = <2>;
274 interrupts = <9>;
275 clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>;
276 resets = <&lpc_reset 4>;
277 no-loopback-test;
278 status = "disabled";
279 };
280
281 uart5: serial@1e784000 {
282 compatible = "ns16550a";
283 reg = <0x1e784000 0x20>;
284 reg-shift = <2>;
285 interrupts = <10>;
286 clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>;
287 no-loopback-test;
288 status = "disabled";
289 };
290
291 wdt1: watchdog@1e785000 {
292 compatible = "aspeed,ast2400-wdt";
293 reg = <0x1e785000 0x1c>;
294 clocks = <&syscon ASPEED_CLK_APB>;
295 };
296
297 wdt2: watchdog@1e785020 {
298 compatible = "aspeed,ast2400-wdt";
299 reg = <0x1e785020 0x1c>;
300 clocks = <&syscon ASPEED_CLK_APB>;
301 };
302
303 pwm_tacho: pwm-tacho-controller@1e786000 {
304 compatible = "aspeed,ast2400-pwm-tacho";
305 #address-cells = <1>;
306 #size-cells = <0>;
307 reg = <0x1e786000 0x1000>;
308 clocks = <&syscon ASPEED_CLK_24M>;
309 resets = <&syscon ASPEED_RESET_PWM>;
310 status = "disabled";
311 };
312
313 vuart: serial@1e787000 {
314 compatible = "aspeed,ast2400-vuart";
315 reg = <0x1e787000 0x40>;
316 reg-shift = <2>;
317 interrupts = <8>;
318 clocks = <&syscon ASPEED_CLK_APB>;
319 no-loopback-test;
320 status = "disabled";
321 };
322
323 lpc: lpc@1e789000 {
324 compatible = "aspeed,ast2400-lpc", "simple-mfd";
325 reg = <0x1e789000 0x1000>;
326
327 #address-cells = <1>;
328 #size-cells = <1>;
329 ranges = <0x0 0x1e789000 0x1000>;
330
331 lpc_bmc: lpc-bmc@0 {
332 compatible = "aspeed,ast2400-lpc-bmc";
333 reg = <0x0 0x80>;
334 };
335
336 lpc_host: lpc-host@80 {
337 compatible = "aspeed,ast2400-lpc-host", "simple-mfd", "syscon";
338 reg = <0x80 0x1e0>;
339 reg-io-width = <4>;
340
341 #address-cells = <1>;
342 #size-cells = <1>;
343 ranges = <0x0 0x80 0x1e0>;
344
345 lpc_ctrl: lpc-ctrl@0 {
346 compatible = "aspeed,ast2400-lpc-ctrl";
347 reg = <0x0 0x80>;
348 clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
349 status = "disabled";
350 };
351
352 lpc_snoop: lpc-snoop@0 {
353 compatible = "aspeed,ast2400-lpc-snoop";
354 reg = <0x0 0x80>;
355 interrupts = <8>;
356 status = "disabled";
357 };
358
359 lhc: lhc@20 {
360 compatible = "aspeed,ast2400-lhc";
361 reg = <0x20 0x24 0x48 0x8>;
362 };
363
364 lpc_reset: reset-controller@18 {
365 compatible = "aspeed,ast2400-lpc-reset";
366 reg = <0x18 0x4>;
367 #reset-cells = <1>;
368 };
369
370 ibt: ibt@c0 {
371 compatible = "aspeed,ast2400-ibt-bmc";
372 reg = <0xc0 0x18>;
373 interrupts = <8>;
374 clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
375 status = "disabled";
376 };
377 };
378 };
379
380 uart2: serial@1e78d000 {
381 compatible = "ns16550a";
382 reg = <0x1e78d000 0x20>;
383 reg-shift = <2>;
384 interrupts = <32>;
385 clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>;
386 resets = <&lpc_reset 5>;
387 no-loopback-test;
388 status = "disabled";
389 };
390
391 uart3: serial@1e78e000 {
392 compatible = "ns16550a";
393 reg = <0x1e78e000 0x20>;
394 reg-shift = <2>;
395 interrupts = <33>;
396 clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>;
397 resets = <&lpc_reset 6>;
398 no-loopback-test;
399 status = "disabled";
400 };
401
402 uart4: serial@1e78f000 {
403 compatible = "ns16550a";
404 reg = <0x1e78f000 0x20>;
405 reg-shift = <2>;
406 interrupts = <34>;
407 clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>;
408 resets = <&lpc_reset 7>;
409 no-loopback-test;
410 status = "disabled";
411 };
412
413 i2c: bus@1e78a000 {
414 compatible = "simple-bus";
415 #address-cells = <1>;
416 #size-cells = <1>;
417 ranges = <0 0x1e78a000 0x1000>;
418 };
419 };
420 };
421};
422
423&i2c {
424 i2c_ic: interrupt-controller@0 {
425 #interrupt-cells = <1>;
426 compatible = "aspeed,ast2400-i2c-ic";
427 reg = <0x0 0x40>;
428 interrupts = <12>;
429 interrupt-controller;
430 };
431
432 i2c0: i2c-bus@40 {
433 #address-cells = <1>;
434 #size-cells = <0>;
435 #interrupt-cells = <1>;
436
437 reg = <0x40 0x40>;
438 compatible = "aspeed,ast2400-i2c-bus";
439 clocks = <&syscon ASPEED_CLK_APB>;
440 resets = <&syscon ASPEED_RESET_I2C>;
441 bus-frequency = <100000>;
442 interrupts = <0>;
443 interrupt-parent = <&i2c_ic>;
444 status = "disabled";
445 /* Does not need pinctrl properties */
446 };
447
448 i2c1: i2c-bus@80 {
449 #address-cells = <1>;
450 #size-cells = <0>;
451 #interrupt-cells = <1>;
452
453 reg = <0x80 0x40>;
454 compatible = "aspeed,ast2400-i2c-bus";
455 clocks = <&syscon ASPEED_CLK_APB>;
456 resets = <&syscon ASPEED_RESET_I2C>;
457 bus-frequency = <100000>;
458 interrupts = <1>;
459 interrupt-parent = <&i2c_ic>;
460 status = "disabled";
461 /* Does not need pinctrl properties */
462 };
463
464 i2c2: i2c-bus@c0 {
465 #address-cells = <1>;
466 #size-cells = <0>;
467 #interrupt-cells = <1>;
468
469 reg = <0xc0 0x40>;
470 compatible = "aspeed,ast2400-i2c-bus";
471 clocks = <&syscon ASPEED_CLK_APB>;
472 resets = <&syscon ASPEED_RESET_I2C>;
473 bus-frequency = <100000>;
474 interrupts = <2>;
475 interrupt-parent = <&i2c_ic>;
476 pinctrl-names = "default";
477 pinctrl-0 = <&pinctrl_i2c3_default>;
478 status = "disabled";
479 };
480
481 i2c3: i2c-bus@100 {
482 #address-cells = <1>;
483 #size-cells = <0>;
484 #interrupt-cells = <1>;
485
486 reg = <0x100 0x40>;
487 compatible = "aspeed,ast2400-i2c-bus";
488 clocks = <&syscon ASPEED_CLK_APB>;
489 resets = <&syscon ASPEED_RESET_I2C>;
490 bus-frequency = <100000>;
491 interrupts = <3>;
492 interrupt-parent = <&i2c_ic>;
493 pinctrl-names = "default";
494 pinctrl-0 = <&pinctrl_i2c4_default>;
495 status = "disabled";
496 };
497
498 i2c4: i2c-bus@140 {
499 #address-cells = <1>;
500 #size-cells = <0>;
501 #interrupt-cells = <1>;
502
503 reg = <0x140 0x40>;
504 compatible = "aspeed,ast2400-i2c-bus";
505 clocks = <&syscon ASPEED_CLK_APB>;
506 resets = <&syscon ASPEED_RESET_I2C>;
507 bus-frequency = <100000>;
508 interrupts = <4>;
509 interrupt-parent = <&i2c_ic>;
510 pinctrl-names = "default";
511 pinctrl-0 = <&pinctrl_i2c5_default>;
512 status = "disabled";
513 };
514
515 i2c5: i2c-bus@180 {
516 #address-cells = <1>;
517 #size-cells = <0>;
518 #interrupt-cells = <1>;
519
520 reg = <0x180 0x40>;
521 compatible = "aspeed,ast2400-i2c-bus";
522 clocks = <&syscon ASPEED_CLK_APB>;
523 resets = <&syscon ASPEED_RESET_I2C>;
524 bus-frequency = <100000>;
525 interrupts = <5>;
526 interrupt-parent = <&i2c_ic>;
527 pinctrl-names = "default";
528 pinctrl-0 = <&pinctrl_i2c6_default>;
529 status = "disabled";
530 };
531
532 i2c6: i2c-bus@1c0 {
533 #address-cells = <1>;
534 #size-cells = <0>;
535 #interrupt-cells = <1>;
536
537 reg = <0x1c0 0x40>;
538 compatible = "aspeed,ast2400-i2c-bus";
539 clocks = <&syscon ASPEED_CLK_APB>;
540 resets = <&syscon ASPEED_RESET_I2C>;
541 bus-frequency = <100000>;
542 interrupts = <6>;
543 interrupt-parent = <&i2c_ic>;
544 pinctrl-names = "default";
545 pinctrl-0 = <&pinctrl_i2c7_default>;
546 status = "disabled";
547 };
548
549 i2c7: i2c-bus@300 {
550 #address-cells = <1>;
551 #size-cells = <0>;
552 #interrupt-cells = <1>;
553
554 reg = <0x300 0x40>;
555 compatible = "aspeed,ast2400-i2c-bus";
556 clocks = <&syscon ASPEED_CLK_APB>;
557 resets = <&syscon ASPEED_RESET_I2C>;
558 bus-frequency = <100000>;
559 interrupts = <7>;
560 interrupt-parent = <&i2c_ic>;
561 pinctrl-names = "default";
562 pinctrl-0 = <&pinctrl_i2c8_default>;
563 status = "disabled";
564 };
565
566 i2c8: i2c-bus@340 {
567 #address-cells = <1>;
568 #size-cells = <0>;
569 #interrupt-cells = <1>;
570
571 reg = <0x340 0x40>;
572 compatible = "aspeed,ast2400-i2c-bus";
573 clocks = <&syscon ASPEED_CLK_APB>;
574 resets = <&syscon ASPEED_RESET_I2C>;
575 bus-frequency = <100000>;
576 interrupts = <8>;
577 interrupt-parent = <&i2c_ic>;
578 pinctrl-names = "default";
579 pinctrl-0 = <&pinctrl_i2c9_default>;
580 status = "disabled";
581 };
582
583 i2c9: i2c-bus@380 {
584 #address-cells = <1>;
585 #size-cells = <0>;
586 #interrupt-cells = <1>;
587
588 reg = <0x380 0x40>;
589 compatible = "aspeed,ast2400-i2c-bus";
590 clocks = <&syscon ASPEED_CLK_APB>;
591 resets = <&syscon ASPEED_RESET_I2C>;
592 bus-frequency = <100000>;
593 interrupts = <9>;
594 interrupt-parent = <&i2c_ic>;
595 pinctrl-names = "default";
596 pinctrl-0 = <&pinctrl_i2c10_default>;
597 status = "disabled";
598 };
599
600 i2c10: i2c-bus@3c0 {
601 #address-cells = <1>;
602 #size-cells = <0>;
603 #interrupt-cells = <1>;
604
605 reg = <0x3c0 0x40>;
606 compatible = "aspeed,ast2400-i2c-bus";
607 clocks = <&syscon ASPEED_CLK_APB>;
608 resets = <&syscon ASPEED_RESET_I2C>;
609 bus-frequency = <100000>;
610 interrupts = <10>;
611 interrupt-parent = <&i2c_ic>;
612 pinctrl-names = "default";
613 pinctrl-0 = <&pinctrl_i2c11_default>;
614 status = "disabled";
615 };
616
617 i2c11: i2c-bus@400 {
618 #address-cells = <1>;
619 #size-cells = <0>;
620 #interrupt-cells = <1>;
621
622 reg = <0x400 0x40>;
623 compatible = "aspeed,ast2400-i2c-bus";
624 clocks = <&syscon ASPEED_CLK_APB>;
625 resets = <&syscon ASPEED_RESET_I2C>;
626 bus-frequency = <100000>;
627 interrupts = <11>;
628 interrupt-parent = <&i2c_ic>;
629 pinctrl-names = "default";
630 pinctrl-0 = <&pinctrl_i2c12_default>;
631 status = "disabled";
632 };
633
634 i2c12: i2c-bus@440 {
635 #address-cells = <1>;
636 #size-cells = <0>;
637 #interrupt-cells = <1>;
638
639 reg = <0x440 0x40>;
640 compatible = "aspeed,ast2400-i2c-bus";
641 clocks = <&syscon ASPEED_CLK_APB>;
642 resets = <&syscon ASPEED_RESET_I2C>;
643 bus-frequency = <100000>;
644 interrupts = <12>;
645 interrupt-parent = <&i2c_ic>;
646 pinctrl-names = "default";
647 pinctrl-0 = <&pinctrl_i2c13_default>;
648 status = "disabled";
649 };
650
651 i2c13: i2c-bus@480 {
652 #address-cells = <1>;
653 #size-cells = <0>;
654 #interrupt-cells = <1>;
655
656 reg = <0x480 0x40>;
657 compatible = "aspeed,ast2400-i2c-bus";
658 clocks = <&syscon ASPEED_CLK_APB>;
659 resets = <&syscon ASPEED_RESET_I2C>;
660 bus-frequency = <100000>;
661 interrupts = <13>;
662 interrupt-parent = <&i2c_ic>;
663 pinctrl-names = "default";
664 pinctrl-0 = <&pinctrl_i2c14_default>;
665 status = "disabled";
666 };
667};
668
669&pinctrl {
670 pinctrl_acpi_default: acpi_default {
671 function = "ACPI";
672 groups = "ACPI";
673 };
674
675 pinctrl_adc0_default: adc0_default {
676 function = "ADC0";
677 groups = "ADC0";
678 };
679
680 pinctrl_adc1_default: adc1_default {
681 function = "ADC1";
682 groups = "ADC1";
683 };
684
685 pinctrl_adc10_default: adc10_default {
686 function = "ADC10";
687 groups = "ADC10";
688 };
689
690 pinctrl_adc11_default: adc11_default {
691 function = "ADC11";
692 groups = "ADC11";
693 };
694
695 pinctrl_adc12_default: adc12_default {
696 function = "ADC12";
697 groups = "ADC12";
698 };
699
700 pinctrl_adc13_default: adc13_default {
701 function = "ADC13";
702 groups = "ADC13";
703 };
704
705 pinctrl_adc14_default: adc14_default {
706 function = "ADC14";
707 groups = "ADC14";
708 };
709
710 pinctrl_adc15_default: adc15_default {
711 function = "ADC15";
712 groups = "ADC15";
713 };
714
715 pinctrl_adc2_default: adc2_default {
716 function = "ADC2";
717 groups = "ADC2";
718 };
719
720 pinctrl_adc3_default: adc3_default {
721 function = "ADC3";
722 groups = "ADC3";
723 };
724
725 pinctrl_adc4_default: adc4_default {
726 function = "ADC4";
727 groups = "ADC4";
728 };
729
730 pinctrl_adc5_default: adc5_default {
731 function = "ADC5";
732 groups = "ADC5";
733 };
734
735 pinctrl_adc6_default: adc6_default {
736 function = "ADC6";
737 groups = "ADC6";
738 };
739
740 pinctrl_adc7_default: adc7_default {
741 function = "ADC7";
742 groups = "ADC7";
743 };
744
745 pinctrl_adc8_default: adc8_default {
746 function = "ADC8";
747 groups = "ADC8";
748 };
749
750 pinctrl_adc9_default: adc9_default {
751 function = "ADC9";
752 groups = "ADC9";
753 };
754
755 pinctrl_bmcint_default: bmcint_default {
756 function = "BMCINT";
757 groups = "BMCINT";
758 };
759
760 pinctrl_ddcclk_default: ddcclk_default {
761 function = "DDCCLK";
762 groups = "DDCCLK";
763 };
764
765 pinctrl_ddcdat_default: ddcdat_default {
766 function = "DDCDAT";
767 groups = "DDCDAT";
768 };
769
770 pinctrl_extrst_default: extrst_default {
771 function = "EXTRST";
772 groups = "EXTRST";
773 };
774
775 pinctrl_flack_default: flack_default {
776 function = "FLACK";
777 groups = "FLACK";
778 };
779
780 pinctrl_flbusy_default: flbusy_default {
781 function = "FLBUSY";
782 groups = "FLBUSY";
783 };
784
785 pinctrl_flwp_default: flwp_default {
786 function = "FLWP";
787 groups = "FLWP";
788 };
789
790 pinctrl_gpid_default: gpid_default {
791 function = "GPID";
792 groups = "GPID";
793 };
794
795 pinctrl_gpid0_default: gpid0_default {
796 function = "GPID0";
797 groups = "GPID0";
798 };
799
800 pinctrl_gpid2_default: gpid2_default {
801 function = "GPID2";
802 groups = "GPID2";
803 };
804
805 pinctrl_gpid4_default: gpid4_default {
806 function = "GPID4";
807 groups = "GPID4";
808 };
809
810 pinctrl_gpid6_default: gpid6_default {
811 function = "GPID6";
812 groups = "GPID6";
813 };
814
815 pinctrl_gpie0_default: gpie0_default {
816 function = "GPIE0";
817 groups = "GPIE0";
818 };
819
820 pinctrl_gpie2_default: gpie2_default {
821 function = "GPIE2";
822 groups = "GPIE2";
823 };
824
825 pinctrl_gpie4_default: gpie4_default {
826 function = "GPIE4";
827 groups = "GPIE4";
828 };
829
830 pinctrl_gpie6_default: gpie6_default {
831 function = "GPIE6";
832 groups = "GPIE6";
833 };
834
835 pinctrl_i2c10_default: i2c10_default {
836 function = "I2C10";
837 groups = "I2C10";
838 };
839
840 pinctrl_i2c11_default: i2c11_default {
841 function = "I2C11";
842 groups = "I2C11";
843 };
844
845 pinctrl_i2c12_default: i2c12_default {
846 function = "I2C12";
847 groups = "I2C12";
848 };
849
850 pinctrl_i2c13_default: i2c13_default {
851 function = "I2C13";
852 groups = "I2C13";
853 };
854
855 pinctrl_i2c14_default: i2c14_default {
856 function = "I2C14";
857 groups = "I2C14";
858 };
859
860 pinctrl_i2c3_default: i2c3_default {
861 function = "I2C3";
862 groups = "I2C3";
863 };
864
865 pinctrl_i2c4_default: i2c4_default {
866 function = "I2C4";
867 groups = "I2C4";
868 };
869
870 pinctrl_i2c5_default: i2c5_default {
871 function = "I2C5";
872 groups = "I2C5";
873 };
874
875 pinctrl_i2c6_default: i2c6_default {
876 function = "I2C6";
877 groups = "I2C6";
878 };
879
880 pinctrl_i2c7_default: i2c7_default {
881 function = "I2C7";
882 groups = "I2C7";
883 };
884
885 pinctrl_i2c8_default: i2c8_default {
886 function = "I2C8";
887 groups = "I2C8";
888 };
889
890 pinctrl_i2c9_default: i2c9_default {
891 function = "I2C9";
892 groups = "I2C9";
893 };
894
895 pinctrl_lpcpd_default: lpcpd_default {
896 function = "LPCPD";
897 groups = "LPCPD";
898 };
899
900 pinctrl_lpcpme_default: lpcpme_default {
901 function = "LPCPME";
902 groups = "LPCPME";
903 };
904
905 pinctrl_lpcrst_default: lpcrst_default {
906 function = "LPCRST";
907 groups = "LPCRST";
908 };
909
910 pinctrl_lpcsmi_default: lpcsmi_default {
911 function = "LPCSMI";
912 groups = "LPCSMI";
913 };
914
915 pinctrl_mac1link_default: mac1link_default {
916 function = "MAC1LINK";
917 groups = "MAC1LINK";
918 };
919
920 pinctrl_mac2link_default: mac2link_default {
921 function = "MAC2LINK";
922 groups = "MAC2LINK";
923 };
924
925 pinctrl_mdio1_default: mdio1_default {
926 function = "MDIO1";
927 groups = "MDIO1";
928 };
929
930 pinctrl_mdio2_default: mdio2_default {
931 function = "MDIO2";
932 groups = "MDIO2";
933 };
934
935 pinctrl_ncts1_default: ncts1_default {
936 function = "NCTS1";
937 groups = "NCTS1";
938 };
939
940 pinctrl_ncts2_default: ncts2_default {
941 function = "NCTS2";
942 groups = "NCTS2";
943 };
944
945 pinctrl_ncts3_default: ncts3_default {
946 function = "NCTS3";
947 groups = "NCTS3";
948 };
949
950 pinctrl_ncts4_default: ncts4_default {
951 function = "NCTS4";
952 groups = "NCTS4";
953 };
954
955 pinctrl_ndcd1_default: ndcd1_default {
956 function = "NDCD1";
957 groups = "NDCD1";
958 };
959
960 pinctrl_ndcd2_default: ndcd2_default {
961 function = "NDCD2";
962 groups = "NDCD2";
963 };
964
965 pinctrl_ndcd3_default: ndcd3_default {
966 function = "NDCD3";
967 groups = "NDCD3";
968 };
969
970 pinctrl_ndcd4_default: ndcd4_default {
971 function = "NDCD4";
972 groups = "NDCD4";
973 };
974
975 pinctrl_ndsr1_default: ndsr1_default {
976 function = "NDSR1";
977 groups = "NDSR1";
978 };
979
980 pinctrl_ndsr2_default: ndsr2_default {
981 function = "NDSR2";
982 groups = "NDSR2";
983 };
984
985 pinctrl_ndsr3_default: ndsr3_default {
986 function = "NDSR3";
987 groups = "NDSR3";
988 };
989
990 pinctrl_ndsr4_default: ndsr4_default {
991 function = "NDSR4";
992 groups = "NDSR4";
993 };
994
995 pinctrl_ndtr1_default: ndtr1_default {
996 function = "NDTR1";
997 groups = "NDTR1";
998 };
999
1000 pinctrl_ndtr2_default: ndtr2_default {
1001 function = "NDTR2";
1002 groups = "NDTR2";
1003 };
1004
1005 pinctrl_ndtr3_default: ndtr3_default {
1006 function = "NDTR3";
1007 groups = "NDTR3";
1008 };
1009
1010 pinctrl_ndtr4_default: ndtr4_default {
1011 function = "NDTR4";
1012 groups = "NDTR4";
1013 };
1014
1015 pinctrl_ndts4_default: ndts4_default {
1016 function = "NDTS4";
1017 groups = "NDTS4";
1018 };
1019
1020 pinctrl_nri1_default: nri1_default {
1021 function = "NRI1";
1022 groups = "NRI1";
1023 };
1024
1025 pinctrl_nri2_default: nri2_default {
1026 function = "NRI2";
1027 groups = "NRI2";
1028 };
1029
1030 pinctrl_nri3_default: nri3_default {
1031 function = "NRI3";
1032 groups = "NRI3";
1033 };
1034
1035 pinctrl_nri4_default: nri4_default {
1036 function = "NRI4";
1037 groups = "NRI4";
1038 };
1039
1040 pinctrl_nrts1_default: nrts1_default {
1041 function = "NRTS1";
1042 groups = "NRTS1";
1043 };
1044
1045 pinctrl_nrts2_default: nrts2_default {
1046 function = "NRTS2";
1047 groups = "NRTS2";
1048 };
1049
1050 pinctrl_nrts3_default: nrts3_default {
1051 function = "NRTS3";
1052 groups = "NRTS3";
1053 };
1054
1055 pinctrl_oscclk_default: oscclk_default {
1056 function = "OSCCLK";
1057 groups = "OSCCLK";
1058 };
1059
1060 pinctrl_pwm0_default: pwm0_default {
1061 function = "PWM0";
1062 groups = "PWM0";
1063 };
1064
1065 pinctrl_pwm1_default: pwm1_default {
1066 function = "PWM1";
1067 groups = "PWM1";
1068 };
1069
1070 pinctrl_pwm2_default: pwm2_default {
1071 function = "PWM2";
1072 groups = "PWM2";
1073 };
1074
1075 pinctrl_pwm3_default: pwm3_default {
1076 function = "PWM3";
1077 groups = "PWM3";
1078 };
1079
1080 pinctrl_pwm4_default: pwm4_default {
1081 function = "PWM4";
1082 groups = "PWM4";
1083 };
1084
1085 pinctrl_pwm5_default: pwm5_default {
1086 function = "PWM5";
1087 groups = "PWM5";
1088 };
1089
1090 pinctrl_pwm6_default: pwm6_default {
1091 function = "PWM6";
1092 groups = "PWM6";
1093 };
1094
1095 pinctrl_pwm7_default: pwm7_default {
1096 function = "PWM7";
1097 groups = "PWM7";
1098 };
1099
1100 pinctrl_rgmii1_default: rgmii1_default {
1101 function = "RGMII1";
1102 groups = "RGMII1";
1103 };
1104
1105 pinctrl_rgmii2_default: rgmii2_default {
1106 function = "RGMII2";
1107 groups = "RGMII2";
1108 };
1109
1110 pinctrl_rmii1_default: rmii1_default {
1111 function = "RMII1";
1112 groups = "RMII1";
1113 };
1114
1115 pinctrl_rmii2_default: rmii2_default {
1116 function = "RMII2";
1117 groups = "RMII2";
1118 };
1119
1120 pinctrl_rom16_default: rom16_default {
1121 function = "ROM16";
1122 groups = "ROM16";
1123 };
1124
1125 pinctrl_rom8_default: rom8_default {
1126 function = "ROM8";
1127 groups = "ROM8";
1128 };
1129
1130 pinctrl_romcs1_default: romcs1_default {
1131 function = "ROMCS1";
1132 groups = "ROMCS1";
1133 };
1134
1135 pinctrl_romcs2_default: romcs2_default {
1136 function = "ROMCS2";
1137 groups = "ROMCS2";
1138 };
1139
1140 pinctrl_romcs3_default: romcs3_default {
1141 function = "ROMCS3";
1142 groups = "ROMCS3";
1143 };
1144
1145 pinctrl_romcs4_default: romcs4_default {
1146 function = "ROMCS4";
1147 groups = "ROMCS4";
1148 };
1149
1150 pinctrl_rxd1_default: rxd1_default {
1151 function = "RXD1";
1152 groups = "RXD1";
1153 };
1154
1155 pinctrl_rxd2_default: rxd2_default {
1156 function = "RXD2";
1157 groups = "RXD2";
1158 };
1159
1160 pinctrl_rxd3_default: rxd3_default {
1161 function = "RXD3";
1162 groups = "RXD3";
1163 };
1164
1165 pinctrl_rxd4_default: rxd4_default {
1166 function = "RXD4";
1167 groups = "RXD4";
1168 };
1169
1170 pinctrl_salt1_default: salt1_default {
1171 function = "SALT1";
1172 groups = "SALT1";
1173 };
1174
1175 pinctrl_salt2_default: salt2_default {
1176 function = "SALT2";
1177 groups = "SALT2";
1178 };
1179
1180 pinctrl_salt3_default: salt3_default {
1181 function = "SALT3";
1182 groups = "SALT3";
1183 };
1184
1185 pinctrl_salt4_default: salt4_default {
1186 function = "SALT4";
1187 groups = "SALT4";
1188 };
1189
1190 pinctrl_sd1_default: sd1_default {
1191 function = "SD1";
1192 groups = "SD1";
1193 };
1194
1195 pinctrl_sd2_default: sd2_default {
1196 function = "SD2";
1197 groups = "SD2";
1198 };
1199
1200 pinctrl_sgpmck_default: sgpmck_default {
1201 function = "SGPMCK";
1202 groups = "SGPMCK";
1203 };
1204
1205 pinctrl_sgpmi_default: sgpmi_default {
1206 function = "SGPMI";
1207 groups = "SGPMI";
1208 };
1209
1210 pinctrl_sgpmld_default: sgpmld_default {
1211 function = "SGPMLD";
1212 groups = "SGPMLD";
1213 };
1214
1215 pinctrl_sgpmo_default: sgpmo_default {
1216 function = "SGPMO";
1217 groups = "SGPMO";
1218 };
1219
1220 pinctrl_sgpsck_default: sgpsck_default {
1221 function = "SGPSCK";
1222 groups = "SGPSCK";
1223 };
1224
1225 pinctrl_sgpsi0_default: sgpsi0_default {
1226 function = "SGPSI0";
1227 groups = "SGPSI0";
1228 };
1229
1230 pinctrl_sgpsi1_default: sgpsi1_default {
1231 function = "SGPSI1";
1232 groups = "SGPSI1";
1233 };
1234
1235 pinctrl_sgpsld_default: sgpsld_default {
1236 function = "SGPSLD";
1237 groups = "SGPSLD";
1238 };
1239
1240 pinctrl_sioonctrl_default: sioonctrl_default {
1241 function = "SIOONCTRL";
1242 groups = "SIOONCTRL";
1243 };
1244
1245 pinctrl_siopbi_default: siopbi_default {
1246 function = "SIOPBI";
1247 groups = "SIOPBI";
1248 };
1249
1250 pinctrl_siopbo_default: siopbo_default {
1251 function = "SIOPBO";
1252 groups = "SIOPBO";
1253 };
1254
1255 pinctrl_siopwreq_default: siopwreq_default {
1256 function = "SIOPWREQ";
1257 groups = "SIOPWREQ";
1258 };
1259
1260 pinctrl_siopwrgd_default: siopwrgd_default {
1261 function = "SIOPWRGD";
1262 groups = "SIOPWRGD";
1263 };
1264
1265 pinctrl_sios3_default: sios3_default {
1266 function = "SIOS3";
1267 groups = "SIOS3";
1268 };
1269
1270 pinctrl_sios5_default: sios5_default {
1271 function = "SIOS5";
1272 groups = "SIOS5";
1273 };
1274
1275 pinctrl_siosci_default: siosci_default {
1276 function = "SIOSCI";
1277 groups = "SIOSCI";
1278 };
1279
1280 pinctrl_spi1_default: spi1_default {
1281 function = "SPI1";
1282 groups = "SPI1";
1283 };
1284
1285 pinctrl_spi1debug_default: spi1debug_default {
1286 function = "SPI1DEBUG";
1287 groups = "SPI1DEBUG";
1288 };
1289
1290 pinctrl_spi1passthru_default: spi1passthru_default {
1291 function = "SPI1PASSTHRU";
1292 groups = "SPI1PASSTHRU";
1293 };
1294
1295 pinctrl_spics1_default: spics1_default {
1296 function = "SPICS1";
1297 groups = "SPICS1";
1298 };
1299
1300 pinctrl_timer3_default: timer3_default {
1301 function = "TIMER3";
1302 groups = "TIMER3";
1303 };
1304
1305 pinctrl_timer4_default: timer4_default {
1306 function = "TIMER4";
1307 groups = "TIMER4";
1308 };
1309
1310 pinctrl_timer5_default: timer5_default {
1311 function = "TIMER5";
1312 groups = "TIMER5";
1313 };
1314
1315 pinctrl_timer6_default: timer6_default {
1316 function = "TIMER6";
1317 groups = "TIMER6";
1318 };
1319
1320 pinctrl_timer7_default: timer7_default {
1321 function = "TIMER7";
1322 groups = "TIMER7";
1323 };
1324
1325 pinctrl_timer8_default: timer8_default {
1326 function = "TIMER8";
1327 groups = "TIMER8";
1328 };
1329
1330 pinctrl_txd1_default: txd1_default {
1331 function = "TXD1";
1332 groups = "TXD1";
1333 };
1334
1335 pinctrl_txd2_default: txd2_default {
1336 function = "TXD2";
1337 groups = "TXD2";
1338 };
1339
1340 pinctrl_txd3_default: txd3_default {
1341 function = "TXD3";
1342 groups = "TXD3";
1343 };
1344
1345 pinctrl_txd4_default: txd4_default {
1346 function = "TXD4";
1347 groups = "TXD4";
1348 };
1349
1350 pinctrl_uart6_default: uart6_default {
1351 function = "UART6";
1352 groups = "UART6";
1353 };
1354
1355 pinctrl_usbcki_default: usbcki_default {
1356 function = "USBCKI";
1357 groups = "USBCKI";
1358 };
1359
1360 pinctrl_usb2h_default: usb2h_default {
1361 function = "USB2H1";
1362 groups = "USB2H1";
1363 };
1364
1365 pinctrl_usb2d_default: usb2d_default {
1366 function = "USB2D1";
1367 groups = "USB2D1";
1368 };
1369
1370 pinctrl_vgabios_rom_default: vgabios_rom_default {
1371 function = "VGABIOS_ROM";
1372 groups = "VGABIOS_ROM";
1373 };
1374
1375 pinctrl_vgahs_default: vgahs_default {
1376 function = "VGAHS";
1377 groups = "VGAHS";
1378 };
1379
1380 pinctrl_vgavs_default: vgavs_default {
1381 function = "VGAVS";
1382 groups = "VGAVS";
1383 };
1384
1385 pinctrl_vpi18_default: vpi18_default {
1386 function = "VPI18";
1387 groups = "VPI18";
1388 };
1389
1390 pinctrl_vpi24_default: vpi24_default {
1391 function = "VPI24";
1392 groups = "VPI24";
1393 };
1394
1395 pinctrl_vpi30_default: vpi30_default {
1396 function = "VPI30";
1397 groups = "VPI30";
1398 };
1399
1400 pinctrl_vpo12_default: vpo12_default {
1401 function = "VPO12";
1402 groups = "VPO12";
1403 };
1404
1405 pinctrl_vpo24_default: vpo24_default {
1406 function = "VPO24";
1407 groups = "VPO24";
1408 };
1409
1410 pinctrl_wdtrst1_default: wdtrst1_default {
1411 function = "WDTRST1";
1412 groups = "WDTRST1";
1413 };
1414
1415 pinctrl_wdtrst2_default: wdtrst2_default {
1416 function = "WDTRST2";
1417 groups = "WDTRST2";
1418 };
1419};