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192.168.1.100 / T108 / c2023d5d03be91dbb983606f0ec5e9e4ea36c8c2 / . / marvell / linux / arch / arm / boot / dts / asr1803-p401-asr5811.dts
blob: afcf999b1525787dff90a7d90dc7ad8506626d0b [file] [log] [blame]
b.liue9582032025-04-17 19:18:16 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2021 ASR Technology Group Ltd.
4 */
5
6/dts-v1/;
7#include "asr1803.dtsi"
8
9/ {
10 model = "ASR 1803(FALCON) Board EVB";
11 compatible = "asr,1803-evb", "asr,1803";
12
13 chosen {
14 bootargs = "root=/dev/mtdblock5 rootfstype=squashfs init=/etc/preinit noinitrd console=ttyS0,115200 mem=128M";
15 };
16
17 memory {
18 reg = <0x00000000 0x10000000>;
19 };
20
21 firmware {
22 optee {
23 compatible = "linaro,optee-tz";
24 method = "smc";
25 };
26 };
27
28 soc {
29 axi@d4200000 { /* AXI */
30 usbphy: usbphy@d4207000 {
31 status = "okay";
32 };
33 udc: udc@d4208000 {
34 enable-vbuson-int = <0x1>;
35 /* no-acchg-det; */
36 status = "okay";
37 };
38 ehci: ehci@d4208100 {
39 status = "okay";
40 };
41 otg: otg@d4208100 {
42 status = "disabled";
43 pinctrl-names = "default";
44 pinctrl-0 = <&otg_vbus_func>;
45 otg,use-gpio-vbus;
46 gpio-num = <122>;
47 };
48 eth0: asr-eth@0xd4281800 {
49 compatible = "asr,asr-eth";
50 pinctrl-names = "default", "rgmii-pins";
51 pinctrl-0 = <&emac_pmx_func0 &emac_pmx_func2 &emac_pmx_func3>;
52 pinctrl-1 = <&emac_pmx_func0 &emac_pmx_func1 &emac_pmx_func2 &emac_pmx_func3>;
53 reg = <0xd4281800 0x200>;
54 interrupts = <10 11>;
55 lpm-qos = <PM_QOS_CPUIDLE_BLOCK_AXI>;
56 clocks = <&soc_clocks ASR1803_CLK_EMAC>;
57 clock-names = "emac-clk";
58 status = "okay";
59
60 reset-gpio = <&gpio 23 0>;
61 reset-active-low;
62
63 reset-delays-us = <0 100000 100000>;
64
65 clk-tuning-enable;
66 /* clk-config(32bit)
67 *
68 * clk_sel(clk-config[23:16])
69 * RGMII:
70 * tx | clk_sel: 0 - from external RX clock
71 * 1 - from inverted external RX clock
72 * rx | clk_sel: 0 - from external RX clock
73 * 1 - from inverted external RX clock
74 *
75 * RMII:
76 * tx | clk_sel: 0 - RMII clock
77 * 1 - Inverted RMII clock
78 * rx | clk_sel: 0 - RMII clock
79 * 1 - Inverted RMII clock
80 *
81 */
82 tx-clk-config = <0x0>;
83 rx-clk-config = <0x0>;
84 3v3-enable = <1>; /* IO voltage, 1 - 3.3v, 0 - 1.8v */
85
86 phy-handle = <&phy3>;
87
88 /* enable fix link for ethernet switch */
89 /*
90 fixed-link {
91 speed = <100>;
92 full-duplex;
93 phy-mode = "rmii";
94 };
95 */
96
97 mdio: mdio-bus {
98 #address-cells = <0x1>;
99 #size-cells = <0x0>;
100 /* YT8521 10M/100M/100OM 1.8V RGMII PHY */
101 phy0: phy@0 {
102 compatible = "ethernet-phy-ieee802.3-c22";
103 device_type = "ethernet-phy";
104 reg = <0x0>; /* set phy address*/
105 phy-mode = "rgmii";
106 };
107
108 /* YT8512B 10M/100M 3.3V RMII PHY */
109 phy3: phy@3 {
110 compatible = "ethernet-phy-ieee802.3-c22";
111 device_type = "ethernet-phy";
112 reg = <0x3>; /* set phy address*/
113 phy-mode = "rmii";
114 };
115
116 /* IP175D 10M/100M 3.3V RMII SWITCH */
117 phy1: phy@1 {
118 compatible = "ethernet-phy-ieee802.3-c22";
119 device_type = "ethernet-phy";
120 reg = <0x1>; /* set phy address*/
121 phy-mode = "rmii";
122 };
123 };
124 };
125 qspi: spi@0xd420b000 {
126 asr,qspi-freq = <78000000>;
127 status = "okay";
128 };
129 /* SD card */
130 sdh0: sdh@d4280000 {
131 pinctrl-names = "default", "slow", "fast";
132 pinctrl-0 = <&sdh0_pmx_func1 &sdh0_pmx_func2 &sdh0_pmx_func3>;
133 pinctrl-1 = <&sdh0_pmx_func1_slow &sdh0_pmx_func2_slow &sdh0_pmx_func3>;
134 pinctrl-2 = <&sdh0_pmx_func1_fast &sdh0_pmx_func2_fast &sdh0_pmx_func3>;
135 /*
136 * Genernal use, juse set vmmc-supply and vqmmc-supply
137 * vmmc-supply = <&supply1>
138 * vqmmc-supply = <&supply2>
139 *
140 * For compatibility, to select one from two supply source
141 * vmmc-supply = <&supply1 &supply1_backup>;
142 * vqmmc-supply = <&supply2 &supply2_backup>;
143 * vmmc2-supply = <&supply1_backup &supply1>;
144 * vqmmc2-supply = <&supply2_backup &supply2>;
145 */
146 vmmc-supply = <&pm802ldo4 &vcc_sdh1>;
147 vqmmc-supply = <&pm802ldo6 &pm803ldo8>;
148 vmmc2-supply = <&vcc_sdh1 &pm802ldo4>;
149 vqmmc2-supply = <&pm803ldo8 &pm802ldo6>;
150 bus-width = <4>;
151 no-mmc;
152 no-sdio;
153 non-removable;
154 broken-cd;
155 wp-inverted;
156 asr,sdh-pm-runtime-en;
157 asr,sdh-host-caps-disable = <(MMC_CAP_UHS_SDR104)>;
158 asr,sdh-quirks = <(
159 SDHCI_QUIRK_BROKEN_CARD_DETECTION |
160 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
161 )>;
162 asr,sdh-quirks2 = <(
163 SDHCI_QUIRK2_SET_AIB_MMC |
164 SDHCI_QUIRK2_PRESET_VALUE_BROKEN
165 )>;
166 /* prop "sdh-dtr-data":
167 <timing preset_rate src_rate tx_delay rx_delay tx_dline_reg rx_dline_reg> */
168 asr,sdh-dtr-data =
169 <PXA_MMC_TIMING_LEGACY PXA_SDH_DTR_26M PXA_SDH_DTR_104M 0 0 0 0>,
170 <PXA_MMC_TIMING_SD_HS PXA_SDH_DTR_52M PXA_SDH_DTR_104M 0 0 0 0>,
171 <PXA_MMC_TIMING_UHS_DDR50 PXA_SDH_DTR_52M PXA_SDH_DTR_104M 0 0 0 3>,
172 <PXA_MMC_TIMING_UHS_SDR50 PXA_SDH_DTR_104M PXA_SDH_DTR_208M 0 0 0 0>,
173 <PXA_MMC_TIMING_UHS_SDR104 PXA_SDH_DTR_208M PXA_SDH_DTR_208M 0 0 0 0>,
174 <PXA_MMC_TIMING_MAX PXA_SDH_DTR_PS_NONE PXA_SDH_DTR_104M 0 0 0 0>;
175 status = "okay";
176 };
177
178 /* SDIO */
179 sdh1: sdh@d4280800 {
180 pinctrl-names = "default", "fast", "sleep";
181 pinctrl-0 = <&sdh1_pmx_func1 &sdh1_pmx_func2 &sdh1_pmx_func3>;
182 pinctrl-1 = <&sdh1_pmx_func1_fast &sdh1_pmx_func2_fast &sdh1_pmx_func3>;
183 pinctrl-2 = <&sdh1_pmx_edge_wakeup>;
184 bus-width = <4>;
185 no-mmc;
186 no-sd;
187 non-removable;
188 keep-power-in-suspend;
189 /* enable-sdio-wakeup; */
190 /* clk-scaling-config:
191 <up_threshold down_threshold polling_interval> */
192 clk-scaling-config = <35 12 200>;
193 min-ddr-qos = <156000 312000 400000>;
194 asr,sdh-pm-runtime-en;
195 asr,sdh-quirks = <(
196 SDHCI_QUIRK_BROKEN_CARD_DETECTION |
197 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
198 )>;
199 asr,sdh-quirks2 = <(
200 SDHCI_QUIRK2_NO_TIMER_RETUNING |
201 SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
202 SDHCI_QUIRK2_BASE_CLOCK_ALWAYS_ON |
203 SDHCI_QUIRK2_TX_INT_CLOCK |
204 SDHCI_QUIRK2_CHANGE_SDIO_CLOCK_FREQ_DYNAMIC
205 )>;
206 asr,sdh-pm-caps = <(MMC_PM_KEEP_POWER)>;
207 asr,sdh-host-caps2 = <(
208 MMC_CAP2_ONLY_1_8V |
209 MMC_CAP2_DISABLE_PROBE_CDSCAN |
210 MMC_CAP2_NO_CMD_BEFORE_CMD5 |
211 MMC_CAP2_SDIO_CLK_52M_ONLY_DNLD_FW
212 )>;
213 /* prop "sdh-dtr-data":
214 <timing preset_rate src_rate tx_delay rx_delay tx_dline_reg rx_dline_reg> */
215 asr,sdh-dtr-data =
216 <PXA_MMC_TIMING_LEGACY PXA_SDH_DTR_26M PXA_SDH_DTR_104M 0 0 0 0>,
217 <PXA_MMC_TIMING_SD_HS PXA_SDH_DTR_45M PXA_SDH_DTR_89M 0 0 0 0>,
218 <PXA_MMC_TIMING_UHS_DDR50 PXA_SDH_DTR_52M PXA_SDH_DTR_104M 0 0 0 3>,
219 <PXA_MMC_TIMING_UHS_SDR50 PXA_SDH_DTR_104M PXA_SDH_DTR_208M 0 0 0 3>,
220 <PXA_MMC_TIMING_UHS_SDR104 PXA_SDH_DTR_208M PXA_SDH_DTR_208M 0 0 0 0>,
221 <PXA_MMC_TIMING_MAX PXA_SDH_DTR_PS_NONE PXA_SDH_DTR_89M 0 0 0 0>;
222 status = "okay";
223 };
224 pcie0: pcie@0xd4288000{
225 reset-gpios = <&gpio 54 0 >;
226 status = "okay";
227 };
228 pciephy0: pcie-phy@d4206000 {
229 status = "okay";
230 };
231 };
232
233 apb@d4000000 {
234 ssp_dai1: pxa-ssp-dai@1 {
235 compatible = "asr,pxa-ssp-dai";
236 reg = <0x1 0x0>;
237 dma-names = "rx", "tx";
238 platform_driver_name = "tdma_platform";
239 burst_size = <4>;
240 playback_period_bytes = <2048>;
241 playback_buffer_bytes = <4096>;
242 capture_period_bytes = <2048>;
243 capture_buffer_bytes = <4096>;
244 };
245 mfpr: mfpr@d401e000 {
246 status = "okay";
247 };
248 timer0: timer@d4014000 {
249 status = "okay";
250 };
251 uart1: uart@d4017000 { /* nezhas evb use ap uart */
252 pinctrl-names = "default","sleep";
253 pinctrl-0 = <&uart1_pmx_func1 &uart1_pmx_func2>;
254 pinctrl-1 = <&uart1_pmx_func1_sleep &uart1_pmx_func2>;
255 edge-wakeup-gpio = <&gpio 29 0>; /* GPIO29: AP UART rx pin */
256 status = "okay";
257 };
258 uart2: uart@d4036000 {
259 pinctrl-names = "default";
260 pinctrl-0 = <&gps_pmx_uart_rxd &gps_pmx_uart_txd>;
261 status = "okay";
262 };
263 rtc: rtc@d4010000 {
264 status = "okay";
265 };
266 pmx: pinmux@d401e000 {
267 /* pin base = base_addr / 4, nr pins & gpio function */
268 pinctrl-single,gpio-range = <
269 /*
270 * GPIO number is hardcoded for range at here.
271 * In gpio chip, GPIO number is not hardcoded for range.
272 * Since one gpio pin may be routed to multiple pins,
273 * define these gpio range in pxa910-dkb.dts not pxa910.dtsi.
274 */
275 /*&range 80 4 0 */ /* GPIO25 ~ GPIO28 */
276 &range 55 32 0 /* GPIO0 ~ GPIO31 */
277 &range 87 32 0 /* GPIO32 ~ GPIO63 */
278 &range 119 32 0 /* GPIO64 ~ GPIO95 */
279 &range 151 32 0 /* GPIO96 ~ GPIO127 */
280 >;
281
282 ssp0_pmx_func: ssp0_pmx_func {
283 pinctrl-single,pins = <
284 GPIO36 AF1 /* TXD */
285 GPIO35 AF1 /* RXD */
286 GPIO34 AF1 /* FRM */
287 /*GPIO34 AF0*/ /* FRM *//* DXS101 Use the config of Cs-gpios */
288 GPIO33 AF1 /* SCLK */
289 >;
290 DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL;
291 };
292 lcd_bl_func: lcd_bl_func {
293 pinctrl-single,pins = <
294 VCXO_OUT AF1 /* GPIO126, lcd bl */
295 GPIO24 AF0 /* reset */
296 GPIO22 AF0 /* lcd d/c */
297 >;
298 MFP_DEFAULT;
299 };
300 uart1_pmx_func1: uart1_pmx_func1 {
301 pinctrl-single,pins = <
302 GPIO29 AF1
303 >;
304 MFP_DEFAULT;
305 };
306 uart1_pmx_func2: uart1_pmx_func2 {
307 pinctrl-single,pins = <
308 GPIO30 AF1
309 >;
310 MFP_DEFAULT;
311 };
312 uart1_pmx_func1_sleep: uart1_pmx_func1_sleep {
313 pinctrl-single,pins = <
314 GPIO29 AF1
315 >;
316 DS_MEDIUM;PULL_NONE;EDGE_BOTH;SL_NORMAL;
317 };
318 twsi0_pmx_func: twsi0_pmx_func {
319 pinctrl-single,pins = <
320 GPIO49 AF1
321 GPIO50 AF1
322 >;
323 MFP_LPM_FLOAT;
324 };
325 twsi0_pmx_gpio: twsi0_pmx_gpio {
326 pinctrl-single,pins = <
327 GPIO49 AF0
328 GPIO50 AF0
329 >;
330 MFP_LPM_FLOAT;
331 };
332 twsi1_pmx_func: twsi1_pmx_func {
333 pinctrl-single,pins = <
334 GPIO10 AF1
335 GPIO11 AF1
336 >;
337 MFP_LPM_FLOAT;
338 };
339 twsi1_pmx_gpio: twsi1_pmx_gpio {
340 pinctrl-single,pins = <
341 GPIO10 AF0
342 GPIO11 AF0
343 >;
344 MFP_LPM_FLOAT;
345 };
346 /* no pull, no LPM */
347 dvc_pmx_func: dvc_pmx_func {
348 /* hw-dvc */
349 pinctrl-single,pins = <
350 TDS_DIO0 AF0
351 TDS_DIO1 AF0
352 >;
353 DS_MEDIUM;PULL_FLOAT;EDGE_NONE;SL_NORMAL;
354 };
355 leds_pmx_func: leds_pmx_func {
356 pinctrl-single,pins = <
357 DF_IO10 AF1
358 DF_IO11 AF1
359 DF_IO12 AF1
360 >;
361 DS_MEDIUM;PULL_FLOAT;EDGE_NONE;SL_NORMAL;
362 };
363
364 gps_pmx_onoff: gps_pmx_onoff {
365 pinctrl-single,pins = <
366 TDS_TXREV AF1
367 >;
368 DS_MEDIUM;PULL_DOWN;EDGE_NONE;SL_NORMAL;
369 };
370 gps_pmx_reset: gps_pmx_reset {
371 pinctrl-single,pins = <
372 TDS_RXON AF1
373 >;
374 DS_MEDIUM;PULL_DOWN;EDGE_NONE;SL_NORMAL;
375 };
376 gps_pmx_uart_rxd: gps_pmx_uart_rxd {
377 /* gps dedicated uart */
378 pinctrl-single,pins = <
379 GPIO51 AF1
380 GPIO32 AF1
381 >;
382 MFP_DEFAULT;
383 };
384 gps_pmx_uart_txd: gps_pmx_uart_txd {
385 /* gps dedicated uart */
386 pinctrl-single,pins = <
387 GPIO52 AF1
388 GPIO31 AF1
389 >;
390 MFP_DEFAULT;
391 };
392
393 panel_rst_func: panel_rst_func {
394 pinctrl-single,pins = <
395 DF_nCS1 AF1
396 >;
397 DS_MEDIUM;PULL_FLOAT;EDGE_NONE;SL_NORMAL;
398 };
399
400 sd_ldo_en: sd_ldo_en {
401 pinctrl-single,pins = <
402 GPIO12 AF0
403 >;
404 MFP_PULL_DOWN;
405 };
406 sdh0_pmx_func1: sdh0_pmx_func1 {
407 pinctrl-single,pins = <
408 MMC1_DAT3 AF0
409 MMC1_DAT2 AF0
410 MMC1_DAT1 AF0
411 MMC1_DAT0 AF0
412 MMC1_CMD AF0
413 >;
414 DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL;
415 };
416 sdh0_pmx_func2: sdh0_pmx_func2 {
417 pinctrl-single,pins = <
418 MMC1_CLK AF0
419 >;
420 DS_MEDIUM;PULL_NONE;EDGE_NONE;
421 };
422 sdh0_pmx_func3: sdh0_pmx_func3 {
423 pinctrl-single,pins = <
424 MMC1_CD AF0
425 >;
426 MFP_PULL_UP;
427 };
428 sdh0_pmx_func1_slow: sdh0_pmx_func1_slow {
429 pinctrl-single,pins = <
430 MMC1_DAT3 AF0
431 MMC1_DAT2 AF0
432 MMC1_DAT1 AF0
433 MMC1_DAT0 AF0
434 MMC1_CMD AF0
435 >;
436 DS_FAST0;PULL_NONE;EDGE_NONE;SL_NORMAL;
437 };
438 sdh0_pmx_func2_slow: sdh0_pmx_func2_slow {
439 pinctrl-single,pins = <
440 MMC1_CLK AF0
441 >;
442 DS_FAST0;PULL_NONE;EDGE_NONE;
443 };
444 sdh0_pmx_func1_fast: sdh0_pmx_func1_fast {
445 pinctrl-single,pins = <
446 MMC1_DAT3 AF0
447 MMC1_DAT2 AF0
448 MMC1_DAT1 AF0
449 MMC1_DAT0 AF0
450 MMC1_CMD AF0
451 >;
452 DS_FAST1;PULL_NONE;EDGE_NONE;SL_NORMAL;
453 };
454 sdh0_pmx_func2_fast: sdh0_pmx_func2_fast {
455 pinctrl-single,pins = <
456 MMC1_CLK AF0
457 >;
458 DS_FAST1;PULL_NONE;EDGE_NONE;
459 };
460 sdh1_pmx_func1_fast: sdh1_pmx_func1_fast {
461 pinctrl-single,pins = <
462 TDS_DIO13 AF0 /* WLAN_DAT3 */
463 TDS_DIO14 AF0 /* WLAN_DAT2 */
464 TDS_DIO15 AF0 /* WLAN_DAT1 */
465 TDS_DIO16 AF0 /* WLAN_DAT0 */
466 TDS_DIO17 AF0 /* WLAN_CMD */
467 >;
468 DS_FAST0;PULL_NONE;EDGE_NONE;SL_NORMAL;
469 };
470 sdh1_pmx_func2_fast: sdh1_pmx_func2_fast {
471 pinctrl-single,pins = <
472 TDS_DIO18 AF0 /* WLAN_CLK */
473 >;
474 DS_FAST0;PULL_DOWN;EDGE_NONE;SL_NORMAL;
475 };
476 sdh1_pmx_func1: sdh1_pmx_func1 {
477 pinctrl-single,pins = <
478 TDS_DIO13 AF0 /* WLAN_DAT3 */
479 TDS_DIO14 AF0 /* WLAN_DAT2 */
480 TDS_DIO15 AF0 /* WLAN_DAT1 */
481 TDS_DIO16 AF0 /* WLAN_DAT0 */
482 TDS_DIO17 AF0 /* WLAN_CMD */
483 >;
484 DS_FAST0;PULL_NONE;EDGE_NONE;SL_NORMAL;
485 };
486 sdh1_pmx_func2: sdh1_pmx_func2 {
487 pinctrl-single,pins = <
488 TDS_DIO18 AF0 /* WLAN_CLK */
489 >;
490 DS_MEDIUM;PULL_DOWN;EDGE_NONE;
491 };
492 sdh1_pmx_func3: sdh1_pmx_func3 {
493 pinctrl-single,pins = <
494 GPIO10 AF0 /* VCXO_REQ AF1 WLAN_WAKE_HOST */
495 >;
496 MFP_PULL_DOWN;
497 };
498 sdh1_pmx_edge_wakeup: sdh1_pmx_edge_wakeup {
499 pinctrl-single,pins = <
500 GPIO10 AF0 /* WLAN_WAKEUP_HOST */
501 >;
502 DS_MEDIUM;PULL_DOWN;EDGE_RISE;SL_NORMAL;
503 };
504 sdh1_pmx_pd_rst_off: sdh1_pmx_pd_rst_off {
505 pinctrl-single,pins = <
506 GPIO11 AF0 /* WLAN_PDn */
507 GPIO13 AF0 /* HOST_WAKEUP_WLAN */
508 GPIO14 AF0 /* HOST RESET WLAN */
509 >;
510 MFP_PULL_DOWN;
511 };
512 sdh1_pmx_pd_rst_on: sdh1_pmx_pd_rst_on {
513 pinctrl-single,pins = <
514 GPIO11 AF0 /* WLAN_PDn */
515 GPIO13 AF0 /* HOST_WAKEUP_WLAN */
516 GPIO14 AF0 /* HOST RESET WLAN */
517 >;
518 MFP_PULL_UP;
519 };
520 rfkill_32k_clk: rfkill_32k_clk {
521 pinctrl-single,pins = <
522 VBUS_DRV AF2 /*GPIO[122] */
523 >;
524 DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_LOW;
525 };
526 eta6005_charger_en: eta6005_charger_en {
527 pinctrl-single,pins = <
528 GPIO08 AF0
529 >;
530 MFP_PULL_UP;
531 };
532 eta6005_charger_stat: eta6005_charger_stat {
533 pinctrl-single,pins = <
534 GPIO04 AF0
535 >;
536 MFP_DEFAULT;
537 };
538
539 alc5616_pmx_func1: alc5616_pmx_func1 {
540 pinctrl-single,pins = <
541 GPIO08 AF0 /* AP_UART1_DCD_N -> CODEC_IRQ */
542 >;
543 MFP_DEFAULT;
544 };
545 alc5616_pmx_func2: alc5616_pmx_func2 {
546 pinctrl-single,pins = <
547 GPIO08 AF0 /* AP_UART1_DCD_N -> CODEC_IRQ */
548 >;
549 MFP_DEFAULT;
550 };
551 audio_regs_pmx_func1: audio_regs_pmx_func1 {
552 pinctrl-single,pins = <
553 GPIO20 AF7 /* I2S_SYSCLK */
554 >;
555 MFP_DEFAULT;
556 };
557 audio_regs_pmx_func2: audio_regs_pmx_func2 {
558 pinctrl-single,pins = <
559 GPIO20 AF7 /* I2S_SYSCLK */
560 >;
561 MFP_DEFAULT;
562 };
563
564 audio_pa_pmx_func: audio_pa_pmx_func {
565 pinctrl-single,pins = <
566 GPIO12 AF0 /* PA */
567 >;
568 MFP_DEFAULT;
569 };
570
571 slic_pmx_func1: slic_pmx_func1 {
572 pinctrl-single,pins = <
573 GPIO20 AF0 /* SLIC_INT, GPIO20 */
574 VCXO_OUT AF1 /* GPIO126, SLIC_3V3LDO_EN/LCD_BK_EN */
575 >;
576 MFP_DEFAULT;
577 };
578 slic_pmx_func2: slic_pmx_func2 {
579 pinctrl-single,pins = <
580 GPIO21 AF0 /* SLIC_RESET, GPIO21 */
581 >;
582 MFP_DEFAULT;
583 };
584 slic_pmx_func1_sleep: slic_pmx_func1_sleep {
585 pinctrl-single,pins = <
586 GPIO20 AF0 /* SLIC_INT, GPIO20 */
587 >;
588 DS_MEDIUM;PULL_UP;EDGE_BOTH;SL_NORMAL;
589 };
590
591 otg_vbus_func: otg_vbus_func {
592 pinctrl-single,pins = <
593 VBUS_DRV AF1 /* GPIO[122] */
594 >;
595 DS_MEDIUM;PULL_DOWN;EDGE_NONE;
596 };
597
598 emac_pmx_func0: emac_pmx_func0 {
599 pinctrl-single,pins = <
600 GPIO00 AF1 /* GMAC1_RX_DV */
601 GPIO01 AF1 /* GMAC1_RX_D0 */
602 GPIO02 AF1 /* GMAC1_RX_D1 */
603 GPIO03 AF1 /* GMAC1_RX_CLK */
604 /* GPIO04 AF1 GMAC1_RX_D2 */
605 /* GPIO05 AF1 GMAC1_RX_D3 */
606 GPIO06 AF1 /* GMAC1_TX_D0 */
607 GPIO07 AF1 /* GMAC1_TX_D1 */
608 /* GPIO12 AF1 GMAC1_TX_CLK */
609 /* GPIO13 AF1 GMAC1_TX_D2 */
610 /* GPIO14 AF1 GMAC1_TX_D3 */
611 GPIO15 AF1 /* GMAC1_TX_EN */
612 GPIO16 AF1 /* GMAC1_TX_MDC */
613 /* GPIO17 AF1 GMAC1_TX_MDIO */
614 >;
615 DS_MEDIUM;PULL_DOWN;EDGE_NONE;SL_NORMAL;
616 };
617 emac_pmx_func1: emac_pmx_func1 {
618 pinctrl-single,pins = <
619 GPIO04 AF1 /* GMAC1_RX_D2 */
620 GPIO05 AF1 /* GMAC1_RX_D3 */
621 GPIO12 AF1 /* GMAC1_TX_CLK */
622 GPIO13 AF1 /* GMAC1_TX_D2 */
623 GPIO14 AF1 /* GMAC1_TX_D3 */
624 >;
625 DS_MEDIUM;PULL_DOWN;EDGE_NONE;SL_NORMAL;
626 };
627 emac_pmx_func2: emac_pmx_func2 {
628 pinctrl-single,pins = <
629 GPIO17 AF1 /* GMAC1_TX_MDIO */
630 GPIO18 AF1 /* GMAC1_TX_INT_N */
631 >;
632 DS_MEDIUM;PULL_UP;EDGE_NONE;SL_NORMAL;
633 };
634 emac_pmx_func3: emac_pmx_func3 {
635 pinctrl-single,pins = <
636 GPIO23 AF0 /* RESET */
637 /* GPIO54 AF0 LDO_EN */
638 >;
639 DS_SLOW0;PULL_FLOAT;EDGE_NONE;SL_NORMAL;
640 };
641 usim1_pmx_func: usim1_pmx_func {
642 pinctrl-single,pins = <
643 GPIO19 AF0
644 >;
645 DS_MEDIUM;PULL_UP;EDGE_NONE;SL_NORMAL;
646 };
647 usim1_pmx_func_sleep: usim1_pmx_func_sleep {
648 pinctrl-single,pins = <
649 GPIO19 AF0
650 >;
651 DS_MEDIUM;PULL_UP;EDGE_BOTH;SL_NORMAL;
652 };
653 pcie_pmx_pd_rst_off: pcie_pmx_pd_rst_off {
654 pinctrl-single,pins = <
655 GPIO54 AF0 /* PERST_N */
656 GPIO123 AF1 /* DC_EN */
657 >;
658 MFP_PULL_DOWN;
659 };
660 pcie_pmx_pd_rst_on: pcie_pmx_pd_rst_on {
661 pinctrl-single,pins = <
662 GPIO54 AF0 /* PERST_N */
663 GPIO123 AF1 /* DC_EN */
664 >;
665 MFP_PULL_UP;
666 };
667 gpiokey_pmx_func: gpiokey_pmx_func {
668 pinctrl-single,pins = <
669 GPIO09 AF0
670 >;
671 DS_MEDIUM;PULL_UP;EDGE_NONE;SL_NORMAL;
672 };
673 };
674
675 ssp0: spi@d401b000 {
676 status = "okay";
677 pinctrl-names = "default";
678 pinctrl-0 = <&ssp0_pmx_func>;
679 asr,spi-inc-mode;
680 /*cs-gpios = <&gpio 34 0>;*//* DXS101 Use the config of Cs-gpios */
681#ifdef CONFIG_FB_SPI_LCD
682 /* this enhancemnet feature is not suitable for
683 3 line 9bits spi lcd. */
684 /* asr,ssp-enhancement; */
685
686 lcd: spidev@0 {
687 #address-cells = <1>;
688 #size-cells = <1>;
689 compatible = "spilcd";
690 pinctrl-names = "default";
691 pinctrl-0 = <&lcd_bl_func>;
692 reg = <0>;
693 /* ST7735: need to set spi-max-frequency to 26M
694 * ST7789V: can set spi-max-frequency to 52M
695 */
696 spi-max-frequency = <26000000>;
697 xres = <128>;
698 yres = <128>;
699 bits = <8>; /* 8: 4line, 9: 3line */
700 rst_gpio = <&gpio 24 0>;
701 bl_gpio = <&gpio 126 0>;
702 rs_gpio = <&gpio 22 0>;
703 /* if comment the following statement, it means
704 * the avdd is sit on the "always-on" ldo.
705 */
706 /* avdd-supply = <&LDO1>; */
707 };
708#else
709 slic: spidev@0{
710 #address-cells = <1>;
711 #size-cells = <1>;
712 compatible = "asr,slic";
713 reg = <0>;
714 spi-cpol;
715 spi-cpha;
716 spi-max-frequency = <6500000>;
717 };
718#endif
719 };
720 twsi0: i2c@d4011000 {
721 status= "okay";
722 alc5616@1b {
723 compatible = "asrmicro,alc5616";
724 reg = <0x1b>;
725 pinctrl-names = "default", "sleep";
726 pinctrl-0 = <&alc5616_pmx_func1>;
727 pinctrl-1 = <&alc5616_pmx_func2>;
728 clocks = <&soc_clocks ASR1803_CLK_I2S_SYSCLK>;
729 clock-names = "i2s_sys_clk";
730#if 0
731 3V3-gpio = <&gpio 23 0>;/* CODEC_LDO_EN */
732 irq-gpio = <&gpio 24 0>;/* CODEC_IRQ for headset detection */
733#else
734 irq-gpio = <&gpio 8 0>;/* CODEC_IRQ for headset detection */
735#endif
736 };
737
738 /*
739 pmic4: 88pm805@38 {
740 compatible = "marvell,88pm805";
741 reg = <0x38>;
742 };
743 */
744 };
745 twsi1: i2c@d4010800 {
746 status= "disabled";
747 nau8810@1a {
748 compatible = "marvell,nau8810";
749 reg = <0x1a>;
750 };
751 };
752 twsi2: i2c@d4037000 {
753 status = "okay";
754
755 pmic4: 88pm805@38 {
756 compatible = "marvell,88pm805";
757 reg = <0x38>;
758 };
759
760 pmic5: pm802@0 {
761 compatible = "asr,pm802";
762 reg = <0x00>;
763 interrupts = <4>;
764 interrupt-parent = <&intc>;
765 interrupt-controller;
766 #interrupt-cells = <1>;
767 chg_irq_from_exton;
768 battery {
769 compatible = "asr,pm802-bat";
770 status = "disabled";
771
772 online-gpadc = <1>;
773 temperature-gpadc = <1>;
774
775 hi-volt-online = <1150>; /* mV */
776 lo-volt-online = <20>; /* mV */
777 hi-volt-temp = <1150>; /* mV */
778 lo-volt-temp = <200>; /* mV */
779
780 sw-fg-use-ntc;
781 full-capacity = <2050>; /* mAh */
782 r1-resistor = <40>; /* mohm */
783 r2-resistor = <30>; /* mohm */
784 rs-resistor = <120>; /* mohm */
785 roff-resistor = <0>; /* mohm */
786 roff-initial-resistor = <0>; /* mohm */
787
788 times-in-zero-degree = <1>;
789 offset-in-zero-degree = <0>;
790
791 times-in-ten-degree = <2>;
792 offset-in-ten-degree = <100>;
793
794 power-off-threshold = <3350>; /* mV */
795 safe-power-off-threshold = <3200>; /* mV */
796
797 online-gp-bias-curr = <11>; /* uA */
798
799 soc-ramp-up-interval = <150>; /* s */
800 /* choose -20C, 0C, 10C, 40C, 45C, 55C as threshold */
801 tbat-threshold = <20 0 10 40 45 55>; /* ohm */
802 ntc-table-size = <88>;
803 stop-chg-for-vbatmeas;
804 /* -24C, -23C, ..., 62C, 63C */
805 ntc-table = <
806 89680 85130 80840 76790 72970 69360 65960 62740
807 59700 56830 54130 51530 49100 46800 44610 42550
808 40590 38730 36970 35300 33710 32210 30780 29420
809 28130 26910 25750 24640 23590 22580 21630 20720
810 19860 19030 18250 17500 16790 16110 15460 14840
811 14250 13690 13150 12640 12150 11680 11230 10800
812 10390 10000 9620 9270 8920 8590 8280 7980
813 7690 7410 7150 6890 6650 6410 6190 5970
814 5770 5570 5380 5190 5020 4850 4680 4530
815 4380 4230 4100 3960 3830 3710 3590 3480
816 3370 3260 3160 3060 2960 2870 2780 2700
817 >;
818 };
819 usb {
820 status = "disabled";
821 vbus_gpio = <0xff>; /* set_vbus */
822 id-gpadc = <0xff>; /* usb-id */
823 vchg-from-exton = <1>;
824 vbus-detect = <1>; /* vbus-irq */
825 get-vbus = <1>; /* get-vbus */
826 };
827 };
828 pmic6: pm803@30 {
829 compatible = "asr,pm803";
830 reg = <0x30>;
831 interrupts = <4>;
832 interrupt-parent = <&intc>;
833 interrupt-controller;
834 #interrupt-cells = <1>;
835 chg_irq_from_exton;
836 battery {
837 compatible = "asr,pm803-bat";
838 status = "disabled";
839
840 online-gpadc = <1>;
841 temperature-gpadc = <1>;
842
843 hi-volt-online = <1150>; /* mV */
844 lo-volt-online = <20>; /* mV */
845 hi-volt-temp = <1150>; /* mV */
846 lo-volt-temp = <200>; /* mV */
847
848 sw-fg-use-ntc;
849 full-capacity = <2050>; /* mAh */
850 r1-resistor = <40>; /* mohm */
851 r2-resistor = <30>; /* mohm */
852 rs-resistor = <120>; /* mohm */
853 roff-resistor = <0>; /* mohm */
854 roff-initial-resistor = <0>; /* mohm */
855
856 times-in-zero-degree = <1>;
857 offset-in-zero-degree = <0>;
858
859 times-in-ten-degree = <2>;
860 offset-in-ten-degree = <100>;
861
862 power-off-threshold = <3350>; /* mV */
863 safe-power-off-threshold = <3200>; /* mV */
864
865 online-gp-bias-curr = <11>; /* uA */
866
867 soc-ramp-up-interval = <150>; /* s */
868 /* choose -20C, 0C, 10C, 40C, 45C, 55C as threshold */
869 tbat-threshold = <20 0 10 40 45 55>; /* ohm */
870 ntc-table-size = <88>;
871 stop-chg-for-vbatmeas;
872 /* -24C, -23C, ..., 62C, 63C */
873 ntc-table = <
874 89680 85130 80840 76790 72970 69360 65960 62740
875 59700 56830 54130 51530 49100 46800 44610 42550
876 40590 38730 36970 35300 33710 32210 30780 29420
877 28130 26910 25750 24640 23590 22580 21630 20720
878 19860 19030 18250 17500 16790 16110 15460 14840
879 14250 13690 13150 12640 12150 11680 11230 10800
880 10390 10000 9620 9270 8920 8590 8280 7980
881 7690 7410 7150 6890 6650 6410 6190 5970
882 5770 5570 5380 5190 5020 4850 4680 4530
883 4380 4230 4100 3960 3830 3710 3590 3480
884 3370 3260 3160 3060 2960 2870 2780 2700
885 >;
886 };
887 usb {
888 status = "disabled";
889 vbus_gpio = <0xff>; /* set_vbus */
890 id-gpadc = <0xff>; /* usb-id */
891 vchg-from-exton = <1>;
892 vbus-detect = <1>; /* vbus-irq */
893 get-vbus = <1>; /* get-vbus */
894 };
895 };
896 };
897 };
898 };
899
900 vcc_sdh1: sd-regulator {
901 compatible = "regulator-fixed";
902 pinctrl-names = "default";
903 pinctrl-0 = <&sd_ldo_en>;/*conflict with audio-pa*/
904 regulator-name = "SDH1 VCC";
905 regulator-min-microvolt = <3300000>;
906 regulator-max-microvolt = <3300000>;
907 gpio = <&gpio 12 0>;/*conflict with audio-pa*/
908 enable-active-high;
909 };
910
911 asr-rfkill {
912 compatible = "asr,asr-rfkill";
913 clocks = <&soc_clocks ASR1803_CLK_VCTCXO_REQ>;
914 clock-names = "wifi_26m";
915 pinctrl-names = "default", "off", "on";
916 pinctrl-0 = <&rfkill_32k_clk>;
917 pinctrl-1 = <&sdh1_pmx_pd_rst_off>;
918 pinctrl-2 = <&sdh1_pmx_pd_rst_on>;
919 sd-host = <&sdh1>;
920 pd-gpio = <&gpio 11 0>;
921 host-wakeup-wlan-gpio = <&gpio 13 0>;
922 wlan-wakeup-host-gpio = <&gpio 10 0>;
923 rst-gpio = <&gpio 14 0>;
924 status = "okay";
925 };
926
927 pcie-rfkill {
928 compatible = "mrvl,pcie-rfkill";
929 pinctrl-names = "off", "on";
930 pinctrl-0 = <&pcie_pmx_pd_rst_off>;
931 pinctrl-1 = <&pcie_pmx_pd_rst_on>;
932 rst-gpio = <&gpio 54 0>;
933 3v3-ldo-gpio = <&gpio 123 0>;
934 status = "okay";
935 };
936
937 sound {
938 compatible = "ASRMICRO,asrmicro-snd-card";
939 ssp-controllers = <&ssp_dai1>;
940 };
941
942 usim1: usim {
943 compatible = "asr,usim1";
944 pinctrl-names = "default", "sleep";
945 pinctrl-0 = <&usim1_pmx_func>;
946 pinctrl-1 = <&usim1_pmx_func_sleep>;
947 edge_detect_gpio = <19>; /* GPIO19: SIM detect pin */
948 status = "okay";
949 };
950
951 gpio_keys {
952 compatible = "gpio-keys";
953 #address-cells = <1>;
954 #size-cells = <0>;
955 /* autorepeat; */
956 pinctrl-names = "default";
957 pinctrl-0 = <&gpiokey_pmx_func>;
958 button@1 {
959 label = "qrcode-key";
960 linux,code = <139>; /* KEY_MENU, refer to linux/input.h */
961 /* NOTE:
962 * We use the FORCE DOWNLOAD key to implement the qrcode key in DKB.
963 * Customer SHOULD change it to any other gpios.
964 * Because user may do the misoperation that
965 * powerup with FDL key pressed,
966 * then the borad will enter force download mode.
967 */
968 gpios = <&gpio 9 1>;
969 gpio-key,wakeup;
970 };
971 };
972
973 audio_pa {
974 compatible = "asrmicro,audio-pa";
975 pinctrl-names = "default";
976 pinctrl-0 = <&audio_pa_pmx_func>;
977 pa-gpio = <&gpio 12 0>;/* NOTES:need to disable the other device using GPIO12, such as SD */
978 status = "disabled";
979 };
980
981 audio_regs {
982 compatible = "ASRMICRO,audio-registers";
983 pinctrl-names = "default", "sleep";
984 pinctrl-0 = <&audio_regs_pmx_func1>;
985 pinctrl-1 = <&audio_regs_pmx_func2>;
986 reg = <0xD4050044 0x4>;
987 status = "okay";
988 };
989
990 nz3-slic {
991 compatible = "asr,nz3-slic";
992 pinctrl-names = "default", "sleep";
993 pinctrl-0 = <&slic_pmx_func1 &slic_pmx_func2>;
994 pinctrl-1 = <&slic_pmx_func1_sleep &slic_pmx_func2>;
995 rst-gpio = <&gpio 21 0>;
996 edge-wakeup-gpio = <&gpio 20 0>;
997 vdd-3v3-gpio = <&gpio 126 0>;
998 status = "disabled";
999 };
1000 microsemi-slic {
1001 compatible = "asr,microsemi-slic";
1002 pinctrl-names = "default", "sleep";
1003 pinctrl-0 = <&slic_pmx_func1>;
1004 pinctrl-1 = <&slic_pmx_func1_sleep>;
1005 edge-wakeup-gpio = <&gpio 20 0>;
1006 vdd-3v3-gpio = <&gpio 126 0>;
1007 status = "disabled";
1008 };
1009 maxlinear-slic {
1010 compatible = "asr,maxlinear-slic";
1011 pinctrl-names = "default", "sleep";
1012 pinctrl-0 = <&slic_pmx_func1 &slic_pmx_func2>;
1013 pinctrl-1 = <&slic_pmx_func1_sleep &slic_pmx_func2>;
1014 rst-gpio = <&gpio 21 0>;
1015 edge-wakeup-gpio = <&gpio 20 0>;
1016 vdd-3v3-gpio = <&gpio 126 0>;
1017 status = "disabled";
1018 };
1019};
1020#include "asr_pm802.dtsi"
1021#include "88pm805.dtsi"
1022#include "asr_pm803.dtsi"
1023
1024#ifdef CONFIG_AB_SYSTEM
1025#include "asr1803_ab_flash_layout.dtsi"
1026#else
1027#include "asr1803_flash_layout.dtsi"
1028#endif