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192.168.1.100 / T108 / c2023d5d03be91dbb983606f0ec5e9e4ea36c8c2 / . / marvell / linux / arch / arm / boot / dts / asr1806-p301-pose.dts
blob: 14972aa5126d088d2cf7bf94a0a7ec5afc8505f5 [file] [log] [blame]
b.liue9582032025-04-17 19:18:16 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2023 ASR Microelectronics Co., Ltd.
4 */
5
6/dts-v1/;
7#include "asr1806.dtsi"
8
9/* #define CONFIG_FB_ASR_MIPI_CMD 1 */
10
11/ {
12 model = "ASR 1806(FALCON-T) Board EVB";
13 compatible = "asr,1803-evb", "asr,1803";
14
15 chosen {
16 bootargs = "root=/dev/mtdblock5 rootfstype=squashfs init=/etc/preinit noinitrd console=ttyS0,115200 mem=128M";
17 };
18
19 memory {
20 reg = <0x00000000 0x10000000>;
21 };
22
23 firmware {
24 optee {
25 compatible = "linaro,optee-tz";
26 method = "smc";
27 };
28 };
29
30 soc {
31 axi@d4200000 { /* AXI */
32 lcd: lcd@d420a000 {
33 compatible = "asr,fb";
34 pinctrl-names = "default";
35 pinctrl-0 = <&lcd_pmx_func>;
36 interrupts = <51>;
37 lpm-qos = <PM_QOS_CPUIDLE_BLOCK_AXI>;
38 reg = <0xd420a000 0x800>;
39 dsi_base = <0xd420a800>;
40 #ifdef CONFIG_FB_ASR_MIPI_CMD
41 panel_type = <1>; /* cmd */
42 #else
43 panel_type = <0>; /* video */
44 #endif
45
46 gpio_ctrl = <1>;
47
48 #ifdef CONFIG_FB_ASR_MIPI_CMD
49 power_gpio = <&gpio 127 0>;
50 #endif
51 reset_gpio = <&gpio 31 0>;
52 vsync_gpio = <&gpio 32 0>;
53 //avdd-supply = <&ldo1>;
54 status = "okay";
55 };
56
57 backlight: pwm_bl {
58 compatible = "pwm-backlight";
59 pwms = <&pwm2 50000>;
60 brightness-levels = <0 4 8 16 32 64 128 255>;
61 default-brightness-level = <6>;
62 #ifdef CONFIG_FB_ASR_MIPI_CMD
63 status = "disabled";
64 #else
65 status = "okay";
66 #endif
67 };
68
69 usbphy: usbphy@d4207000 {
70 status = "okay";
71 };
72#ifdef CONFIG_USB_DWC2_ASR_OTG /* otg mode */
73 usb: usb@c0000000 {
74 dr_mode = "otg";
75 pinctrl-names = "default","sleep";
76 pinctrl-0 = <&usb_id_pinmux &usb_host_pinmux>;
77 pinctrl-1 = <&usb_id_pinmux_slp &usb_host_pinmux>;
78 usbid_gpio = <99>;
79 edge_detect_gpio = <99>;
80 otg,use-gpio-vbus;
81 gpio-num = <122>;
82 status = "okay";
83 };
84#else
85 usb: usb@c0000000 {
86 status = "okay";
87 };
88#endif
89 eth0: asr-eth@0xd4281800 {
90 compatible = "asr,asr-eth";
91 pinctrl-names = "default", "rgmii-pins";
92 pinctrl-0 = <&emac_pmx_func0 &emac_pmx_func2 &emac_pmx_func3>;
93 pinctrl-1 = <&emac_pmx_func0 &emac_pmx_func1 &emac_pmx_func2 &emac_pmx_func3>;
94 reg = <0xd4281800 0x200>;
95 interrupts = <10 11>;
96 lpm-qos = <PM_QOS_CPUIDLE_BLOCK_AXI>;
97 clocks = <&soc_clocks ASR1803_CLK_EMAC
98 &soc_clocks ASR1803_CLK_EMAC_PTP>;
99 clock-names = "emac-clk", "ptp-clk";
100 ptp-support;
101 ptp-clk-rate = <100000000>;
102 status = "okay";
103
104 reset-gpio = <&gpio 20 0>;
105 reset-active-low;
106 reset-delays-us = <0 100000 100000>;
107
108 ldo-gpio = <&gpio 118 0>;
109 ldo-active-low;
110 ldo-delays-us = <0 100000 100000>;
111
112 clk-tuning-enable;
113 /* clk-config(32bit)
114 *
115 * clk_sel(clk-config[23:16])
116 * RGMII:
117 * tx | clk_sel: 0 - from external RX clock
118 * 1 - from inverted external RX clock
119 * rx | clk_sel: 0 - from external RX clock
120 * 1 - from inverted external RX clock
121 *
122 * RMII:
123 * tx | clk_sel: 0 - RMII clock
124 * 1 - Inverted RMII clock
125 * rx | clk_sel: 0 - RMII clock
126 * 1 - Inverted RMII clock
127 *
128 */
129 tx-clk-config = <0x0>;
130 rx-clk-config = <0x0>;
131#if 0
132 /* enable 1000M phy*/
133 3v3-enable = <0>; /* IO voltage, 1 - 3.3v, 0 - 1.8v */
134 phy-handle = <&phy0>;
135#else
136 /* enable 100M phy*/
137 3v3-enable = <1>; /* IO voltage, 1 - 3.3v, 0 - 1.8v */
138 phy-handle = <&phy3>;
139#endif
140 /* enable fix link for ethernet switch */
141 /*
142 fixed-link {
143 speed = <100>;
144 full-duplex;
145 phy-mode = "rmii";
146 };
147 */
148
149 mdio: mdio-bus {
150 #address-cells = <0x1>;
151 #size-cells = <0x0>;
152 /* YT8521 10M/100M/100OM 1.8V RGMII PHY */
153 phy0: phy@0 {
154 compatible = "ethernet-phy-ieee802.3-c22";
155 device_type = "ethernet-phy";
156 reg = <0x0>; /* set phy address*/
157 phy-mode = "rgmii";
158 tx_rx_delay = <0xb 0x0>; /* 150ps per step*/
159 };
160
161 /* YT8512B 10M/100M 3.3V RMII PHY */
162 phy3: phy@3 {
163 compatible = "ethernet-phy-ieee802.3-c22";
164 device_type = "ethernet-phy";
165 reg = <0x3>; /* set phy address*/
166 phy-mode = "rmii";
167 driver_strength = <0x3>;
168 };
169
170 /* IP175D 10M/100M 3.3V RMII SWITCH */
171 phy1: phy@1 {
172 compatible = "ethernet-phy-ieee802.3-c22";
173 device_type = "ethernet-phy";
174 reg = <0x1>; /* set phy address*/
175 phy-mode = "rmii";
176 };
177 };
178 };
179 qspi: spi@0xd420b000 {
180 asr,qspi-freq = <78000000>;
181 status = "okay";
182 };
183 /* SD card */
184 sdh0: sdh@d4280000 {
185 pinctrl-names = "default", "slow", "fast";
186 pinctrl-0 = <&sdh0_pmx_func1 &sdh0_pmx_func2 &sdh0_pmx_func3>;
187 pinctrl-1 = <&sdh0_pmx_func1_slow &sdh0_pmx_func2_slow &sdh0_pmx_func3>;
188 pinctrl-2 = <&sdh0_pmx_func1_fast &sdh0_pmx_func2_fast &sdh0_pmx_func3>;
189 /*
190 * Genernal use, juse set vmmc-supply and vqmmc-supply
191 * vmmc-supply = <&supply1>
192 * vqmmc-supply = <&supply2>
193 *
194 * For compatibility, to select one from two supply source
195 * vmmc-supply = <&supply1 &supply1_backup>;
196 * vqmmc-supply = <&supply2 &supply2_backup>;
197 * vmmc2-supply = <&supply1_backup &supply1>;
198 * vqmmc2-supply = <&supply2_backup &supply2>;
199 */
200 vmmc-supply = <&vcc_sdh1>;
201 vqmmc-supply = <&pm802ldo6>;
202#ifndef CONFIG_ASR_DSDS
203 vmmc2-supply = <&vcc_sdh1 &pm802ldo4>;
204 vqmmc2-supply = <&pm803ldo8 &pm802ldo6>;
205#endif
206 bus-width = <4>;
207 no-mmc;
208 no-sdio;
209 non-removable;
210 broken-cd;
211 wp-inverted;
212 asr,sdh-pm-runtime-en;
213 asr,sdh-host-caps-disable = <(MMC_CAP_UHS_SDR104)>;
214 asr,sdh-quirks = <(
215 SDHCI_QUIRK_BROKEN_CARD_DETECTION |
216 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
217 )>;
218 asr,sdh-quirks2 = <(
219 SDHCI_QUIRK2_SET_AIB_MMC |
220 SDHCI_QUIRK2_PRESET_VALUE_BROKEN
221 )>;
222 /* prop "sdh-dtr-data":
223 <timing preset_rate src_rate tx_delay rx_delay tx_dline_reg rx_dline_reg> */
224 asr,sdh-dtr-data =
225 <PXA_MMC_TIMING_LEGACY PXA_SDH_DTR_26M PXA_SDH_DTR_104M 0 0 0 0>,
226 <PXA_MMC_TIMING_SD_HS PXA_SDH_DTR_52M PXA_SDH_DTR_104M 0 0 0 0>,
227 <PXA_MMC_TIMING_UHS_DDR50 PXA_SDH_DTR_52M PXA_SDH_DTR_104M 0 0 0 3>,
228 <PXA_MMC_TIMING_UHS_SDR50 PXA_SDH_DTR_104M PXA_SDH_DTR_208M 0 0 0 0>,
229 <PXA_MMC_TIMING_UHS_SDR104 PXA_SDH_DTR_208M PXA_SDH_DTR_208M 0 0 0 0>,
230 <PXA_MMC_TIMING_MAX PXA_SDH_DTR_PS_NONE PXA_SDH_DTR_104M 0 0 0 0>;
231 status = "okay";
232 };
233
234 /* SDIO */
235 sdh1: sdh@d4280800 {
236 pinctrl-names = "default", "fast", "sleep";
237 pinctrl-0 = <&sdh1_pmx_func1 &sdh1_pmx_func2 &sdh1_pmx_func3>;
238 pinctrl-1 = <&sdh1_pmx_func1_fast &sdh1_pmx_func2_fast &sdh1_pmx_func3>;
239 pinctrl-2 = <&sdh1_pmx_edge_wakeup>;
240 bus-width = <4>;
241 no-mmc;
242 no-sd;
243 non-removable;
244 keep-power-in-suspend;
245 enable-sdio-wakeup;
246 /* clk-scaling-config:
247 <up_threshold down_threshold polling_interval> */
248 clk-scaling-config = <25 12 200>;
249 min-ddr-qos = <156000 312000 400000>;
250 asr,sdh-pm-runtime-en;
251 asr,sdh-quirks = <(
252 SDHCI_QUIRK_BROKEN_CARD_DETECTION |
253 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
254 )>;
255 asr,sdh-quirks2 = <(
256 SDHCI_QUIRK2_NO_TIMER_RETUNING |
257 SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
258 SDHCI_QUIRK2_BASE_CLOCK_ALWAYS_ON
259 )>;
260 asr,sdh-pm-caps = <(MMC_PM_KEEP_POWER)>;
261 asr,sdh-host-caps2 = <(
262 MMC_CAP2_ONLY_1_8V |
263 MMC_CAP2_DISABLE_PROBE_CDSCAN |
264 MMC_CAP2_CLK_SCALE |
265 MMC_CAP2_BUS_CLK_NO_SCALE
266 )>;
267 /* prop "sdh-dtr-data":
268 <timing preset_rate src_rate tx_delay rx_delay tx_dline_reg rx_dline_reg> */
269 asr,sdh-dtr-data =
270 <PXA_MMC_TIMING_LEGACY PXA_SDH_DTR_26M PXA_SDH_DTR_104M 0 0 0 0>,
271 <PXA_MMC_TIMING_SD_HS PXA_SDH_DTR_45M PXA_SDH_DTR_89M 0 0 0 0>,
272 <PXA_MMC_TIMING_UHS_DDR50 PXA_SDH_DTR_52M PXA_SDH_DTR_104M 0 0 0 3>,
273 <PXA_MMC_TIMING_UHS_SDR50 PXA_SDH_DTR_83M PXA_SDH_DTR_83M 0 0 0 3>,
274 <PXA_MMC_TIMING_UHS_SDR104 PXA_SDH_DTR_208M PXA_SDH_DTR_208M 0 0 0 0>,
275 <PXA_MMC_TIMING_MAX PXA_SDH_DTR_PS_NONE PXA_SDH_DTR_89M 0 0 0 0>;
276 status = "okay";
277 };
278
279 pcie0: pcie@0xd4288000{
280 reset-gpios = <&gpio 42 0 >;
281 status = "okay";
282 };
283 pciephy0: pcie-phy@d4206000 {
284 status = "okay";
285 };
286 camera: camera@d420d000 {
287 compatible = "asr,camera";
288 reg = <0xd420d000 0x1000>, /* IPE registers */
289 <0xd420f000 0x1000>; /* ISP registers */
290 reg-names = "ipe", "isp";
291 interrupts = <64>;
292 pinctrl-names = "default";
293 pinctrl-0 = <&isp_spi_data>;
294 lpm-qos = <PM_QOS_CPUIDLE_BLOCK_AXI>;
295 clock-frequency = <24>;
296 clocks = <&soc_clocks ASR1803_CLK_CAMERA>;
297 clock-names = "cam_clk";
298 status = "okay";
299 port {
300 #address-cells = <1>;
301 #size-cells = <0>;
302 spi_in_cam: endpoint@0 {
303 reg = <0>;
304 remote-endpoint = <&gc0312_out>;
305 };
306 };
307 };
308 };
309
310 apb@d4000000 {
311 pwm2: pwm@d401a800 {
312 pinctrl-names = "default";
313 pinctrl-0 = <&pinctrl_pwm2>;
314 #ifdef CONFIG_FB_ASR_MIPI_CMD
315 status = "disabled";
316 #else
317 status = "okay";
318 #endif
319 };
320 mfpr: mfpr@d401e000 {
321 status = "okay";
322 };
323 timer0: timer@d4014000 {
324 status = "okay";
325 };
326 uart1: uart@d4017000 { /* nezhas evb use ap uart */
327 pinctrl-names = "default","sleep";
328 pinctrl-0 = <&uart1_pmx_func1 &uart1_pmx_func2>;
329 pinctrl-1 = <&uart1_pmx_func1_sleep &uart1_pmx_func2>;
330 edge-wakeup-gpio = <&gpio 29 0>; /* GPIO29: AP UART rx pin */
331 status = "okay";
332 };
333 uart2: uart@d4036000 {
334 pinctrl-names = "default";
335 pinctrl-0 = <&gps_pmx_uart_rxd &gps_pmx_uart_txd>;
336 status = "okay";
337 };
338 rtc: rtc@d4010000 {
339 status = "okay";
340 };
341 pmx: pinmux@d401e000 {
342 /* pin base = base_addr / 4, nr pins & gpio function */
343 pinctrl-single,gpio-range = <
344 /*
345 * GPIO number is hardcoded for range at here.
346 * In gpio chip, GPIO number is not hardcoded for range.
347 * Since one gpio pin may be routed to multiple pins,
348 * define these gpio range in pxa910-dkb.dts not pxa910.dtsi.
349 */
350 /*&range 80 4 0 */ /* GPIO25 ~ GPIO28 */
351 &range 55 32 0 /* GPIO0 ~ GPIO31 */
352 &range 87 32 0 /* GPIO32 ~ GPIO63 */
353 &range 119 32 0 /* GPIO64 ~ GPIO95 */
354 &range 151 32 0 /* GPIO96 ~ GPIO127 */
355 >;
356
357 lcd_pmx_func: lcd_pmx_func {
358 pinctrl-single,pins = <
359 /* mipi */
360 GPIO31 AF0 /* reset */
361 GPIO32 AF0 /* vsync */
362 #ifdef CONFIG_FB_ASR_MIPI_CMD
363 VCXO_OUT AF1
364 #endif
365 >;
366 /* NOTE: need to PULL_UP here */
367 DS_MEDIUM;PULL_UP;EDGE_NONE;LPM_NONE;
368 };
369
370 pinctrl_pwm2: pmw2grp {
371 pinctrl-single,pins = <
372 VCXO_OUT AF2 /* pwm2 */
373 >;
374 DS_MEDIUM;PULL_UP;EDGE_NONE;LPM_NONE;
375 };
376
377 tp_pinmux: tp_pinmux {
378 pinctrl-single,pins = <
379 GPIO54 AF0 /* TP_INT */
380 GPIO08 AF0 /* TP_RST */
381 >;
382 DS_MEDIUM;PULL_UP;EDGE_NONE;LPM_NONE;
383 };
384
385 ssp0_pmx_func: ssp0_pmx_func {
386 pinctrl-single,pins = <
387 GPIO36 AF1 /* TXD */
388 GPIO35 AF1 /* RXD */
389 GPIO34 AF1 /* FRM */
390 /*GPIO34 AF0*/ /* FRM *//* DXS101 Use the config of Cs-gpios */
391 GPIO33 AF1 /* SCLK */
392 >;
393 DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL;
394 };
395
396 uart1_pmx_func1: uart1_pmx_func1 {
397 pinctrl-single,pins = <
398 GPIO29 AF1
399 >;
400 MFP_DEFAULT;
401 };
402 uart1_pmx_func2: uart1_pmx_func2 {
403 pinctrl-single,pins = <
404 GPIO30 AF1
405 >;
406 MFP_DEFAULT;
407 };
408 uart1_pmx_func1_sleep: uart1_pmx_func1_sleep {
409 pinctrl-single,pins = <
410 GPIO29 AF1
411 >;
412 DS_MEDIUM;PULL_NONE;EDGE_BOTH;SL_NORMAL;
413 };
414 twsi0_pmx_func: twsi0_pmx_func {
415 pinctrl-single,pins = <
416 GPIO49 AF1
417 GPIO50 AF1
418 >;
419 MFP_LPM_FLOAT;
420 };
421 twsi0_pmx_gpio: twsi0_pmx_gpio {
422 pinctrl-single,pins = <
423 GPIO49 AF0
424 GPIO50 AF0
425 >;
426 MFP_LPM_FLOAT;
427 };
428 twsi1_pmx_func: twsi1_pmx_func {
429 pinctrl-single,pins = <
430 GPIO10 AF1
431 GPIO11 AF1
432 >;
433 MFP_LPM_FLOAT;
434 };
435 twsi1_pmx_gpio: twsi1_pmx_gpio {
436 pinctrl-single,pins = <
437 GPIO10 AF0
438 GPIO11 AF0
439 >;
440 MFP_LPM_FLOAT;
441 };
442 /* no pull, no LPM */
443 dvc_pmx_func: dvc_pmx_func {
444 /* hw-dvc */
445 pinctrl-single,pins = <
446 TDS_DIO0 AF0
447 TDS_DIO1 AF0
448 >;
449 DS_MEDIUM;PULL_FLOAT;EDGE_NONE;SL_NORMAL;
450 };
451 leds_pmx_func: leds_pmx_func {
452 pinctrl-single,pins = <
453 DF_IO10 AF1
454 DF_IO11 AF1
455 DF_IO12 AF1
456 >;
457 DS_MEDIUM;PULL_FLOAT;EDGE_NONE;SL_NORMAL;
458 };
459
460 gps_pmx_onoff: gps_pmx_onoff {
461 pinctrl-single,pins = <
462 TDS_TXREV AF1
463 >;
464 DS_MEDIUM;PULL_DOWN;EDGE_NONE;SL_NORMAL;
465 };
466 gps_pmx_reset: gps_pmx_reset {
467 pinctrl-single,pins = <
468 TDS_RXON AF1
469 >;
470 DS_MEDIUM;PULL_DOWN;EDGE_NONE;SL_NORMAL;
471 };
472 gps_pmx_uart_rxd: gps_pmx_uart_rxd {
473 /* gps dedicated uart */
474 pinctrl-single,pins = <
475 GPIO51 AF1
476 /* conflict with mipi */
477 /* GPIO32 AF1 */
478 >;
479 MFP_DEFAULT;
480 };
481 gps_pmx_uart_txd: gps_pmx_uart_txd {
482 /* gps dedicated uart */
483 pinctrl-single,pins = <
484 GPIO52 AF1
485 /* conflict with mipi */
486 /* GPIO31 AF1 */
487 >;
488 MFP_DEFAULT;
489 };
490
491 sd_ldo_en: sd_ldo_en {
492 pinctrl-single,pins = <
493 GPIO45 AF0
494 >;
495 MFP_PULL_DOWN;
496 };
497 sdh0_pmx_func1: sdh0_pmx_func1 {
498 pinctrl-single,pins = <
499 MMC1_DAT3 AF0
500 MMC1_DAT2 AF0
501 MMC1_DAT1 AF0
502 MMC1_DAT0 AF0
503 MMC1_CMD AF0
504 >;
505 DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL;
506 };
507 sdh0_pmx_func2: sdh0_pmx_func2 {
508 pinctrl-single,pins = <
509 MMC1_CLK AF0
510 >;
511 DS_MEDIUM;PULL_NONE;EDGE_NONE;
512 };
513 sdh0_pmx_func3: sdh0_pmx_func3 {
514 pinctrl-single,pins = <
515 MMC1_CD AF0
516 >;
517 MFP_PULL_UP;
518 };
519 sdh0_pmx_func1_slow: sdh0_pmx_func1_slow {
520 pinctrl-single,pins = <
521 MMC1_DAT3 AF0
522 MMC1_DAT2 AF0
523 MMC1_DAT1 AF0
524 MMC1_DAT0 AF0
525 MMC1_CMD AF0
526 >;
527 DS_FAST0;PULL_NONE;EDGE_NONE;SL_NORMAL;
528 };
529 sdh0_pmx_func2_slow: sdh0_pmx_func2_slow {
530 pinctrl-single,pins = <
531 MMC1_CLK AF0
532 >;
533 DS_FAST0;PULL_NONE;EDGE_NONE;
534 };
535 sdh0_pmx_func1_fast: sdh0_pmx_func1_fast {
536 pinctrl-single,pins = <
537 MMC1_DAT3 AF0
538 MMC1_DAT2 AF0
539 MMC1_DAT1 AF0
540 MMC1_DAT0 AF0
541 MMC1_CMD AF0
542 >;
543 DS_FAST1;PULL_NONE;EDGE_NONE;SL_NORMAL;
544 };
545 sdh0_pmx_func2_fast: sdh0_pmx_func2_fast {
546 pinctrl-single,pins = <
547 MMC1_CLK AF0
548 >;
549 DS_FAST1;PULL_NONE;EDGE_NONE;
550 };
551
552 sdh1_pmx_func1_fast: sdh1_pmx_func1_fast {
553 pinctrl-single,pins = <
554 TDS_DIO13 AF0 /* WLAN_DAT3 */
555 TDS_DIO14 AF0 /* WLAN_DAT2 */
556 TDS_DIO15 AF0 /* WLAN_DAT1 */
557 TDS_DIO16 AF0 /* WLAN_DAT0 */
558 TDS_DIO17 AF0 /* WLAN_CMD */
559 >;
560 DS_FAST0;PULL_NONE;EDGE_NONE;SL_NORMAL;
561 };
562 sdh1_pmx_func2_fast: sdh1_pmx_func2_fast {
563 pinctrl-single,pins = <
564 TDS_DIO18 AF0 /* WLAN_CLK */
565 >;
566 DS_FAST0;PULL_DOWN;EDGE_NONE;SL_NORMAL;
567 };
568 sdh1_pmx_func1: sdh1_pmx_func1 {
569 pinctrl-single,pins = <
570 TDS_DIO13 AF0 /* WLAN_DAT3 */
571 TDS_DIO14 AF0 /* WLAN_DAT2 */
572 TDS_DIO15 AF0 /* WLAN_DAT1 */
573 TDS_DIO16 AF0 /* WLAN_DAT0 */
574 TDS_DIO17 AF0 /* WLAN_CMD */
575 >;
576 DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_LOW;
577 };
578 sdh1_pmx_func2: sdh1_pmx_func2 {
579 pinctrl-single,pins = <
580 TDS_DIO18 AF0 /* WLAN_CLK */
581 >;
582 DS_MEDIUM;PULL_DOWN;EDGE_NONE;SL_LOW;
583 };
584 sdh1_pmx_func3: sdh1_pmx_func3 {
585 pinctrl-single,pins = <
586 PRI_TDI AF1 /* WLAN_WAKE_HOST */
587 >;
588 MFP_PULL_DOWN;
589 };
590 sdh1_pmx_edge_wakeup: sdh1_pmx_edge_wakeup {
591 pinctrl-single,pins = <
592 PRI_TDI AF1 /* WLAN_WAKE_HOST */
593 >;
594 DS_MEDIUM;PULL_DOWN;EDGE_RISE;SL_NORMAL;
595 };
596 sdh1_pmx_pd_rst_off: sdh1_pmx_pd_rst_off {
597 pinctrl-single,pins = <
598 PRI_TDO AF1 /* WLAN_PDn */
599 GPIO41 AF0 /* LDO_EN */
600 >;
601 MFP_PULL_DOWN;
602 };
603 sdh1_pmx_pd_rst_on: sdh1_pmx_pd_rst_on {
604 pinctrl-single,pins = <
605 PRI_TDO AF1 /* WLAN_PDn */
606 GPIO41 AF0 /* LDO_EN */
607 >;
608 MFP_PULL_UP;
609 };
610
611 otg_vbus_func: otg_vbus_func {
612 pinctrl-single,pins = <
613 VBUS_DRV AF1 /* GPIO[122] */
614 >;
615 DS_MEDIUM;PULL_DOWN;EDGE_NONE;
616 };
617
618 emac_pmx_func0: emac_pmx_func0 {
619 pinctrl-single,pins = <
620 GPIO00 AF1 /* GMAC1_RX_DV */
621 GPIO01 AF1 /* GMAC1_RX_D0 */
622 GPIO02 AF1 /* GMAC1_RX_D1 */
623 GPIO03 AF1 /* GMAC1_RX_CLK */
624 /* GPIO04 AF1 GMAC1_RX_D2 */
625 /* GPIO05 AF1 GMAC1_RX_D3 */
626 GPIO06 AF1 /* GMAC1_TX_D0 */
627 GPIO07 AF1 /* GMAC1_TX_D1 */
628 /* GPIO12 AF1 GMAC1_TX_CLK */
629 /* GPIO13 AF1 GMAC1_TX_D2 */
630 /* GPIO14 AF1 GMAC1_TX_D3 */
631 GPIO15 AF1 /* GMAC1_TX_EN */
632 GPIO16 AF1 /* GMAC1_TX_MDC */
633 /* GPIO17 AF1 GMAC1_TX_MDIO */
634 >;
635 DS_MEDIUM;PULL_DOWN;EDGE_NONE;SL_NORMAL;
636 };
637 emac_pmx_func1: emac_pmx_func1 {
638 pinctrl-single,pins = <
639 GPIO04 AF1 /* GMAC1_RX_D2 */
640 GPIO05 AF1 /* GMAC1_RX_D3 */
641 GPIO12 AF1 /* GMAC1_TX_CLK */
642 GPIO13 AF1 /* GMAC1_TX_D2 */
643 GPIO14 AF1 /* GMAC1_TX_D3 */
644 >;
645 DS_MEDIUM;PULL_DOWN;EDGE_NONE;SL_NORMAL;
646 };
647 emac_pmx_func2: emac_pmx_func2 {
648 pinctrl-single,pins = <
649 GPIO17 AF1 /* GMAC1_TX_MDIO */
650 GPIO18 AF1 /* GMAC1_TX_INT_N */
651 >;
652 DS_MEDIUM;PULL_UP;EDGE_NONE;SL_NORMAL;
653 };
654 emac_pmx_func3: emac_pmx_func3 {
655 pinctrl-single,pins = <
656 GPIO20 AF0 /* RESET */
657 PRI_TMS AF1 /* LDO_EN */
658 >;
659 DS_SLOW0;PULL_FLOAT;EDGE_NONE;SL_NORMAL;
660 };
661 usim1_pmx_func: usim1_pmx_func {
662 pinctrl-single,pins = <
663 GPIO19 AF0
664 >;
665 DS_MEDIUM;PULL_UP;EDGE_NONE;SL_NORMAL;
666 };
667 usim1_pmx_func_sleep: usim1_pmx_func_sleep {
668 pinctrl-single,pins = <
669 GPIO19 AF0
670 >;
671 DS_MEDIUM;PULL_UP;EDGE_BOTH;SL_NORMAL;
672 };
673 usim2_pmx_func: usim2_pmx_func {
674 pinctrl-single,pins = <
675 GPIO44 AF0
676 >;
677 DS_MEDIUM;PULL_UP;EDGE_NONE;SL_NORMAL;
678 };
679 usim2_pmx_func_sleep: usim2_pmx_func_sleep {
680 pinctrl-single,pins = <
681 GPIO44 AF0
682 >;
683 DS_MEDIUM;PULL_UP;EDGE_BOTH;SL_NORMAL;
684 };
685 pcie_pmx_pd_rst_off: pcie_pmx_pd_rst_off {
686 pinctrl-single,pins = <
687 GPIO42 AF0 /* PERST_N */
688 GPIO53 AF0 /* DC_EN */
689 >;
690 MFP_PULL_DOWN;
691 };
692 pcie_pmx_pd_rst_on: pcie_pmx_pd_rst_on {
693 pinctrl-single,pins = <
694 GPIO42 AF0 /* PERST_N */
695 GPIO53 AF0 /* DC_EN */
696 >;
697 MFP_PULL_UP;
698 };
699
700 gc032a_pmx_func: gc032a_pmx_func {
701 pinctrl-single,pins = <
702 GPIO21 AF2 /* mclk */
703 >;
704 DS_SLOW0;PULL_FLOAT;EDGE_NONE;SL_NORMAL;
705 };
706 isp_spi_data: isp_spi_data {
707 pinctrl-single,pins = <
708 /* spi_data0 ... spi_data1 */
709 GPIO24 AF2
710 GPIO23 AF2
711 /* camera spi clk */
712 GPIO22 AF2
713 >;
714 DS_MEDIUM;PULL_FLOAT;EDGE_NONE;SL_NORMAL;
715 };
716 usb_id_pinmux: usb_id_pinmux {
717 pinctrl-single,pins = <
718 USB_ID AF1/* usbid-gpio99 */
719 >;
720 DS_MEDIUM;PULL_UP;EDGE_NONE;LPM_NONE;
721 };
722 usb_id_pinmux_slp: usb_id_pinmux_slp {
723 pinctrl-single,pins = <
724 USB_ID AF1 /* usbid-gpio99 */
725 >;
726 DS_MEDIUM;PULL_UP;EDGE_BOTH;LPM_NONE;
727 };
728 usb_host_pinmux: usb_host_pinmux {
729 pinctrl-single,pins = <
730 VBUS_DRV AF1 /* gpio-122 */
731 >;
732 DS_MEDIUM;PULL_FLOAT;EDGE_NONE;LPM_NONE;
733 };
734 };
735
736 ssp0: spi@d401b000 {
737 status = "okay";
738 pinctrl-names = "default";
739 pinctrl-0 = <&ssp0_pmx_func>;
740 asr,spi-inc-mode;
741 };
742 twsi0: i2c@d4011000 {
743 status= "okay";
744 /*
745 pmic4: 88pm805@38 {
746 compatible = "marvell,88pm805";
747 reg = <0x38>;
748 };
749 */
750 };
751 twsi1: i2c@d4010800 {
752 pinctrl-names = "default","gpio";
753 pinctrl-0 = <&twsi1_pmx_func>;
754 pinctrl-1 = <&twsi1_pmx_gpio>;
755 i2c-gpio = <&gpio 10 0 &gpio 11 0>;
756 status= "okay";
757 nau8810@1a {
758 compatible = "marvell,nau8810";
759 reg = <0x1a>;
760 };
761 ft6336: touchscreen@38 {
762 compatible = "focaltech,ft6236";
763 reg = <0x38>;
764 interrupt-parent = <&gpio>;
765 interrupts = <54 0>;
766 pinctrl-names = "default";
767 pinctrl-0 = <&tp_pinmux>;
768 reset-gpios = <&gpio 8 1>; /* active low */
769 touchscreen-inverted-y;
770 /* hw ts resolution does not match display */
771 touchscreen-size-y = <854>;
772 touchscreen-size-x = <480>;
773 touchscreen-swapped-x-y;
774 };
775 gc032a: gc032a@21{
776 compatible = "galaxycore,gc032a";
777 reg = <0x21>;
778 pinctrl-names = "default";
779 pinctrl-0 = <&gc032a_pmx_func>;
780 pwdn-gpios = <&gpio 37 0>;
781 power-gpios = <&gpio 40 0>;
782 /*avdd-supply = <&pm802ldo6>;//2v8
783 iovdd-supply = <&pm802ldo5>;//1v8*/
784
785 status = "okay";
786 port {
787 gc0312_out: endpoint {
788 remote-endpoint = <&spi_in_cam>;
789 };
790 };
791 };
792 };
793 twsi2: i2c@d4037000 {
794 status = "okay";
795
796 pmic4: 88pm805@38 {
797 compatible = "marvell,88pm805";
798 reg = <0x38>;
799 };
800
801 pmic5: pm802@0 {
802 compatible = "asr,pm802";
803 reg = <0x00>;
804 interrupts = <4>;
805 interrupt-parent = <&intc>;
806 interrupt-controller;
807 #interrupt-cells = <1>;
808 chg_irq_from_exton;
809 scs-int-active-high;
810 battery {
811 compatible = "asr,pm802-bat";
812 status = "disabled";
813
814 online-gpadc = <1>;
815 temperature-gpadc = <1>;
816
817 hi-volt-online = <1150>; /* mV */
818 lo-volt-online = <20>; /* mV */
819 hi-volt-temp = <1150>; /* mV */
820 lo-volt-temp = <200>; /* mV */
821
822 sw-fg-use-ntc;
823 full-capacity = <2050>; /* mAh */
824 r1-resistor = <40>; /* mohm */
825 r2-resistor = <30>; /* mohm */
826 rs-resistor = <120>; /* mohm */
827 roff-resistor = <0>; /* mohm */
828 roff-initial-resistor = <0>; /* mohm */
829
830 times-in-zero-degree = <1>;
831 offset-in-zero-degree = <0>;
832
833 times-in-ten-degree = <2>;
834 offset-in-ten-degree = <100>;
835
836 power-off-threshold = <3350>; /* mV */
837 safe-power-off-threshold = <3200>; /* mV */
838
839 online-gp-bias-curr = <11>; /* uA */
840
841 soc-ramp-up-interval = <150>; /* s */
842 /* choose -20C, 0C, 10C, 40C, 45C, 55C as threshold */
843 tbat-threshold = <20 0 10 40 45 55>; /* ohm */
844 ntc-table-size = <88>;
845 stop-chg-for-vbatmeas;
846 /* -24C, -23C, ..., 62C, 63C */
847 ntc-table = <
848 89680 85130 80840 76790 72970 69360 65960 62740
849 59700 56830 54130 51530 49100 46800 44610 42550
850 40590 38730 36970 35300 33710 32210 30780 29420
851 28130 26910 25750 24640 23590 22580 21630 20720
852 19860 19030 18250 17500 16790 16110 15460 14840
853 14250 13690 13150 12640 12150 11680 11230 10800
854 10390 10000 9620 9270 8920 8590 8280 7980
855 7690 7410 7150 6890 6650 6410 6190 5970
856 5770 5570 5380 5190 5020 4850 4680 4530
857 4380 4230 4100 3960 3830 3710 3590 3480
858 3370 3260 3160 3060 2960 2870 2780 2700
859 >;
860 };
861 usb {
862 status = "disabled";
863 vbus_gpio = <0xff>; /* set_vbus */
864 id-gpadc = <0xff>; /* usb-id */
865 vchg-from-exton = <1>;
866 vbus-detect = <1>; /* vbus-irq */
867 get-vbus = <1>; /* get-vbus */
868 };
869 };
870 pmic6: pm803@30 {
871 compatible = "asr,pm803";
872 reg = <0x30>;
873 interrupts = <4>;
874 interrupt-parent = <&intc>;
875 interrupt-controller;
876 #interrupt-cells = <1>;
877 chg_irq_from_exton;
878 scs-int-active-high;
879 battery {
880 compatible = "asr,pm803-bat";
881 status = "disabled";
882
883 online-gpadc = <1>;
884 temperature-gpadc = <1>;
885
886 hi-volt-online = <1150>; /* mV */
887 lo-volt-online = <20>; /* mV */
888 hi-volt-temp = <1150>; /* mV */
889 lo-volt-temp = <200>; /* mV */
890
891 sw-fg-use-ntc;
892 full-capacity = <2050>; /* mAh */
893 r1-resistor = <40>; /* mohm */
894 r2-resistor = <30>; /* mohm */
895 rs-resistor = <120>; /* mohm */
896 roff-resistor = <0>; /* mohm */
897 roff-initial-resistor = <0>; /* mohm */
898
899 times-in-zero-degree = <1>;
900 offset-in-zero-degree = <0>;
901
902 times-in-ten-degree = <2>;
903 offset-in-ten-degree = <100>;
904
905 power-off-threshold = <3350>; /* mV */
906 safe-power-off-threshold = <3200>; /* mV */
907
908 online-gp-bias-curr = <11>; /* uA */
909
910 soc-ramp-up-interval = <150>; /* s */
911 /* choose -20C, 0C, 10C, 40C, 45C, 55C as threshold */
912 tbat-threshold = <20 0 10 40 45 55>; /* ohm */
913 ntc-table-size = <88>;
914 stop-chg-for-vbatmeas;
915 /* -24C, -23C, ..., 62C, 63C */
916 ntc-table = <
917 89680 85130 80840 76790 72970 69360 65960 62740
918 59700 56830 54130 51530 49100 46800 44610 42550
919 40590 38730 36970 35300 33710 32210 30780 29420
920 28130 26910 25750 24640 23590 22580 21630 20720
921 19860 19030 18250 17500 16790 16110 15460 14840
922 14250 13690 13150 12640 12150 11680 11230 10800
923 10390 10000 9620 9270 8920 8590 8280 7980
924 7690 7410 7150 6890 6650 6410 6190 5970
925 5770 5570 5380 5190 5020 4850 4680 4530
926 4380 4230 4100 3960 3830 3710 3590 3480
927 3370 3260 3160 3060 2960 2870 2780 2700
928 >;
929 };
930 usb {
931 status = "disabled";
932 vbus_gpio = <0xff>; /* set_vbus */
933 id-gpadc = <0xff>; /* usb-id */
934 vchg-from-exton = <1>;
935 vbus-detect = <1>; /* vbus-irq */
936 get-vbus = <1>; /* get-vbus */
937 };
938 };
939 };
940 };
941 };
942
943 vcc_sdh1: sd-regulator {
944 compatible = "regulator-fixed";
945 pinctrl-names = "default";
946 pinctrl-0 = <&sd_ldo_en>;
947 regulator-name = "SDH1 VCC";
948 regulator-min-microvolt = <3300000>;
949 regulator-max-microvolt = <3300000>;
950 gpio = <&gpio 45 0>;
951 enable-active-high;
952 status = "okay";
953 };
954
955 asr-rfkill {
956 compatible = "asr,asr-rfkill";
957 pinctrl-names = "off", "on";
958 pinctrl-0 = <&sdh1_pmx_pd_rst_off>;
959 pinctrl-1 = <&sdh1_pmx_pd_rst_on>;
960 sd-host = <&sdh1>;
961 pd-gpio = <&gpio 120 0>;
962 3v3-ldo-gpio = <&gpio 41 0>;
963 edge-wakeup-gpio = <&gpio 117 0>;
964 status = "okay";
965 };
966
967 pcie-rfkill {
968 compatible = "mrvl,pcie-rfkill";
969 pinctrl-names = "off", "on";
970 pinctrl-0 = <&pcie_pmx_pd_rst_off>;
971 pinctrl-1 = <&pcie_pmx_pd_rst_on>;
972 rst-gpio = <&gpio 42 0>;
973 3v3-ldo-gpio = <&gpio 53 0>;
974 status = "okay";
975 };
976
977 usim1: usim1 {
978 compatible = "asr,usim1";
979 pinctrl-names = "default", "sleep";
980 pinctrl-0 = <&usim1_pmx_func>;
981 pinctrl-1 = <&usim1_pmx_func_sleep>;
982 edge_detect_gpio = <19>; /* GPIO19: SIM detect pin */
983 status = "okay";
984 };
985 usim2: usim2 {
986 compatible = "asr,usim2";
987 pinctrl-names = "default", "sleep";
988 pinctrl-0 = <&usim2_pmx_func>;
989 pinctrl-1 = <&usim2_pmx_func_sleep>;
990 edge_detect_gpio = <44>; /* GPIO44: SIM detect pin */
991#ifdef CONFIG_ASR_DSDS
992 status = "okay";
993#else
994 status = "disabled";
995#endif
996 };
997
998 audio_regs {
999 compatible = "ASRMICRO,audio-registers";
1000 reg = <0xD4050044 0x4>;
1001 status = "okay";
1002 };
1003};
1004#ifdef CONFIG_ASR_DSDS
1005#include "asr_pm802_2usim.dtsi"
1006#include "88pm805.dtsi"
1007#include "asr_pm803_2usim.dtsi"
1008#else
1009#include "asr_pm802.dtsi"
1010#include "88pm805.dtsi"
1011#include "asr_pm803.dtsi"
1012#endif
1013
1014#ifdef CONFIG_AB_SYSTEM
1015#include "asr1806_ab_flash_layout.dtsi"
1016#else
1017#include "asr1806_flash_layout.dtsi"
1018#endif