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192.168.1.100 / T108 / c2023d5d03be91dbb983606f0ec5e9e4ea36c8c2 / . / marvell / linux / arch / arm / boot / dts / asr1828-p801.dts
blob: 003fdca8735462079e9601076a60cf7dd407a4df [file] [log] [blame]
b.liue9582032025-04-17 19:18:16 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2021 ASR Technology Group Ltd.
4 */
5
6/dts-v1/;
7#include "asr1828.dtsi"
8
9/ {
10 model = "ASR 1828(KAGU) Board EVB";
11 compatible = "asr,1803-evb", "asr,1803";
12
13 chosen {
14 bootargs = "root=/dev/mtdblock5 rootfstype=squashfs init=/etc/preinit noinitrd console=ttyS0,115200 mem=128M";
15 };
16
17 memory {
18 reg = <0x00000000 0x10000000>;
19 };
20
21 firmware {
22 optee {
23 compatible = "linaro,optee-tz";
24 method = "smc";
25 };
26 };
27
28 soc {
29 axi@d4200000 { /* AXI */
30 usb3phy: usb3phy@c0030000 {
31 status = "okay";
32 };
33#ifndef CONFIG_USB_DWC3_ASR_OTG
34 usb3_0: usb3-0 {
35 status = "okay";
36 };
37#else
38 usb3_0_otg: usb3-0-otg {
39 pinctrl-names = "default","sleep";
40 pinctrl-0 = <&usb_id_pinmux &usb_host_pinmux>;
41 pinctrl-1 = <&usb_id_pinmux_slp &usb_host_pinmux>;
42 usbid_gpio = <65>;
43 edge_detect_gpio = <99>;
44 otg,use-gpio-vbus;
45 gpio-num = <122>;
46 status = "okay";
47 };
48#endif
49 eth0: asr-eth@0xd4281800 {
50 compatible = "asr,asr-eth-v2";
51 pinctrl-names = "default", "rgmii-pins";
52 pinctrl-0 = <&emac_pmx_func0 &emac_pmx_func2 &emac_pmx_func3 &emac_pmx_func4>;
53 pinctrl-1 = <&emac_pmx_func0 &emac_pmx_func1 &emac_pmx_func2 &emac_pmx_func3 &emac_pmx_func4>;
54 reg = <0xd4281800 0x200>;
55 interrupts = <10 11>;
56 lpm-qos = <PM_QOS_CPUIDLE_BLOCK_AXI>;
57 clocks = <&soc_clocks ASR1803_CLK_EMAC>;
58 clock-names = "emac-clk";
59 status = "okay";
60
61 ldo-gpio = <&gpio 20 0>;
62 ldo-active-low;
63 ldo-delays-us = <0 100000 100000>;
64
65 reset-gpio = <&gpio 19 0>;
66 reset-active-low;
67 reset-delays-us = <0 100000 100000>;
68
69 clk-tuning-enable;
70 /* clk-config(32bit)
71 *
72 * rmii_ref_clk(clk-config[31:24])
73 * 0 - from SOC
74 * 1 - from phy
75 * clk_sel(clk-config[23:16])
76 * RGMII:
77 * tx | clk_sel: 0 - from RX clock
78 * 1 - from SOC clock
79 * rx | clk_sel: not care
80 *
81 * RMII:
82 * tx | clk_sel: 0 - RMII clock
83 * 1 - Inverted RMII clock
84 * rx | clk_sel: 0 - RMII clock
85 * 1 - Inverted RMII clock
86 *
87 * delay_code(clk-config[15:8])
88 * 0 ~ 255
89 *
90 * delay_step(clk-config[7:0])
91 * 0b000 - 22ps
92 * 0b001 - 29ps
93 * 0b010 - 36ps
94 * 0b011 - 43ps
95 */
96 tx-clk-config = <0x2e03>;
97 rx-clk-config = <0x0>;
98
99 phy-handle = <&phy0>;
100
101 /* enable fix link for ethernet switch */
102 /*
103 fixed-link {
104 speed = <100>;
105 full-duplex;
106 phy-mode = "rmii";
107 };
108 */
109
110 mdio: mdio-bus {
111 #address-cells = <0x1>;
112 #size-cells = <0x0>;
113 /* YT8521 10M/100M/100OM 1.8V RGMII PHY */
114 phy0: phy@0 {
115 compatible = "ethernet-phy-ieee802.3-c22";
116 device_type = "ethernet-phy";
117 reg = <0x0>; /* set phy address*/
118 phy-mode = "rgmii";
119 tx_rx_delay = <0x0 0x0>; /* 150ps per step*/
120 };
121 };
122 };
123 qspi: spi@0xd420b000 {
124 asr,qspi-freq = <78000000>;
125 status = "okay";
126 };
127 /* SD card */
128 sdh0: sdh@d4280000 {
129 pinctrl-names = "default", "slow", "fast", "sleep";
130 pinctrl-0 = <&sdh0_pmx_func1 &sdh0_pmx_func2 &sdh0_pmx_func3>;
131 pinctrl-1 = <&sdh0_pmx_func1_slow &sdh0_pmx_func2_slow &sdh0_pmx_func3>;
132 pinctrl-2 = <&sdh0_pmx_func1_fast &sdh0_pmx_func2_fast &sdh0_pmx_func3>;
133 pinctrl-3 = <&sdh0_pmx_cd_wakeup>;
134 vmmc-supply = <&pm802ldo4>;
135 vqmmc-supply = <&pm802ldo6>;
136 /* vmmc2-supply = <&vcc_sdh1>; */
137 /* vqmmc2-supply = <&pm803ldo8>; */
138 bus-width = <4>;
139 no-mmc;
140 no-sdio;
141 /*non-removable;
142 broken-cd;*/
143 wp-inverted;
144 asr,sdh-pm-runtime-en;
145 asr,sdh-host-caps-disable = <(MMC_CAP_UHS_SDR104)>;
146#if 1 /* CD via gpio */
147 cd-gpios = <&gpio 64 1>;
148 asr,sdh-quirks2 = <(
149 SDHCI_QUIRK2_SET_AIB_MMC |
150 SDHCI_QUIRK2_PRESET_VALUE_BROKEN
151 )>;
152 asr,sdh-host-caps = <(
153 MMC_CAP_CD_WAKE
154 )>;
155 asr,sdh-quirks = <(
156 SDHCI_QUIRK_BROKEN_CARD_DETECTION |
157 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
158 )>;
159#else /* CD via SDH */
160 asr,sdh-quirks = <(
161 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
162 )>;
163 asr,sdh-quirks2 = <(
164 SDHCI_QUIRK2_SET_AIB_MMC |
165 SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
166 SDHCI_QUIRK2_BASE_CLOCK_ALWAYS_ON
167 )>;
168#endif
169 /* prop "sdh-dtr-data":
170 <timing preset_rate src_rate tx_delay rx_delay tx_dline_reg rx_dline_reg> */
171 asr,sdh-dtr-data =
172 <PXA_MMC_TIMING_LEGACY PXA_SDH_DTR_26M PXA_SDH_DTR_104M 0 0 0 0>,
173 <PXA_MMC_TIMING_SD_HS PXA_SDH_DTR_52M PXA_SDH_DTR_104M 0 0 0 0>,
174 <PXA_MMC_TIMING_UHS_DDR50 PXA_SDH_DTR_52M PXA_SDH_DTR_104M 0 0 0 3>,
175 <PXA_MMC_TIMING_UHS_SDR50 PXA_SDH_DTR_104M PXA_SDH_DTR_208M 0 0 0 0>,
176 <PXA_MMC_TIMING_UHS_SDR104 PXA_SDH_DTR_208M PXA_SDH_DTR_208M 0 0 0 0>,
177 <PXA_MMC_TIMING_MAX PXA_SDH_DTR_PS_NONE PXA_SDH_DTR_104M 0 0 0 0>;
178 status = "okay";
179 };
180
181 /* SDIO */
182 sdh1: sdh@d4280800 {
183 pinctrl-names = "default", "fast", "sleep";
184 pinctrl-0 = <&sdh1_pmx_func1 &sdh1_pmx_func2 &sdh1_pmx_func3>;
185 pinctrl-1 = <&sdh1_pmx_func1_fast &sdh1_pmx_func2_fast &sdh1_pmx_func3>;
186 pinctrl-2 = <&sdh1_pmx_edge_wakeup>;
187 bus-width = <4>;
188 no-mmc;
189 no-sd;
190 non-removable;
191 keep-power-in-suspend;
192 enable-sdio-wakeup;
193 /* clk-scaling-config:
194 <up_threshold down_threshold polling_interval> */
195 clk-scaling-config = <25 12 200>;
196 min-ddr-qos = <156000 312000 400000>;
197 asr,sdh-pm-runtime-en;
198 asr,sdh-quirks = <(
199 SDHCI_QUIRK_BROKEN_CARD_DETECTION |
200 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
201 )>;
202 asr,sdh-quirks2 = <(
203 SDHCI_QUIRK2_TIMEOUT_SHORT |
204 SDHCI_QUIRK2_NO_TIMER_RETUNING |
205 SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
206 SDHCI_QUIRK2_BASE_CLOCK_ALWAYS_ON
207 )>;
208 asr,sdh-pm-caps = <(MMC_PM_KEEP_POWER)>;
209 asr,sdh-host-caps2 = <(
210 MMC_CAP2_ONLY_1_8V |
211 MMC_CAP2_DISABLE_PROBE_CDSCAN |
212 MMC_CAP2_CLK_SCALE |
213 MMC_CAP2_BUS_CLK_NO_SCALE
214 )>;
215 /* prop "sdh-dtr-data":
216 <timing preset_rate src_rate tx_delay rx_delay tx_dline_reg rx_dline_reg> */
217 asr,sdh-dtr-data =
218 <PXA_MMC_TIMING_LEGACY PXA_SDH_DTR_26M PXA_SDH_DTR_104M 0 0 0 0>,
219 <PXA_MMC_TIMING_SD_HS PXA_SDH_DTR_45M PXA_SDH_DTR_89M 0 0 0 0>,
220 <PXA_MMC_TIMING_UHS_DDR50 PXA_SDH_DTR_52M PXA_SDH_DTR_104M 0 0 0 3>,
221 <PXA_MMC_TIMING_UHS_SDR50 PXA_SDH_DTR_83M PXA_SDH_DTR_83M 0 0 0 3>,
222 <PXA_MMC_TIMING_UHS_SDR104 PXA_SDH_DTR_208M PXA_SDH_DTR_208M 0 0 0 0>,
223 <PXA_MMC_TIMING_MAX PXA_SDH_DTR_PS_NONE PXA_SDH_DTR_89M 0 0 0 0>;
224 status = "okay";
225 };
226 pcie0: pcie@0xd4288000{
227 reset-gpios = <&gpio 80 0>;
228 status = "okay";
229 };
230 pcie1: pcie@0xd428c000{
231 reset-gpios = <&gpio 72 0>;
232 status = "okay";
233 };
234 pciephy0: pcie-phy@d4210000 {
235 status = "okay";
236 };
237 pciephy1: pcie-phy@d4220000{
238 status = "okay";
239 };
240 };
241
242 apb@d4000000 {
243 ssp_dai1: pxa-ssp-dai@1 {
244 compatible = "asr,pxa-ssp-dai";
245 reg = <0x1 0x0>;
246 };
247 mfpr: mfpr@d401e000 {
248 status = "okay";
249 };
250 timer0: timer@d4014000 {
251 status = "okay";
252 };
253 uart1: uart@d4017000 { /* nezhas evb use ap uart */
254 pinctrl-names = "default","sleep";
255 pinctrl-0 = <&uart1_pmx_func1 &uart1_pmx_func2>;
256 pinctrl-1 = <&uart1_pmx_func1_sleep &uart1_pmx_func2>;
257 edge-wakeup-gpio = <&gpio 29 0>; /* GPIO29: AP UART rx pin */
258 status = "okay";
259 };
260 uart2: uart@d4036000 {
261 pinctrl-names = "default";
262 pinctrl-0 = <&gps_pmx_uart_rxd &gps_pmx_uart_txd>;
263 status = "okay";
264 };
265 uart3: uart@d4018000 {
266 pinctrl-names = "default";
267 pinctrl-0 = <&uart3_pmx_func>;
268 status = "disabled";
269 };
270 rtc: rtc@d4010000 {
271 status = "okay";
272 };
273 pmx: pinmux@d401e000 {
274 /* pin base = base_addr / 4, nr pins & gpio function */
275 pinctrl-single,gpio-range = <
276 /*
277 * GPIO number is hardcoded for range at here.
278 * In gpio chip, GPIO number is not hardcoded for range.
279 * Since one gpio pin may be routed to multiple pins,
280 * define these gpio range in pxa910-dkb.dts not pxa910.dtsi.
281 */
282 /*&range 80 4 0 */ /* GPIO25 ~ GPIO28 */
283 &range 55 32 0 /* GPIO0 ~ GPIO31 */
284 &range 87 32 0 /* GPIO32 ~ GPIO63 */
285 &range 119 32 0 /* GPIO64 ~ GPIO95 */
286 &range 151 32 0 /* GPIO96 ~ GPIO127 */
287 >;
288
289 ssp0_pmx_func: ssp0_pmx_func {
290 pinctrl-single,pins = <
291 GPIO36 AF1 /* TXD */
292 GPIO35 AF1 /* RXD */
293 GPIO34 AF1 /* FRM */
294 /*GPIO34 AF0*/ /* FRM *//* DXS101 Use the config of Cs-gpios */
295 GPIO33 AF1 /* SCLK */
296 >;
297 DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL;
298 };
299 lcd_bl_func: lcd_bl_func {
300 pinctrl-single,pins = <
301 VCXO_OUT AF1 /* GPIO126, lcd bl */
302 GPIO23 AF0 /* reset */
303 GPIO24 AF0 /* lcd d/c */
304 >;
305 MFP_DEFAULT;
306 };
307 uart1_pmx_func1: uart1_pmx_func1 {
308 pinctrl-single,pins = <
309 GPIO29 AF1
310 >;
311 MFP_DEFAULT;
312 };
313 uart1_pmx_func2: uart1_pmx_func2 {
314 pinctrl-single,pins = <
315 GPIO30 AF1
316 >;
317 MFP_DEFAULT;
318 };
319 uart1_pmx_func1_sleep: uart1_pmx_func1_sleep {
320 pinctrl-single,pins = <
321 GPIO29 AF1
322 >;
323 DS_MEDIUM;PULL_NONE;EDGE_BOTH;SL_NORMAL;
324 };
325 twsi0_pmx_func: twsi0_pmx_func {
326 pinctrl-single,pins = <
327 GPIO49 AF1
328 GPIO50 AF1
329 >;
330 MFP_LPM_FLOAT;
331 };
332 twsi0_pmx_gpio: twsi0_pmx_gpio {
333 pinctrl-single,pins = <
334 GPIO49 AF0
335 GPIO50 AF0
336 >;
337 MFP_LPM_FLOAT;
338 };
339 twsi1_pmx_func: twsi1_pmx_func {
340 pinctrl-single,pins = <
341 GPIO10 AF1
342 GPIO11 AF1
343 >;
344 MFP_LPM_FLOAT;
345 };
346 twsi1_pmx_gpio: twsi1_pmx_gpio {
347 pinctrl-single,pins = <
348 GPIO10 AF0
349 GPIO11 AF0
350 >;
351 MFP_LPM_FLOAT;
352 };
353 /* no pull, no LPM */
354 dvc_pmx_func: dvc_pmx_func {
355 /* hw-dvc */
356 pinctrl-single,pins = <
357 TDS_DIO0 AF0
358 TDS_DIO1 AF0
359 >;
360 DS_MEDIUM;PULL_FLOAT;EDGE_NONE;SL_NORMAL;
361 };
362 leds_pmx_func: leds_pmx_func {
363 pinctrl-single,pins = <
364 DF_IO10 AF1
365 DF_IO11 AF1
366 DF_IO12 AF1
367 >;
368 DS_MEDIUM;PULL_FLOAT;EDGE_NONE;SL_NORMAL;
369 };
370
371 gps_pmx_onoff: gps_pmx_onoff {
372 pinctrl-single,pins = <
373 TDS_TXREV AF1
374 >;
375 DS_MEDIUM;PULL_DOWN;EDGE_NONE;SL_NORMAL;
376 };
377 gps_pmx_reset: gps_pmx_reset {
378 pinctrl-single,pins = <
379 TDS_RXON AF1
380 >;
381 DS_MEDIUM;PULL_DOWN;EDGE_NONE;SL_NORMAL;
382 };
383 gps_pmx_uart_rxd: gps_pmx_uart_rxd {
384 /* gps dedicated uart */
385 pinctrl-single,pins = <
386 GPIO51 AF1
387 >;
388 MFP_DEFAULT;
389 };
390 gps_pmx_uart_txd: gps_pmx_uart_txd {
391 /* gps dedicated uart */
392 pinctrl-single,pins = <
393 GPIO52 AF1
394 >;
395 MFP_DEFAULT;
396 };
397 uart3_pmx_func: uart3_pmx_func {
398 pinctrl-single,pins = <
399 GPIO53 AF1 /* RX */
400 GPIO54 AF1 /* TX */
401 >;
402 MFP_DEFAULT;
403 };
404 panel_rst_func: panel_rst_func {
405 pinctrl-single,pins = <
406 DF_nCS1 AF1
407 >;
408 DS_MEDIUM;PULL_FLOAT;EDGE_NONE;SL_NORMAL;
409 };
410
411 sd_ldo_en: sd_ldo_en {
412 pinctrl-single,pins = <
413 GPIO12 AF0
414 >;
415 MFP_PULL_DOWN;
416 };
417 sdh0_pmx_func1: sdh0_pmx_func1 {
418 pinctrl-single,pins = <
419 MMC1_DAT3 AF0
420 MMC1_DAT2 AF0
421 MMC1_DAT1 AF0
422 MMC1_DAT0 AF0
423 MMC1_CMD AF0
424 >;
425 DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL;
426 };
427 sdh0_pmx_func2: sdh0_pmx_func2 {
428 pinctrl-single,pins = <
429 MMC1_CLK AF0
430 >;
431 DS_MEDIUM;PULL_NONE;EDGE_NONE;
432 };
433 sdh0_pmx_func3: sdh0_pmx_func3 {
434 pinctrl-single,pins = <
435 MMC1_CD AF1
436 >;
437 DS_MEDIUM;PULL_UP;EDGE_NONE;SL_NORMAL;
438 };
439 sdh0_pmx_cd_wakeup: sdh0_pmx_func1_cd_wakeup {
440 pinctrl-single,pins = <
441 MMC1_CD AF1
442 >;
443 DS_MEDIUM;PULL_UP;EDGE_BOTH;SL_NORMAL;
444 };
445 sdh0_pmx_func1_slow: sdh0_pmx_func1_slow {
446 pinctrl-single,pins = <
447 MMC1_DAT3 AF0
448 MMC1_DAT2 AF0
449 MMC1_DAT1 AF0
450 MMC1_DAT0 AF0
451 MMC1_CMD AF0
452 >;
453 DS_SLOW0;PULL_NONE;EDGE_NONE;SL_NORMAL;
454 };
455 sdh0_pmx_func2_slow: sdh0_pmx_func2_slow {
456 pinctrl-single,pins = <
457 MMC1_CLK AF0
458 >;
459 DS_SLOW0;PULL_NONE;EDGE_NONE;
460 };
461 sdh0_pmx_func1_fast: sdh0_pmx_func1_fast {
462 pinctrl-single,pins = <
463 MMC1_DAT3 AF0
464 MMC1_DAT2 AF0
465 MMC1_DAT1 AF0
466 MMC1_DAT0 AF0
467 MMC1_CMD AF0
468 >;
469 DS_FAST1;PULL_NONE;EDGE_NONE;SL_NORMAL;
470 };
471 sdh0_pmx_func2_fast: sdh0_pmx_func2_fast {
472 pinctrl-single,pins = <
473 MMC1_CLK AF0
474 >;
475 DS_FAST1;PULL_NONE;EDGE_NONE;
476 };
477 sdh1_pmx_func1_fast: sdh1_pmx_func1_fast {
478 pinctrl-single,pins = <
479 TDS_DIO13 AF0 /* WLAN_DAT3 */
480 TDS_DIO14 AF0 /* WLAN_DAT2 */
481 TDS_DIO15 AF0 /* WLAN_DAT1 */
482 TDS_DIO16 AF0 /* WLAN_DAT0 */
483 TDS_DIO17 AF0 /* WLAN_CMD */
484 >;
485 DS_FAST0;PULL_NONE;EDGE_NONE;SL_NORMAL;
486 };
487 sdh1_pmx_func2_fast: sdh1_pmx_func2_fast {
488 pinctrl-single,pins = <
489 TDS_DIO18 AF0 /* WLAN_CLK */
490 >;
491 DS_FAST0;PULL_DOWN;EDGE_NONE;SL_NORMAL;
492 };
493 sdh1_pmx_func1: sdh1_pmx_func1 {
494 pinctrl-single,pins = <
495 TDS_DIO13 AF0 /* WLAN_DAT3 */
496 TDS_DIO14 AF0 /* WLAN_DAT2 */
497 TDS_DIO15 AF0 /* WLAN_DAT1 */
498 TDS_DIO16 AF0 /* WLAN_DAT0 */
499 TDS_DIO17 AF0 /* WLAN_CMD */
500 >;
501 DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_LOW;
502 };
503 sdh1_pmx_func2: sdh1_pmx_func2 {
504 pinctrl-single,pins = <
505 TDS_DIO18 AF0 /* WLAN_CLK */
506 >;
507 DS_MEDIUM;PULL_DOWN;EDGE_NONE;SL_LOW;
508 };
509 sdh1_pmx_func3: sdh1_pmx_func3 {
510 pinctrl-single,pins = <
511 GPIO70 AF0 /* VCXO_REQ AF1 WLAN_WAKE_HOST */
512 >;
513 MFP_PULL_DOWN;
514 };
515 sdh1_pmx_edge_wakeup: sdh1_pmx_edge_wakeup {
516 pinctrl-single,pins = <
517 GPIO70 AF0 /* VCXO_REQ AF1 */
518 >;
519 DS_MEDIUM;PULL_DOWN;EDGE_RISE;SL_NORMAL;
520 };
521 sdh1_pmx_pd_rst_off: sdh1_pmx_pd_rst_off {
522 pinctrl-single,pins = <
523 GPIO69 AF0 /* GPIO31 AF0 WLAN_PDn */
524 GPIO62 AF0 /* GPIO32 AF0 LDO_EN */
525 >;
526 MFP_PULL_DOWN;
527 };
528 sdh1_pmx_pd_rst_on: sdh1_pmx_pd_rst_on {
529 pinctrl-single,pins = <
530 GPIO69 AF0 /* GPIO31 AF0 WLAN_PDn */
531 GPIO62 AF0 /* GPIO32 AF0 LDO_EN */
532 >;
533 MFP_PULL_UP;
534 };
535 eta6005_charger_en: eta6005_charger_en {
536 pinctrl-single,pins = <
537 /* GPIO08 AF0 */
538 >;
539 MFP_PULL_UP;
540 };
541 eta6005_charger_stat: eta6005_charger_stat {
542 pinctrl-single,pins = <
543 GPIO04 AF0
544 >;
545 MFP_DEFAULT;
546 };
547
548 alc5616_pmx_func1: alc5616_pmx_func1 {
549 pinctrl-single,pins = <
550 GPIO20 AF7 /* I2S_SYSCLK */
551 GPIO08 AF0 /* AP_UART1_DCD_N -> CODEC_IRQ */
552 >;
553 MFP_DEFAULT;
554 };
555 alc5616_pmx_func2: alc5616_pmx_func2 {
556 pinctrl-single,pins = <
557 GPIO20 AF7 /* I2S_SYSCLK */
558 GPIO08 AF0 /* AP_UART1_DCD_N -> CODEC_IRQ */
559 >;
560 MFP_DEFAULT;
561 };
562
563 ecall_pmx_func: ecall_pmx_func {
564 pinctrl-single,pins = <
565 GPIO08 AF0 /* auto mode ecall */
566 GPIO09 AF0 /* manual mode ecall */
567 >;
568 MFP_DEFAULT;
569 };
570
571 slic_pmx_func1: slic_pmx_func1 {
572 pinctrl-single,pins = <
573 GPIO24 AF0 /* SLIC_INT, GPIO24 */
574 VCXO_OUT AF1 /* GPIO126, SLIC_3V3LDO_EN/LCD_BK_EN */
575 >;
576 MFP_DEFAULT;
577 };
578 slic_pmx_func2: slic_pmx_func2 {
579 pinctrl-single,pins = <
580 GPIO23 AF0 /* SLIC_RESET, GPIO23 */
581 >;
582 MFP_DEFAULT;
583 };
584 slic_pmx_func1_sleep: slic_pmx_func1_sleep {
585 pinctrl-single,pins = <
586 GPIO24 AF0 /* SLIC_INT, GPIO24 */
587 >;
588 DS_MEDIUM;PULL_UP;EDGE_BOTH;SL_NORMAL;
589 };
590
591 otg_vbus_func: otg_vbus_func {
592 pinctrl-single,pins = <
593 VBUS_DRV AF1 /* GPIO[122] */
594 >;
595 DS_MEDIUM;PULL_DOWN;EDGE_NONE;
596 };
597
598 emac_pmx_func0: emac_pmx_func0 {
599 pinctrl-single,pins = <
600 GPIO00 AF1 /* GMAC1_RX_DV */
601 GPIO01 AF1 /* GMAC1_RX_D0 */
602 GPIO02 AF1 /* GMAC1_RX_D1 */
603 GPIO03 AF1 /* GMAC1_RX_CLK */
604 /* GPIO04 AF1 GMAC1_RX_D2 */
605 /* GPIO05 AF1 GMAC1_RX_D3 */
606 GPIO06 AF1 /* GMAC1_TX_D0 */
607 GPIO07 AF1 /* GMAC1_TX_D1 */
608 /* GPIO12 AF1 GMAC1_TX_CLK */
609 /* GPIO13 AF1 GMAC1_TX_D2 */
610 /* GPIO14 AF1 GMAC1_TX_D3 */
611 GPIO15 AF1 /* GMAC1_TX_EN */
612 /* GPIO16 AF1 GMAC1_TX_MDC */
613 /* GPIO17 AF1 GMAC1_TX_MDIO */
614 >;
615 DS_MEDIUM;PULL_DOWN;EDGE_NONE;SL_NORMAL;
616 };
617 emac_pmx_func1: emac_pmx_func1 {
618 pinctrl-single,pins = <
619 GPIO04 AF1 /* GMAC1_RX_D2 */
620 GPIO05 AF1 /* GMAC1_RX_D3 */
621 GPIO12 AF1 /* GMAC1_TX_CLK */
622 GPIO13 AF1 /* GMAC1_TX_D2 */
623 GPIO14 AF1 /* GMAC1_TX_D3 */
624 >;
625 DS_MEDIUM;PULL_DOWN;EDGE_NONE;SL_NORMAL;
626 };
627 emac_pmx_func2: emac_pmx_func2 {
628 pinctrl-single,pins = <
629 GPIO17 AF1 /* GMAC1_TX_MDIO */
630 GPIO18 AF1 /* GMAC1_TX_INT_N */
631 >;
632 DS_MEDIUM;PULL_UP;EDGE_NONE;SL_NORMAL;
633 };
634 emac_pmx_func3: emac_pmx_func3 {
635 pinctrl-single,pins = <
636 GPIO16 AF1 /* GMAC1_TX_MDC */
637 >;
638 DS_SLOW0;PULL_DOWN;EDGE_NONE;SL_NORMAL;
639 };
640 emac_pmx_func4: emac_pmx_func4 {
641 pinctrl-single,pins = <
642 GPIO19 AF0 /* RESET */
643 GPIO20 AF0 /* LDO_EN */
644 >;
645 DS_SLOW0;PULL_FLOAT;EDGE_NONE;SL_NORMAL;
646 };
647 usim1_pmx_func: usim1_pmx_func {
648 pinctrl-single,pins = <
649 GPIO08 AF0
650 >;
651 DS_MEDIUM;PULL_UP;EDGE_NONE;SL_NORMAL;
652 };
653 usim1_pmx_func_sleep: usim1_pmx_func_sleep {
654 pinctrl-single,pins = <
655 GPIO08 AF0
656 >;
657 DS_MEDIUM;PULL_UP;EDGE_BOTH;SL_NORMAL;
658 };
659 pcie_pmx_pd_rst_off: pcie_pmx_pd_rst_off {
660 pinctrl-single,pins = <
661 GPIO72 AF0 /* PERST_N */
662 GPIO22 AF0 /* DC_EN */
663 GPIO80 AF0 /* PERST_N */
664 GPIO21 AF0 /* DC_EN */
665 >;
666 MFP_PULL_DOWN;
667 };
668 pcie_pmx_pd_rst_on: pcie_pmx_pd_rst_on {
669 pinctrl-single,pins = <
670 GPIO72 AF0 /* PERST_N */
671 GPIO22 AF0 /* DC_EN */
672 GPIO80 AF0 /* PERST_N */
673 GPIO21 AF0 /* DC_EN */
674 >;
675 MFP_PULL_UP;
676 };
677 gpiokey_pmx_func: gpiokey_pmx_func {
678 pinctrl-single,pins = <
679 GPIO09 AF0
680 >;
681 DS_MEDIUM;PULL_UP;EDGE_NONE;SL_NORMAL;
682 };
683 usb_id_pinmux: usb_id_pinmux {
684 pinctrl-single,pins = <
685 USB_ID AF1 /* usbid-gpio65 */
686 >;
687 DS_MEDIUM;PULL_UP;EDGE_NONE;LPM_NONE;
688 };
689 usb_id_pinmux_slp: usb_id_pinmux_slp {
690 pinctrl-single,pins = <
691 USB_ID AF1 /* usbid-gpio65 */
692 >;
693 DS_MEDIUM;PULL_UP;EDGE_BOTH;LPM_NONE;
694 };
695 usb_host_pinmux: usb_host_pinmux {
696 pinctrl-single,pins = <
697 VBUS_DRV AF1 /* gpio-122 */
698 >;
699 DS_MEDIUM;PULL_FLOAT;EDGE_NONE;LPM_NONE;
700 };
701 };
702
703 ssp0: spi@d401b000 {
704 status = "okay";
705 pinctrl-names = "default";
706 pinctrl-0 = <&ssp0_pmx_func>;
707 asr,spi-inc-mode;
708#ifdef CONFIG_FB_SPI_LCD
709 /* this enhancemnet feature is not suitable for
710 3 line 9bits spi lcd. */
711 /* asr,ssp-enhancement; */
712
713 lcd: spidev@0 {
714 #address-cells = <1>;
715 #size-cells = <1>;
716 compatible = "spilcd";
717 pinctrl-names = "default";
718 pinctrl-0 = <&lcd_bl_func>;
719 reg = <0>;
720 /* ST7735: need to set spi-max-frequency to 26M
721 * ST7789V: can set spi-max-frequency to 52M
722 */
723 spi-max-frequency = <26000000>;
724 xres = <128>;
725 yres = <128>;
726 bits = <8>; /* 8: 4line, 9: 3line */
727 rst_gpio = <&gpio 23 0>;
728 bl_gpio = <&gpio 126 0>;
729 rs_gpio = <&gpio 24 0>;
730 /* if comment the following statement, it means
731 * the avdd is sit on the "always-on" ldo.
732 */
733 /* avdd-supply = <&LDO1>; */
734 };
735#else
736 /*cs-gpios = <&gpio 34 0>;*//* DXS101 Use the config of Cs-gpios */
737 slic: spidev@0{
738 #address-cells = <1>;
739 #size-cells = <1>;
740 compatible = "asr,slic";
741 reg = <0>;
742 spi-cpol;
743 spi-cpha;
744 spi-max-frequency = <6500000>;
745 };
746#endif
747 };
748 twsi0: i2c@d4011000 {
749 status= "okay";
750#if 0
751 alc5616@1b {
752 compatible = "asrmicro,alc5616";
753 reg = <0x1b>;
754 pinctrl-names = "default", "AUDIO_PA_PDN";
755 pinctrl-0 = <&alc5616_pmx_func1>;
756 pinctrl-1 = <&alc5616_pmx_func2>;
757 i2s_synclk-gpio = <&gpio 20 0>;
758#if 0
759 3V3-gpio = <&gpio 23 0>;/* CODEC_LDO_EN */
760 irq-gpio = <&gpio 24 0>;/* CODEC_IRQ for headset detection */
761#else
762 irq-gpio = <&gpio 8 0>;/* CODEC_IRQ for headset detection */
763#endif
764 };
765#endif
766 /*
767 pmic4: 88pm805@38 {
768 compatible = "marvell,88pm805";
769 reg = <0x38>;
770 };
771 */
772 };
773 twsi1: i2c@d4010800 {
774 status= "disabled";
775 nau8810@1a {
776 compatible = "marvell,nau8810";
777 reg = <0x1a>;
778 };
779 };
780 twsi2: i2c@d4037000 {
781 status = "okay";
782
783 pmic4: 88pm805@38 {
784 compatible = "marvell,88pm805";
785 reg = <0x38>;
786 };
787
788 pmic5: pm802@0 {
789 compatible = "asr,pm802";
790 reg = <0x00>;
791 interrupts = <4>;
792 interrupt-parent = <&intc>;
793 interrupt-controller;
794 #interrupt-cells = <1>;
795 chg_irq_from_exton;
796 battery {
797 compatible = "asr,pm802-bat";
798 status = "disabled";
799
800 online-gpadc = <1>;
801 temperature-gpadc = <1>;
802
803 hi-volt-online = <1150>; /* mV */
804 lo-volt-online = <20>; /* mV */
805 hi-volt-temp = <1150>; /* mV */
806 lo-volt-temp = <200>; /* mV */
807
808 sw-fg-use-ntc;
809 full-capacity = <2050>; /* mAh */
810 r1-resistor = <40>; /* mohm */
811 r2-resistor = <30>; /* mohm */
812 rs-resistor = <120>; /* mohm */
813 roff-resistor = <0>; /* mohm */
814 roff-initial-resistor = <0>; /* mohm */
815
816 times-in-zero-degree = <1>;
817 offset-in-zero-degree = <0>;
818
819 times-in-ten-degree = <2>;
820 offset-in-ten-degree = <100>;
821
822 power-off-threshold = <3350>; /* mV */
823 safe-power-off-threshold = <3200>; /* mV */
824
825 online-gp-bias-curr = <11>; /* uA */
826
827 soc-ramp-up-interval = <150>; /* s */
828 /* choose -20C, 0C, 10C, 40C, 45C, 55C as threshold */
829 tbat-threshold = <20 0 10 40 45 55>; /* ohm */
830 ntc-table-size = <88>;
831 stop-chg-for-vbatmeas;
832 /* -24C, -23C, ..., 62C, 63C */
833 ntc-table = <
834 89680 85130 80840 76790 72970 69360 65960 62740
835 59700 56830 54130 51530 49100 46800 44610 42550
836 40590 38730 36970 35300 33710 32210 30780 29420
837 28130 26910 25750 24640 23590 22580 21630 20720
838 19860 19030 18250 17500 16790 16110 15460 14840
839 14250 13690 13150 12640 12150 11680 11230 10800
840 10390 10000 9620 9270 8920 8590 8280 7980
841 7690 7410 7150 6890 6650 6410 6190 5970
842 5770 5570 5380 5190 5020 4850 4680 4530
843 4380 4230 4100 3960 3830 3710 3590 3480
844 3370 3260 3160 3060 2960 2870 2780 2700
845 >;
846 };
847 usb {
848 status = "disabled";
849 vbus_gpio = <0xff>; /* set_vbus */
850 id-gpadc = <0xff>; /* usb-id */
851 vchg-from-exton = <1>;
852 vbus-detect = <1>; /* vbus-irq */
853 get-vbus = <1>; /* get-vbus */
854 };
855 };
856 pmic6: pm803@30 {
857 compatible = "asr,pm803";
858 reg = <0x30>;
859 interrupts = <4>;
860 interrupt-parent = <&intc>;
861 interrupt-controller;
862 #interrupt-cells = <1>;
863 chg_irq_from_exton;
864 battery {
865 compatible = "asr,pm803-bat";
866 status = "disabled";
867
868 online-gpadc = <1>;
869 temperature-gpadc = <1>;
870
871 hi-volt-online = <1150>; /* mV */
872 lo-volt-online = <20>; /* mV */
873 hi-volt-temp = <1150>; /* mV */
874 lo-volt-temp = <200>; /* mV */
875
876 sw-fg-use-ntc;
877 full-capacity = <2050>; /* mAh */
878 r1-resistor = <40>; /* mohm */
879 r2-resistor = <30>; /* mohm */
880 rs-resistor = <120>; /* mohm */
881 roff-resistor = <0>; /* mohm */
882 roff-initial-resistor = <0>; /* mohm */
883
884 times-in-zero-degree = <1>;
885 offset-in-zero-degree = <0>;
886
887 times-in-ten-degree = <2>;
888 offset-in-ten-degree = <100>;
889
890 power-off-threshold = <3350>; /* mV */
891 safe-power-off-threshold = <3200>; /* mV */
892
893 online-gp-bias-curr = <11>; /* uA */
894
895 soc-ramp-up-interval = <150>; /* s */
896 /* choose -20C, 0C, 10C, 40C, 45C, 55C as threshold */
897 tbat-threshold = <20 0 10 40 45 55>; /* ohm */
898 ntc-table-size = <88>;
899 stop-chg-for-vbatmeas;
900 /* -24C, -23C, ..., 62C, 63C */
901 ntc-table = <
902 89680 85130 80840 76790 72970 69360 65960 62740
903 59700 56830 54130 51530 49100 46800 44610 42550
904 40590 38730 36970 35300 33710 32210 30780 29420
905 28130 26910 25750 24640 23590 22580 21630 20720
906 19860 19030 18250 17500 16790 16110 15460 14840
907 14250 13690 13150 12640 12150 11680 11230 10800
908 10390 10000 9620 9270 8920 8590 8280 7980
909 7690 7410 7150 6890 6650 6410 6190 5970
910 5770 5570 5380 5190 5020 4850 4680 4530
911 4380 4230 4100 3960 3830 3710 3590 3480
912 3370 3260 3160 3060 2960 2870 2780 2700
913 >;
914 };
915 usb {
916 status = "disabled";
917 vbus_gpio = <0xff>; /* set_vbus */
918 id-gpadc = <0xff>; /* usb-id */
919 vchg-from-exton = <1>;
920 vbus-detect = <1>; /* vbus-irq */
921 get-vbus = <1>; /* get-vbus */
922 };
923 };
924 };
925 };
926 };
927
928 vcc_sdh1: sd-regulator {
929 compatible = "regulator-fixed";
930 pinctrl-names = "default";
931 pinctrl-0 = <&sd_ldo_en>;
932 regulator-name = "SDH1 VCC";
933 regulator-min-microvolt = <3300000>;
934 regulator-max-microvolt = <3300000>;
935 gpio = <&gpio 12 0>;
936 enable-active-high;
937 status = "disabled";
938 };
939
940 asr-rfkill {
941 compatible = "asr,asr-rfkill";
942 pinctrl-names = "off", "on";
943 pinctrl-0 = <&sdh1_pmx_pd_rst_off>;
944 pinctrl-1 = <&sdh1_pmx_pd_rst_on>;
945 sd-host = <&sdh1>;
946 pd-gpio = <&gpio 69 0>;
947 3v3-ldo-gpio = <&gpio 62 0>;
948#if 1
949 edge-wakeup-gpio = <&gpio 70 0>;
950#else/*for aic sdio wifi 8800dw*/
951 host-wakeup-wlan-gpio = <&gpio 62 0>;
952 wlan-wakeup-host-gpio = <&gpio 70 0>;
953#endif
954 status = "okay";
955 };
956
957 pcie-rfkill {
958 compatible = "mrvl,pcie-rfkill";
959 pinctrl-names = "off", "on";
960 pinctrl-0 = <&pcie_pmx_pd_rst_off>;
961 pinctrl-1 = <&pcie_pmx_pd_rst_on>;
962 rst-gpio = <&gpio 80 0>;
963 rst-gpio2 = <&gpio 72 0>;
964 3v3-ldo-gpio = <&gpio 21 0>;
965 3v3-ldo-gpio2 = <&gpio 22 0>;
966 status = "okay";
967 };
968 usim1: usim {
969 compatible = "asr,usim1";
970 pinctrl-names = "default", "sleep";
971 pinctrl-0 = <&usim1_pmx_func>;
972 pinctrl-1 = <&usim1_pmx_func_sleep>;
973 edge_detect_gpio = <8>; /* GPIO8: SIM detect pin */
974 status = "okay";
975 };
976 gpio_keys {
977 compatible = "gpio-keys";
978 #address-cells = <1>;
979 #size-cells = <0>;
980 /* autorepeat; */
981 pinctrl-names = "default";
982 pinctrl-0 = <&gpiokey_pmx_func>;
983 button@1 {
984 label = "qrcode-key";
985 linux,code = <139>; /* KEY_MENU, refer to linux/input.h */
986 /* NOTE:
987 * We use the FORCE DOWNLOAD key to implement the qrcode key in DKB.
988 * Customer SHOULD change it to any other gpios.
989 * Because user may do the misoperation that
990 * powerup with FDL key pressed,
991 * then the borad will enter force download mode.
992 */
993 gpios = <&gpio 9 1>;
994 gpio-key,wakeup;
995 };
996 };
997 sound {
998 compatible = "ASRMICRO,asrmicro-snd-card";
999 ssp-controllers = <&ssp_dai1>;
1000 };
1001 ecall {
1002 compatible = "asr,ecall-event";
1003 pinctrl-names = "default";
1004 pinctrl-0 = <&ecall_pmx_func>;
1005 gpio-auto-ecall = <8>;
1006 gpio-manual-ecall = <9>;
1007 status = "disabled";
1008 };
1009 nz3-slic {
1010 compatible = "mrvl,nz3-slic";
1011 pinctrl-names = "default", "sleep";
1012 pinctrl-0 = <&slic_pmx_func1 &slic_pmx_func2>;
1013 pinctrl-1 = <&slic_pmx_func1_sleep &slic_pmx_func2>;
1014 rst-gpio = <&gpio 23 0>;
1015 edge-wakeup-gpio = <&gpio 24 0>;
1016 vdd-3v3-gpio = <&gpio 126 0>;
1017 status = "disabled";
1018 };
1019 microsemi-slic {
1020 compatible = "mrvl,microsemi-slic";
1021 pinctrl-names = "default", "sleep";
1022 pinctrl-0 = <&slic_pmx_func1>;
1023 pinctrl-1 = <&slic_pmx_func1_sleep>;
1024 edge-wakeup-gpio = <&gpio 24 0>;
1025 vdd-3v3-gpio = <&gpio 126 0>;
1026 status = "disabled";
1027 };
1028 maxlinear-slic {
1029 compatible = "mrvl,maxlinear-slic";
1030 pinctrl-names = "default", "sleep";
1031 pinctrl-0 = <&slic_pmx_func1 &slic_pmx_func2>;
1032 pinctrl-1 = <&slic_pmx_func1_sleep &slic_pmx_func2>;
1033 rst-gpio = <&gpio 23 0>;
1034 edge-wakeup-gpio = <&gpio 24 0>;
1035 vdd-3v3-gpio = <&gpio 126 0>;
1036 status = "disabled";
1037 };
1038};
1039#include "asr_pm802.dtsi"
1040#include "88pm805.dtsi"
1041#include "asr_pm803.dtsi"
1042
1043#ifdef CONFIG_AB_SYSTEM
1044#include "asr1828_ab_flash_layout.dtsi"
1045#else
1046#include "asr1828_flash_layout.dtsi"
1047#endif