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192.168.1.100 / T108 / c2023d5d03be91dbb983606f0ec5e9e4ea36c8c2 / . / marvell / linux / arch / arm / boot / dts / asr1901.dtsi
blob: 59f2cb5c8ea39a7ca038becf6d44b55330baac74 [file] [log] [blame]
b.liue9582032025-04-17 19:18:16 +0800[diff] [blame]1/*
2 * Copyright (C) 2018 ASR Microelectronics Ltd.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * publishhed by the Free Software Foundation.
7 */
8/dts-v1/;
9#include "asr1901-pinfunc.h"
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include <dt-bindings/power/asr-pm.h>
12/* #include <dt-bindings/usb/mv_usb_phy.h> */
13#include <dt-bindings/clock/asr,asr1803.h>
14#include <dt-bindings/clock/timer-mmp.h>
15#include <dt-bindings/mmc/asr_sdhci.h>
16#include <dt-bindings/phy/phy.h>
17#include <generated/autoconf.h>
18
19/ {
20 #address-cells = <1>;
21 #size-cells = <1>;
22
23 interrupt-parent = <&gic>;
24
25 aliases {
26 serial0 = &uart1;
27 serial1 = &uart2;
28 serial2 = &uart3;
29 i2c0 = &twsi0;
30 i2c1 = &twsi1;
31 i2c2 = &twsi2;
32 i2c3 = &twsi3;
33 i2c4 = &twsi4;
34 };
35
36 gic: interrupt-controller@d8002000 {
37 compatible = "arm,cortex-a7-gic";
38 interrupt-controller;
39 #interrupt-cells = <3>;
40 reg = <0xd8001000 0x1000>,
41 <0xd8002000 0x2000>;
42 dist-power-domain = "always-on";
43 cpuif-power-domain = "always-on";
44 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
45 IRQ_TYPE_LEVEL_HIGH)>;
46 };
47
48 clock: clock-controller {
49 compatible = "marvell,asr1901-clock";
50 reg = <0xc0000000 0x880>;
51 reg-names = "dmcu";
52 };
53 soc {
54 #address-cells = <1>;
55 #size-cells = <1>;
56 compatible = "simple-bus";
57 interrupt-parent = <&gic>;
58 ranges;
59 ddr@c0000000 { /* DDR memory controller */
60 compatible = "marvell,devfreq-ddr";
61 reg = <0xc0000000 0x880>,
62 <0xc0058500 0x80>;
63 interrupts = <0 99 0x4>;
64 interrupt-names = "nezas-mc-irq";
65 marvell,qos;
66 status = "okay";
67 };
68
69 pmu {
70 compatible = "arm,cortex-a7-pmu";
71 interrupts = <0 58 0x4>;
72 };
73
74 axi@d4200000 { /* AXI */
75 compatible = "mrvl,axi-bus", "simple-bus";
76 #address-cells = <1>;
77 #size-cells = <1>;
78 reg = <0xd4200000 0x00200000>;
79 ranges;
80
81 intc: interrupt-controller@d4282000 {
82 compatible = "mrvl,mmp-intc";
83 status = "disabled";
84 interrupt-controller;
85 #interrupt-cells = <1>;
86 reg = <0xd4282000 0x1000>;
87 mrvl,intc-nr-irqs = <64>;
88 };
89 usb3phy: usb3phy@c0230000 {
90 compatible = "asr,asr-usb3-phy";
91 reg = <0xc0230000 0x1000>;
92 clocks = <&soc_clocks ASR1803_CLK_USB>;
93 clock-names = "usb_clk";
94 status = "disabled";
95 };
96#ifdef CONFIG_USB_DWC3_ASR_OTG
97 usb3_1_otg: usb3-1-otg {
98 compatible = "asr,dwc3";
99 status = "disabled";
100 #address-cells = <1>;
101 #size-cells = <1>;
102 ranges;
103 interrupts = <0 89 0x4>;
104 lpm-qos = <PM_QOS_CPUIDLE_BLOCK_AXI>;
105 pinctrl-names = "default";
106 pinctrl-0 = <&usb_vbus_pinmux &usb_typec_pinmux>;
107 clocks = <&soc_clocks ASR1803_CLK_USB>;
108 clock-names = "usb_clk";
109 usb_dwc3_1: dwc31@c0200000 {
110 compatible = "snps,dwc3";
111 reg = <0xc0200000 0x30000>;
112 interrupts = <0 106 0x4
113 0 106 0x4
114 0 106 0x4>;
115 interrupt-names = "peripheral",
116 "host",
117 "otg";
118 usb-phy = <&usb3phy>;
119 maximum-speed = "super-speed-plus";
120 dr_mode = "otg";
121 phy_type = "utmi";
122 lpm-qos = <PM_QOS_CPUIDLE_BLOCK_AXI>;
123 snps,dis_u3_susphy_quirk;
124 snps,dis_enblslpm_quirk;
125 snps,dis_u2_susphy_quirk;
126 snps,parkmode-disable-ss-quirk;
127 /* allow-suspend; */
128 status = "okay";
129 };
130 };
131#else
132 usb3_1: usb3-1 {
133 compatible = "asr,dwc3";
134 status = "disabled";
135 #address-cells = <1>;
136 #size-cells = <1>;
137 ranges;
138 interrupts = <0 89 0x4>;
139 pinctrl-names = "default";
140 pinctrl-0 = <&usb_vbus_pinmux &usb_typec_pinmux>;
141 clocks = <&soc_clocks ASR1803_CLK_USB>;
142 clock-names = "usb_clk";
143 usb_dwc3_1: dwc31@c0200000 {
144 compatible = "snps,dwc3";
145 reg = <0xc0200000 0x30000>;
146 interrupts = <0 106 0x4>;
147 usb-phy = <&usb3phy>;
148 maximum-speed = "super-speed-plus";
149 dr_mode = "peripheral";
150 phy_type = "utmi";
151 lpm-qos = <PM_QOS_CPUIDLE_BLOCK_AXI>;
152 snps,dis_u3_susphy_quirk;
153 /* allow-suspend; */
154 status = "okay";
155 };
156 };
157#endif
158 sdh0: sdh@d4280000 {
159 compatible = "asr,sdhci";
160 reg = <0xd4280000 0x200>;
161 interrupts = <0 83 0x4>;
162 clocks = <&soc_clocks ASR1803_CLK_SDH0
163 &soc_clocks ASR1803_CLK_SDH_AXI
164 &soc_clocks ASR1803_CLK_SDH0_TUNE
165 >;
166 clock-names = "sdh-io", "sdh-core", "sdh-fclk-tuned";
167 lpm-qos = <PM_QOS_CPUIDLE_BLOCK_AXI>;
168 status = "disabled";
169 };
170 sdh1: sdh@d4280800 {
171 compatible = "asr,sdhci";
172 reg = <0xd4280800 0x200>;
173 interrupts = <0 84 0x4>;
174 clocks = <&soc_clocks ASR1803_CLK_SDH1
175 &soc_clocks ASR1803_CLK_SDH_AXI
176 &soc_clocks ASR1803_CLK_SDH1_TUNE
177 >;
178 clock-names = "sdh-io", "sdh-core", "sdh-fclk-tuned";
179 lpm-qos = <PM_QOS_CPUIDLE_BLOCK_AXI>;
180 status = "disabled";
181 };
182 toe: asr-toe@0xd4208000 {
183 compatible = "asr,asr-toe";
184 reg = <0xc0900000 0x45c>;
185 interrupts = <0 108 0x4>,
186 <0 109 0x4>,
187 <0 3 0x4>,
188 <0 101 0x4>;
189
190 status = "okay";
191 };
192
193 ssp1: spi@d42a0c00 {
194 compatible = "asr,asr-spi";
195 #address-cells = <1>;
196 #size-cells = <0>;
197 reg = <0xd42a0c00 0x30>;
198 asr,ssp-lpm-qos = <PM_QOS_CPUIDLE_BLOCK_AXI>;
199 asr,ssp-clock-rate = <13000000>;
200 asr,ssp-id = <2>;
201 interrupts = <0 49 0x4>;
202 asr,ssp-enhancement;
203 asr,ssp-disable-dma; /* squ dma */
204 /* asr,ssp-slave-mode; */
205 /* asr,slave-rxtimer-to-ms = <0>; */
206 /* asr,ssp-hold-frame-low; */
207 /* asr,spi-master-rxto = <8000>; */
208 /* asr,spi-slave-rxto = <262144>; */
209 /* asr,spi-pio-interval = <5>; */
210 /* asr,spi-1-cycle-delay; */
211 clocks = <&soc_clocks ASR1803_CLK_SSP1>;
212 status = "disabled";
213 };
214
215 sram: squ@d1000000 {
216 compatible = "mmio-sram";
217 #address-cells = <1>;
218 #size-cells = <1>;
219 no-memory-wc;
220 reg = <0xd1000000 0x20000>;
221 ranges;
222
223 /* Add reserved area below */
224 sram@d100ff00 {
225 /* reserved for obm special flags */
226 reg = <0xd100ff00 0x100>;
227 };
228
229 sram@d101c000 {
230 /* reserved for audio debug */
231 reg = <0xd101c000 0x4000>;
232 };
233 };
234
235 qspi: spi@0xd420b000 {
236 #address-cells = <1>;
237 #size-cells = <0>;
238 compatible = "asr,qspi";
239 reg = <0xd420b000 0x1000>, <0x80000000 0x8000000>;
240 reg-names = "qspi-base", "qspi-mmap";
241 asr,qspi-sfa1ad = <0x8000000>;
242 asr,qspi-sfa2ad = <0x8000000>;
243 asr,qspi-sfb1ad = <0x8000000>;
244 asr,qspi-sfb2ad = <0x8000000>;
245 clocks = <&soc_clocks ASR1803_CLK_QSPI
246 &soc_clocks ASR1803_CLK_QSPI_BUS>;
247 clock-names = "qspi_clk", "qspi_bus_clk";
248 asr,qspi-pmuap-reg = <0xd4282860>;
249 /* asr,qspi-id = <0>; */
250 asr,qspi-lpm-qos = <PM_QOS_CPUIDLE_BLOCK_AXI>;
251 interrupts = <0 110 4>;
252 dmas = <&pdma0 45 0xf00>;
253 dma-names = "tx-dma";
254 asr,qspi-sram = <&sram>;
255 status = "disabled";
256 };
257 debug: debug@d4282c00 {
258 compatible = "mrvl,mmp-debug";
259 reg = <0xd4282c00 0x800>;
260 };
261 geu: geu {
262 compatible = "asr,asr-geu";
263 reg = <0xD4292800 0x1000>;
264 interrupts = <0 91 0x4>;
265 asr,asr-fuse;
266 asr,aes-int-mode;
267 dmas = <&pdma0 68 1
268 &pdma0 69 1>;
269 dma-names = "tx", "rx";
270 clocks = <&soc_clocks ASR1803_CLK_GEU>;
271 lpm-qos = <PM_QOS_CPUIDLE_BLOCK_AXI>;
272 status = "okay";
273 };
274 bcm: bcm {
275 compatible = "asr,asr-bcm";
276 reg = <0xD4290000 0x2800>;
277 asr,asr-cipher;
278 asr,asr-sha;
279 interrupts = <0 91 0x4>;
280 clocks = <&soc_clocks ASR1803_CLK_GEU>;
281 lpm-qos = <PM_QOS_CPUIDLE_BLOCK_AXI>;
282 status = "okay";
283 };
284 rng: rng {
285 compatible = "asr,asr-hwrng";
286 reg = <0xD4293800 0x100>;
287 clocks = <&soc_clocks ASR1803_CLK_GEU>;
288 lpm-qos = <PM_QOS_CPUIDLE_BLOCK_AXI>;
289 status = "okay";
290 };
291 pcie0: pcie@d4c00000 {
292 compatible = "asr,kst-pcie", "snps,dw-pcie";
293 device_type = "pci";
294 #address-cells = <3>;
295 #size-cells = <2>;
296 bus-range = <0x00 0xff>;
297 linux,pci-domain = <0>;
298 reg = <0xd4c00000 0x400000>, /* Kestrel PCIe dbi registers */
299 <0xc0410000 0x80000>, /* Kestrel PCIe PHY registers */
300 <0xd4c00000 0x400000>,
301 <0xc0230400 0x10000>; /* eanble usb3-phy if USB is disable */
302 reg-names = "pcie-dbi", "pcie-phy", "config", "usb3-phy";
303 ranges = <0x00000800 0 0xE0020000 0xE0020000 0 0x00001000 /* configuration space */
304 0x81000000 0 0 0xE0010000 0 0x00010000 /* downstream I/O */
305 0x82000000 0 0xE8200000 0xE8200000 0 0x04000000>; /* non-prefetchable memory */
306 lpm-qos = <PM_QOS_CPUIDLE_BLOCK_AXI>;
307 num-lanes = <1>;
308 num-slot = <0>;
309 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
310 interrupt-names = "msi";
311 #interrupt-cells = <1>;
312 interrupt-parent = <&gic>;
313 interrupt-map-mask = <0 0 0 0>;
314 interrupt-map = <0 0 0 0 &gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
315 clocks = <&soc_clocks ASR1803_CLK_PCIE0>;
316 status = "disabled";
317 };
318 pcie1: pcie@0xd4800000{
319 compatible = "asr,kst-pcie", "snps,dw-pcie";
320 device_type = "pci";
321 #address-cells = <3>;
322 #size-cells = <2>;
323 bus-range = <0x00 0xff>;
324 linux,pci-domain = <1>;
325 reg = <0xd4800000 0x400000>, /* Kestrel PCIe dbi registers */
326 <0xc0510000 0x80000>, /* Kestrel PCIe PHY registers */
327 <0xc0230400 0x10000>,
328 <0xd4800000 0x400000>;
329 reg-names = "pcie-dbi", "pcie-phy", "usb3-phy", "config";
330 ranges = <0x00000800 0 0xB8020000 0xB8020000 0 0x00001000 /* configuration space */
331 0x81000000 0 0 0xB8010000 0 0x00010000 /* downstream I/O */
332 0x82000000 0 0xB8200000 0xB8200000 0 0x04000000>; /* non-prefetchable memory */
333 lpm-qos = <PM_QOS_CPUIDLE_BLOCK_AXI>;
334 num-lanes = <1>;
335 num-slot = <1>;
336 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
337 interrupt-names = "msi";
338 #interrupt-cells = <1>;
339 interrupt-parent = <&gic>;
340 interrupt-map-mask = <0 0 0 0>;
341 interrupt-map = <0 0 0 0 &gic GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
342 clocks = <&soc_clocks ASR1803_CLK_PCIE1>;
343 status = "disabled";
344 };
345
346 xgmacphy: xgmac-phy@c0100000 {
347 compatible = "syscon";
348 reg = <0xc0100000 0x2000>;
349 };
350
351 xgmac: ethernet@d4270000 {
352 compatible = "asr,dwc-xgmac", "snps,dwxgmac";
353 reg = <0xd4270000 0x8000>;
354 reg-names = "asrmaceth";
355 interrupts = <0 111 0x4
356 0 112 0x4>;
357 interrupt-names = "macirq", "eth_wake_irq";
358 status = "disabled";
359
360 clock-names = "xgmac-clk";
361 clocks = <&soc_clocks ASR1901_CLK_XGMAC>;
362 lpm-qos = <PM_QOS_CPUIDLE_BLOCK_AXI>;
363 xgmac,phy = <&xgmacphy 0x4>;
364 snps,pbl = <8>;
365 snps,txpbl = <32>;
366 snps,rxpbl = <32>;
367 snps,no-pbl-x8;
368 snps,mixed-burst;
369 snps,ps-speed = <1000>;
370 snps,tso;
371 snps,aal;
372 snps,force_sf_dma_mode;
373 max-speed = <5000>;
374 clk_csr = <5>;
375
376 snps,axi-config = <&xgmac_axi_setup>;
377 snps,mtl-rx-config = <&mtl_rx_setup>;
378 snps,mtl-tx-config = <&mtl_tx_setup>;
379
380 xgmac_axi_setup: snps-axi-config {
381 snps,blen = <4 8 16 0 0 0 0>;
382 };
383
384 mtl_rx_setup: snps-mtl-rx-config {
385 snps,rx-sched-sp;
386 snps,rx-queues-to-use = <2>;
387 queue0 {
388 snps,dcb-algorithm;
389 /* snps,map-to-dma-channel = <2>; */
390 };
391 queue1 {
392 snps,dcb-algorithm;
393 /* snps,map-to-dma-channel = <2>; */
394 };
395 };
396 mtl_tx_setup: snps-mtl-tx-config {
397 snps,tx-sched-wrr;
398 snps,tx-queues-to-use = <2>;
399 queue0 {
400 snps,dcb-algorithm;
401 };
402 queue1 {
403 snps,dcb-algorithm;
404 };
405 };
406 };
407
408 hsdma0: hsdma@d4209000 {
409 compatible = "asr,hsdma-1.0";
410 reg = <0xd4209000 0x1000>;
411 interrupts = <0 118 0x4>;
412 #dma-cells = <1>;
413 #dma-channels = <8>;
414 status = "disabled";
415 };
416 };
417
418 apb@d4000000 { /* APB */
419 compatible = "mrvl,apb-bus", "simple-bus";
420 #address-cells = <1>;
421 #size-cells = <1>;
422 reg = <0xd4000000 0x00200000>;
423 ranges;
424
425 pdma0: pdma@d4000000 {
426 compatible = "asr,pdma-1.0";
427 reg = <0xd4000000 0x10000>;
428 interrupts = <0 56 0x4>;
429 #dma-cells= <2>;
430 #dma-channels = <32>;
431 #dma-channels-tz = <30>;
432 #dma-channels-dedicated = <0x8000>;
433 #dma-channels-tz-reserved = <0x00006000>;
434 lpm-qos = <PM_QOS_CPUIDLE_BLOCK_AXI>;
435 status = "okay";
436 };
437
438 thermal: thermal@d4013300 {
439 compatible = "asr,asr1901-thermal";
440 reg = <0xd4013300 0x74>;
441 interrupts = <0 40 0x4>;
442 clocks = <&soc_clocks ASR1803_CLK_TSEN>;
443 clock-names = "tsen_clk";
444 status = "okay";
445 };
446
447 timer0: timer@d4014000 {
448 compatible = "mrvl,mmp-timer";
449 reg = <0xd4014000 0xD0>;
450 marvell,timer-id = <0>;
451 marvell,timer-flag = <0>;
452 marvell,timer-fastclk-frequency = <3250000>;
453 marvell,timer-apb-frequency = <38400000>;
454 clocks = <&soc_clocks ASR1803_CLK_TIMER0>;
455
456 counter0 {
457 interrupts = <0 7 0x4>;
458 marvell,timer-counter-id = <0>;
459 marvell,timer-counter-cpu = <0>;
460 marvell,timer-counter-frequency = <32768>;
461 marvell,timer-counter-usage = <MMP_TIMER_COUNTER_CLKEVT>;
462 marvell,timer-counter-rating = <200>;
463 };
464
465 counter1 {
466 interrupts = <0 8 0x4>;
467 marvell,timer-counter-id = <1>;
468 marvell,timer-counter-frequency = <32768>;
469 marvell,timer-counter-usage = <MMP_TIMER_COUNTER_CLKSRC>;
470 marvell,timer-counter-rating = <200>;
471 };
472
473 counter2 {
474 interrupts = <0 9 0x4>;
475 marvell,timer-counter-id = <2>;
476 marvell,timer-counter-frequency = <3250000>;
477 marvell,timer-counter-usage = <MMP_TIMER_COUNTER_DELAY>;
478 };
479 };
480 timer1: timer@d401f000 {
481 compatible = "mrvl,mmp-timer";
482 reg = <0xd401f000 0xD0>;
483 marvell,timer-id = <1>;
484 marvell,timer-flag = <0>;
485 marvell,timer-fastclk-frequency = <3250000>;
486 marvell,timer-apb-frequency = <38400000>;
487 clocks = <&soc_clocks ASR1803_CLK_TIMER2>;
488
489 counter0 {
490 interrupts = <0 13 0x4>;
491 marvell,timer-counter-id = <0>;
492 marvell,timer-counter-cpu = <1>;
493 marvell,timer-counter-frequency = <32768>;
494 marvell,timer-counter-usage = <MMP_TIMER_COUNTER_CLKEVT>;
495 marvell,timer-counter-rating = <200>;
496 };
497
498 counter1 {
499 interrupts = <0 14 0x4>;
500 marvell,timer-counter-id = <1>;
501 marvell,timer-counter-cpu = <2>;
502 marvell,timer-counter-frequency = <32768>;
503 marvell,timer-counter-usage = <MMP_TIMER_COUNTER_CLKEVT>;
504 marvell,timer-counter-rating = <200>;
505 };
506
507 counter2 {
508 interrupts = <0 15 0x4>;
509 marvell,timer-counter-id = <2>;
510 marvell,timer-counter-cpu = <3>;
511 marvell,timer-counter-frequency = <32768>;
512 marvell,timer-counter-usage = <MMP_TIMER_COUNTER_CLKEVT>;
513 marvell,timer-counter-rating = <200>;
514 };
515 };
516
517
518 uart1: uart@d4017000 {
519 compatible = "asr,mmp-uart";
520 reg = <0xd4017000 0x100>;
521 interrupts = <0 32 0x4>;
522 uart-drcmr-rx = <3>;
523 uart-drcmr-tx = <4>;
524 dmas = <&pdma0 3 1
525 &pdma0 4 1>;
526 dma-names = "rx", "tx";
527 lpm-qos = <PM_QOS_CPUIDLE_BLOCK_AXI>;
528 clocks = <&soc_clocks ASR1803_CLK_UART0>;
529 resets = <&soc_clocks ASR1803_CLK_UART0>;
530 status = "disabled";
531 };
532
533 uart2: uart@d4018000 {
534 compatible = "asr,mmp-uart";
535 reg = <0xd4018000 0x1000>;
536 interrupts = <0 33 0x4>;
537 uart-drcmr-rx = <5>;
538 uart-drcmr-tx = <6>;
539 dmas = <&pdma0 5 1
540 &pdma0 6 1>;
541 dma-names = "rx", "tx";
542 clocks = <&soc_clocks ASR1803_CLK_UART1>;
543 resets = <&soc_clocks ASR1803_CLK_UART1>;
544 lpm-qos = <PM_QOS_CPUIDLE_BLOCK_AXI>;
545 status = "disabled";
546 };
547
548 uart3: uart@d4017800 {
549 compatible = "asr,mmp-uart";
550 reg = <0xd4017800 0x1000>;
551 interrupts = <0 34 0x4>;
552 uart-drcmr-rx = <19>;
553 uart-drcmr-tx = <20>;
554 dmas = <&pdma0 19 1
555 &pdma0 20 1>;
556 dma-names = "rx", "tx";
557 clocks = <&soc_clocks ASR1803_CLK_UART2>;
558 resets = <&soc_clocks ASR1803_CLK_UART2>;
559 lpm-qos = <PM_QOS_CPUIDLE_BLOCK_AXI>;
560 status = "disabled";
561 };
562
563 gpio: gpio@d4019000 {
564 compatible = "marvell,mmp-gpio";
565 #address-cells = <1>;
566 #size-cells = <1>;
567 reg = <0xd4019000 0x800>;
568 gpio-controller;
569 #gpio-cells = <2>;
570 interrupts = <0 37 0x4>;
571 interrupt-controller;
572 #interrupt-cells = <2>;
573 interrupt-names = "gpio_mux";
574 clocks = <&soc_clocks ASR1803_CLK_GPIO>;
575 resets = <&soc_clocks ASR1803_CLK_GPIO>;
576 status = "okay";
577 gpio-ranges = <&pmx 0 55 32>, <&pmx 0 87 23>,
578 <&pmx 3 110 29>, <&pmx 0 139 3 >,
579 <&pmx 28 51 3>;
580 };
581
582 mfpr: mfpr@d401e000 {
583 compatible = "asr,mfp-leftover";
584 reg = <0xd401e000 0x280>;
585 status = "disabled";
586 };
587
588 edgewakeup: edgewakeup@d4019800 {
589 compatible = "asr,edge-wakeup";
590 reg = <0xd4019800 0x10>,
591 <0xd401e000 0x400>;
592 interrupts = <0 39 0x4>;
593 status = "okay";
594 };
595
596 twsi0: i2c@d4011000 {
597 compatible = "mrvl,mmp-twsi";
598 #address-cells = <1>;
599 #size-cells = <0>;
600 reg = <0xd4011000 0x60>,
601 <0xd40b0300 0x10>;
602 interrupts = <0 20 0x4>;
603 lpm-qos = <PM_QOS_CPUIDLE_BLOCK_DDR>;
604 mrvl,i2c-fast-mode;
605 /*
606 *ilcr: fast mode b17~9=0x23, 390k
607 * standard mode b8~0=0x9f, 97k
608 *iwcr: b5~0=b01010 recommended value from spec
609 */
610 marvell,i2c-ilcr = <0x82c469f>;
611 marvell,i2c-iwcr = <0x1434>;
612 pinctrl-names = "default","gpio";
613 pinctrl-0 = <&twsi0_pmx_func>;
614 pinctrl-1 = <&twsi0_pmx_gpio>;
615 soc-bus-reset;
616 clocks = <&soc_clocks ASR1803_CLK_TWSI0>;
617 clock-names = "twsi0_clk";
618 status = "disabled";
619 };
620 twsi1: i2c@d4010800 {
621 compatible = "mrvl,mmp-twsi";
622 #address-cells = <1>;
623 #size-cells = <0>;
624 reg = <0xd4010800 0x60>;
625 interrupts = <0 21 0x4>;
626 lpm-qos = <PM_QOS_CPUIDLE_BLOCK_DDR>;
627 mrvl,i2c-fast-mode;
628 marvell,i2c-ilcr = <0x82c469f>;
629 marvell,i2c-iwcr = <0x1434>;
630 pinctrl-names = "default","gpio";
631 pinctrl-0 = <&twsi1_pmx_func>;
632 pinctrl-1 = <&twsi1_pmx_gpio>;
633 soc-bus-reset;
634 clocks = <&soc_clocks ASR1803_CLK_TWSI1>;
635 clock-names = "twsi1_clk";
636 status = "disabled";
637 };
638 twsi2: i2c@d4013800 {
639 compatible = "mrvl,mmp-twsi";
640 #address-cells = <1>;
641 #size-cells = <0>;
642 reg = <0xd4013800 0x60>;
643 interrupts = <0 22 0x4>;
644 lpm-qos = <PM_QOS_CPUIDLE_BLOCK_DDR>;
645 mrvl,i2c-fast-mode;
646 marvell,i2c-ilcr = <0x82c469f>;
647 marvell,i2c-iwcr = <0x1434>;
648 pinctrl-names = "default","gpio";
649 pinctrl-0 = <&twsi2_pmx_func>;
650 pinctrl-1 = <&twsi2_pmx_gpio>;
651 soc-bus-reset;
652 clocks = <&soc_clocks ASR1803_CLK_TWSI2>;
653 clock-names = "twsi2_clk";
654 status = "disabled";
655 };
656 twsi3: i2c@d4018800 {
657 compatible = "mrvl,mmp-twsi";
658 #address-cells = <1>;
659 #size-cells = <0>;
660 reg = <0xd4018800 0x60>,
661 <0xd40b0300 0x10>;
662 interrupts = <0 23 0x4>;
663 lpm-qos = <PM_QOS_CPUIDLE_BLOCK_DDR>;
664 marvell,i2c-always-on;
665 mrvl,i2c-fast-mode;
666 marvell,i2c-ilcr = <0x82c469f>;
667 marvell,i2c-iwcr = <0x1434>;
668 soc-bus-reset;
669 clocks = <&soc_clocks ASR1803_CLK_TWSI3>;
670 clock-names = "twsi3_clk";
671 status = "disabled";
672 };
673 twsi4: i2c@d4020000 {
674 compatible = "mrvl,mmp-twsi";
675 #address-cells = <1>;
676 #size-cells = <0>;
677 reg = <0xd4020000 0x60>;
678 interrupts = <0 24 0x4>;
679 lpm-qos = <PM_QOS_CPUIDLE_BLOCK_DDR>;
680 mrvl,i2c-fast-mode;
681 marvell,i2c-ilcr = <0x82c469f>;
682 marvell,i2c-iwcr = <0x1434>;
683 pinctrl-names = "default","gpio";
684 pinctrl-0 = <&twsi4_pmx_func>;
685 pinctrl-1 = <&twsi4_pmx_gpio>;
686 i2c-gpio = <&gpio 35 0 &gpio 36 0>;
687 clocks = <&soc_clocks ASR1803_CLK_TWSI4>;
688 clock-names = "twsi4_clk";
689 status = "disabled";
690 };
691
692 ssp0: spi@d401b000 {
693 compatible = "asr,asr-spi";
694 #address-cells = <1>;
695 #size-cells = <0>;
696 reg = <0xd401b000 0x30>;
697
698 /* DMA: change 0x10000 to 0x0 in SPI slave mode */
699 dmas = <&pdma0 9 0x10000
700 &pdma0 10 0x10000>;
701 dma-names = "rx", "tx";
702
703 asr,ssp-lpm-qos = <PM_QOS_CPUIDLE_BLOCK_AXI>;
704 asr,ssp-clock-rate = <13000000>;
705 asr,ssp-id = <1>;
706 interrupts = <0 35 0x4>;
707 asr,ssp-enhancement;
708 asr,ssp-disable-dma;
709 /* asr,ssp-slave-mode; */
710 /* asr,slave-rxtimer-to-ms = <0>; */
711 /* asr,ssp-hold-frame-low; */
712 /* asr,spi-master-rxto = <8000>; */
713 /* asr,spi-slave-rxto = <262144>; */
714 /* asr,spi-pio-interval = <5>; */
715 /* asr,spi-1-cycle-delay; */
716 /* asr,spi-cs-comb-ctrl; */
717 clocks = <&soc_clocks ASR1803_CLK_SSP0>;
718 status = "disabled";
719 };
720
721 ssp2: spi@d401c000 {
722 compatible = "asr,asr-spi";
723 #address-cells = <1>;
724 #size-cells = <0>;
725 reg = <0xd401c000 0x30>;
726
727 /* DMA: change 0x10000 to 0x0 in SPI slave mode */
728 dmas = <&pdma0 11 0x10000
729 &pdma0 12 0x10000>;
730 dma-names = "rx", "tx";
731
732 asr,ssp-lpm-qos = <PM_QOS_CPUIDLE_BLOCK_AXI>;
733 asr,ssp-clock-rate = <13000000>;
734 asr,ssp-id = <3>;
735 interrupts = <0 36 0x4>;
736 asr,ssp-enhancement;
737 /* asr,ssp-disable-dma; */
738 /* asr,ssp-slave-mode; */
739 /* asr,slave-rxtimer-to-ms = <0>; */
740 /* asr,ssp-hold-frame-low; */
741 /* asr,spi-master-rxto = <8000>; */
742 /* asr,spi-slave-rxto = <262144>; */
743 /* asr,spi-pio-interval = <5>; */
744 /* asr,spi-1-cycle-delay; */
745 clocks = <&soc_clocks ASR1803_CLK_SSP2>;
746 status = "disabled";
747 };
748
749 rtc: rtc@d4010000 {
750 compatible = "mrvl,mmp-rtc";
751 reg = <0xd4010000 0x100>;
752 interrupts = <0 5 0x4
753 0 6 0x4>;
754 interrupt-names = "rtc 1Hz", "rtc alarm";
755 clocks = <&soc_clocks ASR1803_CLK_RTC>;
756 resets = <&soc_clocks ASR1803_CLK_RTC>;
757 status = "disabled";
758 };
759
760 pmx: pinmux@d401e000 {
761 compatible = "pinconf-single";
762 reg = <0xd401e000 0x330>;
763 #address-cells = <1>;
764 #size-cells = <1>;
765 #pinctrl-cells = <1>;
766 #gpio-range-cells = <3>;
767 ranges;
768
769 pinctrl-single,register-width = <32>;
770 pinctrl-single,function-mask = <7>;
771
772 range: gpio-range {
773 #pinctrl-single,gpio-range-cells = <3>;
774 };
775 };
776
777 acipc: acipc@d401d000 {
778 compatible = "mrvl,mmp-acipc";
779 reg = <0xD401d000 0x100>;
780 interrupts = <0 29 0x4>;
781 interrupt-names = "IPC_AP_MUX";
782 status = "okay";
783 };
784 auxadc: auxadc@d4013400 {
785 compatible = "asr,auxadc";
786 reg = <0xd4013400 0x80>;
787 clocks = <&soc_clocks ASR1803_CLK_AUXADC>;
788 clock-names = "auxadc_clk";
789 status = "okay";
790 };
791
792 adsp: adsp@d401d100 {
793 compatible = "asr,adsp";
794 reg = <0xd101c000 0x4000>,
795 <0xd6000000 0x40000>,
796 <0xd6a00000 0x4000>,
797 <0xd6200000 0x10000>,
798 <0xd401d100 0x20>,
799 <0xd401e178 0x10>,
800 <0xd6800014 0x4>,
801 <0xd6800048 0x4>,
802 <0xd4015090 0x4>,
803 <0xd42828f0 0x4>,
804 <0xd428294c 0x4>;
805 interrupts = <0 30 0x4>;
806 interrupt-names = "ipc_adsp2ap_int";
807 status = "okay";
808 };
809
810 seh {
811 compatible = "mrvl,seh";
812 /* use CP TIMER for watchdog to notify cp assert */
813 reg = <0xffffffff 0xff>, <0xd40B0300 0x4>;
814 interrupts = <0 0 0x4>;
815 interrupt-names = "CP_TIMER3";
816 watchdog-type = <2>; /* wdt CP timer3 */
817 status = "okay";
818 };
819
820 sulog: ripc1@d40b0100 {
821 compatible = "mrvl,mmp-sulog";
822 #address-cells = <1>;
823 #size-cells = <0>;
824 reg = <0xd40b0100 0x20> ,
825 <0xd4050210 0x4>;
826 interrupts = <0 31 0x4>;
827 interrupt-names = "RIPC1_INT";
828 status = "disabled";
829 };
830
831 cp-load {
832 compatible = "marvell,cp_load";
833 cp-type = <0x30393838>; /* NZ_MODEM */
834 lpm-qos = <PM_QOS_CPUIDLE_BLOCK_AXI>;
835 status = "okay";
836 };
837
838 data-path {
839 compatible = "marvell,data-path";
840 version = <3>;
841 status = "okay";
842 };
843 };
844
845 soc_clocks: clocks{
846 compatible = "asr,asr1803-clock";
847 reg = <0xd4050000 0x3000>,
848 <0xd4282800 0x400>,
849 <0xd4015000 0x1000>,
850 <0xd4090000 0x1000>,
851 <0xd4282c00 0x400>,
852 <0xc0100000 0x5000>;
853 reg-names = "mpmu", "apmu", "apbc", "apbs", "ciu", "ddrc";
854 #clock-cells = <1>;
855 #reset-cells = <1>;
856 };
857 };
858
859 shared-timer {
860 compatible = "marvell,timer1";
861 dev_name = "timer1_TS";
862 version = "build1";
863 reg = <0xD4016000 0xD0>;
864 status = "okay";
865 };
866
867 mmplog {
868 compatible = "marvell,mmplog-heap";
869 mmplog-base = <0x01f00000>;
870 mmplog-size = <0x8000>;
871 status = "okay";
872 };
873
874 regs_addr_ioremap {
875 #address-cells = <1>;
876 #size-cells = <1>;
877 ranges;
878
879 mpmu: pmu@d4050000 {
880 compatible = "marvell,mmp-pmu-mpmu";
881 reg = <0xd4050000 0x2000>;
882 };
883 apmu: pmu@d4282800 {
884 compatible = "marvell,mmp-pmu-apmu";
885 reg = <0xd4282800 0x400>;
886 };
887 apbc: pmu@d4015000 {
888 compatible = "marvell,mmp-pmu-apbc";
889 reg = <0xd4015000 0x100>;
890 };
891 apbs: pmu@d4090000 {
892 compatible = "marvell,mmp-apb-spare";
893 reg = <0xd4090000 0x200>;
894 };
895 ciu: ciu@d4282c00 {
896 compatible = "marvell,mmp-ciu";
897 reg = <0xd4282c00 0x300>;
898 };
899 squ: squ@0xd42a0000 {
900 compatible = "marvell,mmp-squ";
901 reg = <0xd42a0000 0x800>;
902 };
903 mcu: mcu@0xc0100000 {
904 compatible = "marvell,mmp-mcu";
905 reg = <0xc0100000 0x5000>;
906 };
907 };
908 profile {
909 compatible = "marvell,profile";
910 marvell,profile-number = <0>;
911 };
912
913};
914
915#ifdef CONFIG_OPTEE
916#include "asr1901_tee.dtsi"
917#endif