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192.168.1.100 / T108 / c2023d5d03be91dbb983606f0ec5e9e4ea36c8c2 / . / marvell / linux / arch / arm / boot / dts / asr1903-p501-emac-pps.dts
blob: 7976f6ef1b3e45f5d0c3e2601c6615bdfe7ca5f6 [file] [log] [blame]
b.liue9582032025-04-17 19:18:16 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2023 ASR Microelectronics
4 */
5
6/dts-v1/;
7#include "asr1903.dtsi"
8
9#ifdef CONFIG_FB_ASR
10/* #define CONFIG_FB_ASR_MIPI_CMD 1 */
11#endif
12
13/ {
14 model = "ASR 1903(LAPWING) EVB Board";
15 compatible = "asr,1803-evb", "asr,1803";
16
17 chosen {
18 bootargs = "root=/dev/mtdblock5 rootfstype=squashfs init=/etc/preinit noinitrd console=ttyS0,115200 mem=128M";
19 };
20
21 memory {
22 reg = <0x00000000 0x10000000>;
23 };
24
25 firmware {
26 optee {
27 compatible = "linaro,optee-tz";
28 method = "smc";
29 };
30 };
31
32 soc {
33 axi@d4200000 { /* AXI */
34#ifdef CONFIG_FB_ASR
35 lcd: lcd@d420a000 {
36 compatible = "asr,fb";
37 pinctrl-names = "default";
38 pinctrl-0 = <&lcd_pmx_func>;
39 interrupts = <42>;
40 lpm-qos = <PM_QOS_CPUIDLE_BLOCK_AXI>;
41 reg = <0xd420a000 0x800>;
42 #ifdef CONFIG_FB_ASR_MIPI
43 dsi_base = <0xd420a800>;
44 #ifdef CONFIG_FB_ASR_MIPI_CMD
45 panel_type = <1>; /* cmd */
46 #else
47 panel_type = <0>; /* video */
48 #endif
49
50 gpio_ctrl = <0>;
51
52 #ifdef CONFIG_FB_ASR_MIPI_CMD
53 power_gpio = <&gpio 127 0>;
54 #endif
55 #endif
56 reset_gpio = <&gpio 82 0>;
57 vsync_gpio = <&gpio 81 0>;
58 //avdd-supply = <&ldo1>;
59 status = "okay";
60 };
61
62 backlight: pwm_bl {
63 compatible = "pwm-backlight";
64 pwms = <&pwm2 50000>;
65 brightness-levels = <0 4 8 16 32 64 128 255>;
66 default-brightness-level = <6>;
67 #ifdef CONFIG_FB_ASR_MIPI_CMD
68 status = "disabled";
69 #else
70 status = "okay";
71 #endif
72 };
73#endif
74
75 usb3phy: usb3phy@c0030000 {
76 status = "okay";
77 };
78#ifndef CONFIG_USB_DWC3_ASR_OTG
79 usb3_0: usb3-0 {
80 status = "okay";
81 };
82#else
83 usb3_0_otg: usb3-0-otg {
84 pinctrl-names = "default","sleep";
85 pinctrl-0 = <&usb_id_pinmux &usb_host_pinmux>;
86 pinctrl-1 = <&usb_id_pinmux_slp &usb_host_pinmux>;
87 usbid_gpio = <99>;
88 edge_detect_gpio = <99>;
89 otg,use-gpio-vbus;
90 gpio-num = <122>;
91 status = "okay";
92 };
93#endif
94 eth0: asr-eth@0xd428c000 {
95 compatible = "asr,asr-eth-v3";
96 pinctrl-names = "default", "rgmii-pins";
97 pinctrl-0 = <&emac_pmx_func0 &emac_pmx_func2 &emac_pmx_func3>;
98 pinctrl-1 = <&emac_pmx_func0 &emac_pmx_func1 &emac_pmx_func2 &emac_pmx_func3>;
99 reg = <0xd428c000 0x200>;
100 interrupts = <16 17 61>;
101 lpm-qos = <PM_QOS_CPUIDLE_BLOCK_AXI>;
102 clocks = <&soc_clocks ASR1803_CLK_EMAC
103 &soc_clocks ASR1803_CLK_EMAC_PTP>;
104 clock-names = "emac-clk", "ptp-clk";
105 ptp-support;
106 ptp-clk-rate = <38400000>;
107 pps_source = <1>; /* 0 - bocde, 1 -GNSS */
108#if defined(CONFIG_FB_ASR_SPI) || defined(CONFIG_FB_ASR_MCU)
109 status = "disabled";
110#else
111 status = "okay";
112#endif
113 reset-gpio = <&gpio 20 0>;
114 reset-active-low;
115
116 reset-delays-us = <0 100000 100000>;
117
118 clk-tuning-enable;
119 /* clk-config(32bit)
120 *
121 * rmii_ref_clk(clk-config[31:24])
122 * 0 - from SOC
123 * 1 - from phy
124 * clk_sel(clk-config[23:16])
125 * RGMII:
126 * tx | clk_sel: 0 - from RX clock
127 * 1 - from SOC clock
128 * rx | clk_sel: not care
129 *
130 * RMII:
131 * tx | clk_sel: 0 - RMII clock
132 * 1 - Inverted RMII clock
133 * rx | clk_sel: 0 - RMII clock
134 * 1 - Inverted RMII clock
135 *
136 * delay_code(clk-config[15:8])
137 * 0 ~ 255
138 *
139 * delay_step(clk-config[7:0])
140 * 0b000 - 28.14ps
141 * 0b001 - 37.9ps
142 * 0b010 - 32.91ps
143 * 0b011 - 52.76ps
144 */
145#if 1
146 tx-clk-config = <0x2603>;
147 rx-clk-config = <0x0>;
148 /* enable 1000M phy*/
149 3v3-enable = <0>; /* IO voltage, 1 - 3.3v, 0 - 1.8v */
150 phy-handle = <&phy0>;
151#else
152 tx-clk-config = <0x0>;
153 rx-clk-config = <0x0>;
154 /* enable 100M phy*/
155 3v3-enable = <1>; /* IO voltage, 1 - 3.3v, 0 - 1.8v */
156 phy-handle = <&phy3>;
157#endif
158
159 /* enable fix link for ethernet switch */
160 /*
161 fixed-link {
162 speed = <100>;
163 full-duplex;
164 phy-mode = "rmii";
165 };
166 */
167
168 mdio: mdio-bus {
169 #address-cells = <0x1>;
170 #size-cells = <0x0>;
171 /* YT8521 10M/100M/100OM 1.8V RGMII PHY */
172 phy0: phy@0 {
173 compatible = "ethernet-phy-ieee802.3-c22";
174 device_type = "ethernet-phy";
175 reg = <0x0>; /* set phy address*/
176 phy-mode = "rgmii";
177 tx_rx_delay = <0x0 0x5>; /* 150ps per step*/
178 };
179
180 /* YT8512B 10M/100M 3.3V RMII PHY */
181 phy3: phy@3 {
182 compatible = "ethernet-phy-ieee802.3-c22";
183 device_type = "ethernet-phy";
184 reg = <0x3>; /* set phy address*/
185 phy-mode = "rmii";
186 driver_strength = <0x3>;
187 };
188
189 /* IP175D 10M/100M 3.3V RMII SWITCH */
190 phy1: phy@1 {
191 compatible = "ethernet-phy-ieee802.3-c22";
192 device_type = "ethernet-phy";
193 reg = <0x1>; /* set phy address*/
194 phy-mode = "rmii";
195 };
196 };
197 };
198 qspi: spi@0xd420b000 {
199 asr,qspi-freq = <78000000>;
200 status = "okay";
201 };
202 /* SD card */
203 sdh0: sdh@d4280000 {
204 pinctrl-names = "default", "slow", "fast";
205 pinctrl-0 = <&sdh0_pmx_func1 &sdh0_pmx_func2 &sdh0_pmx_func3>;
206 pinctrl-1 = <&sdh0_pmx_func1_slow &sdh0_pmx_func2_slow &sdh0_pmx_func3>;
207 pinctrl-2 = <&sdh0_pmx_func1_fast &sdh0_pmx_func2_fast &sdh0_pmx_func3>;
208 vmmc-supply = <&vcc_sdh1>;
209 vqmmc-supply = <&pm802ldo6>;
210 bus-width = <4>;
211 no-mmc;
212 no-sdio;
213 non-removable;
214 broken-cd;
215 wp-inverted;
216 asr,sdh-pm-runtime-en;
217 asr,sdh-host-caps-disable = <(MMC_CAP_UHS_SDR104)>;
218 asr,sdh-quirks = <(
219 SDHCI_QUIRK_BROKEN_CARD_DETECTION |
220 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
221 )>;
222 asr,sdh-quirks2 = <(
223 SDHCI_QUIRK2_SET_AIB_MMC |
224 SDHCI_QUIRK2_PRESET_VALUE_BROKEN
225 )>;
226 /* prop "sdh-dtr-data":
227 <timing preset_rate src_rate tx_delay rx_delay tx_dline_reg rx_dline_reg> */
228 asr,sdh-dtr-data =
229 <PXA_MMC_TIMING_LEGACY PXA_SDH_DTR_26M PXA_SDH_DTR_104M 0 0 0 0>,
230 <PXA_MMC_TIMING_SD_HS PXA_SDH_DTR_52M PXA_SDH_DTR_104M 0 0 0 0>,
231 <PXA_MMC_TIMING_UHS_DDR50 PXA_SDH_DTR_52M PXA_SDH_DTR_104M 0 0 0 3>,
232 <PXA_MMC_TIMING_UHS_SDR50 PXA_SDH_DTR_104M PXA_SDH_DTR_208M 0 0 0 0>,
233 <PXA_MMC_TIMING_UHS_SDR104 PXA_SDH_DTR_208M PXA_SDH_DTR_208M 0 0 0 0>,
234 <PXA_MMC_TIMING_MAX PXA_SDH_DTR_PS_NONE PXA_SDH_DTR_104M 0 0 0 0>;
235 status = "okay";
236 };
237
238 /* SDIO */
239 sdh1: sdh@d4280800 {
240 pinctrl-names = "default", "fast", "sleep";
241 pinctrl-0 = <&sdh1_pmx_func1 &sdh1_pmx_func2 &sdh1_pmx_func3>;
242 pinctrl-1 = <&sdh1_pmx_func1_fast &sdh1_pmx_func2_fast &sdh1_pmx_func3>;
243 pinctrl-2 = <&sdh1_pmx_edge_wakeup>;
244 bus-width = <4>;
245 no-mmc;
246 no-sd;
247 non-removable;
248 keep-power-in-suspend;
249 enable-sdio-wakeup;
250 /* clk-scaling-config:
251 <up_threshold down_threshold polling_interval> */
252 clk-scaling-config = <25 12 200>;
253 min-ddr-qos = <156000 312000 400000>;
254 asr,sdh-pm-runtime-en;
255 asr,sdh-quirks = <(
256 SDHCI_QUIRK_BROKEN_CARD_DETECTION |
257 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
258 )>;
259 asr,sdh-quirks2 = <(
260 SDHCI_QUIRK2_NO_TIMER_RETUNING |
261 SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
262 SDHCI_QUIRK2_BASE_CLOCK_ALWAYS_ON
263 )>;
264 asr,sdh-pm-caps = <(MMC_PM_KEEP_POWER)>;
265 asr,sdh-host-caps2 = <(
266 MMC_CAP2_ONLY_1_8V |
267 MMC_CAP2_DISABLE_PROBE_CDSCAN |
268 MMC_CAP2_CLK_SCALE |
269 MMC_CAP2_BUS_CLK_NO_SCALE
270 )>;
271 /* prop "sdh-dtr-data":
272 <timing preset_rate src_rate tx_delay rx_delay tx_dline_reg rx_dline_reg> */
273 asr,sdh-dtr-data =
274 <PXA_MMC_TIMING_LEGACY PXA_SDH_DTR_26M PXA_SDH_DTR_104M 0 0 0 0>,
275 <PXA_MMC_TIMING_SD_HS PXA_SDH_DTR_45M PXA_SDH_DTR_89M 0 0 0 0>,
276 <PXA_MMC_TIMING_UHS_DDR50 PXA_SDH_DTR_52M PXA_SDH_DTR_104M 0 0 0 3>,
277 <PXA_MMC_TIMING_UHS_SDR50 PXA_SDH_DTR_83M PXA_SDH_DTR_83M 0 0 0 3>,
278 <PXA_MMC_TIMING_UHS_SDR104 PXA_SDH_DTR_208M PXA_SDH_DTR_208M 0 0 0 0>,
279 <PXA_MMC_TIMING_MAX PXA_SDH_DTR_PS_NONE PXA_SDH_DTR_89M 0 0 0 0>;
280 status = "okay";
281 };
282 pcie0: pcie@0xd4288000{
283 reset-gpios = <&gpio 42 0 >;
284 status = "okay";
285 };
286 pciephy0: pcie-phy@d4210000 {
287 status = "okay";
288 };
289 camera: camera@d420c000 {
290 compatible = "asr,camera";
291 reg = <0xd420c000 0x1000>, /* IPE registers */
292 <0xd420e000 0x1000>; /* ISP registers */
293 reg-names = "ipe", "isp";
294 interrupts = <58>;
295 pinctrl-names = "default";
296 pinctrl-0 = <&isp_spi_data>;
297 lpm-qos = <PM_QOS_CPUIDLE_BLOCK_AXI>;
298 clock-frequency = <24>;
299 clocks = <&soc_clocks ASR1803_CLK_CAMERA>;
300 clock-names = "cam_clk";
301 status = "okay";
302 port {
303 #address-cells = <1>;
304 #size-cells = <0>;
305 spi_in_cam: endpoint@0 {
306 reg = <0>;
307 remote-endpoint = <&gc0312_out>;
308 };
309 };
310 };
311 };
312
313 apb@d4000000 {
314 ssp_dai1: pxa-ssp-dai@1 {
315 compatible = "asr,pxa-ssp-dai";
316 reg = <0x1 0x0>;
317
318 port = <&ssp1>;
319 pinctrl-names = "default","ssp";
320 pinctrl-0 = <&i2s_gpio>;
321 pinctrl-1 = <&i2s_func>;
322 ssp-gpio = <&gpio 25 0 &gpio 26 0 &gpio 27 0 &gpio 28 0>;
323
324 dmas = <&pdma0 54 1
325 &pdma0 55 1>;
326 dma-names = "rx", "tx";
327
328 platform_driver_name = "pdma_platform";
329 burst_size = <4>;
330 playback_period_bytes = <2048>;
331 playback_buffer_bytes = <4096>;
332 capture_period_bytes = <2048>;
333 capture_buffer_bytes = <4096>;
334 };
335 mfpr: mfpr@d401e000 {
336 status = "okay";
337 /* intend to replace lpm-board-cfg
338 no-apbsd-in-d1pp = <0x1>; //"wakeup-state-d1pp"
339 pin1:pin1@d401e01B0 {
340 offset = <0x1B0>;
341 udr-cfg = <0xA040>;
342 };
343 pin2:pin2@d401e01B4 {
344 offset = <0x1B4>;
345 udr-cfg = <0xA040>;
346 };
347 */
348 };
349 timer0: timer@d4014000 {
350 status = "okay";
351 };
352 /* ap uart1, gps uart */
353 uart1: uart@d4017000 {
354 pinctrl-names = "default";
355 pinctrl-0 = <&uart1_pmx_func>;
356 status = "disabled";
357 };
358 /* ap uart2, gps uart */
359 uart2: uart@d4018000 {
360 pinctrl-names = "default";
361 pinctrl-0 = <&uart2_pmx_func>;
362 status = "okay";
363 };
364 /* ap uart3 */
365 uart3: uart@d401f000 { /* nezhas evb use ap uart */
366 pinctrl-names = "default","sleep";
367 pinctrl-0 = <&uart3_pmx_func1 &uart3_pmx_func2>;
368 pinctrl-1 = <&uart3_pmx_func1_sleep &uart3_pmx_func2>;
369 edge-wakeup-gpio = <&gpio 29 0>; /* GPIO29: AP UART rx pin */
370 status = "okay";
371 };
372 /* ap uart4 */
373 uart4: uart@d401f800 {
374 pinctrl-names = "default";
375 pinctrl-0 = <&uart4_pmx_rxd &uart4_pmx_txd>;
376 status = "disabled";
377 };
378 rtc: rtc@d4010000 {
379 status = "okay";
380 };
381 pmx: pinmux@d401e000 {
382 /* pin base = base_addr / 4, nr pins & gpio function */
383 pinctrl-single,gpio-range = <
384 /*
385 * GPIO number is hardcoded for range at here.
386 * In gpio chip, GPIO number is not hardcoded for range.
387 * Since one gpio pin may be routed to multiple pins,
388 * define these gpio range in pxa910-dkb.dts not pxa910.dtsi.
389 */
390 /*&range 80 4 0 */ /* GPIO25 ~ GPIO28 */
391 &range 55 32 0 /* GPIO0 ~ GPIO31 */
392 &range 87 32 0 /* GPIO32 ~ GPIO63 */
393 &range 119 32 0 /* GPIO64 ~ GPIO95 */
394 &range 151 32 0 /* GPIO96 ~ GPIO127 */
395 >;
396
397#ifdef CONFIG_FB_ASR
398 lcd_pmx_func: lcd_pmx_func {
399 pinctrl-single,pins = <
400 #ifdef CONFIG_FB_ASR_SPI
401 GPIO00 AF3 /* SPI_DCLK */
402 GPIO01 AF3 /* SPI_DCX */
403 GPIO16 AF3 /* SPI_DOUT_1 */
404 GPIO02 AF3 /* SPI_CS0 */
405 GPIO03 AF3 /* SPI_DIN */
406 GPIO06 AF3 /* SPI_DOUT */
407 GPIO81 AF1 /* SPI_VSYNC */
408 GPIO82 AF1 /* SPI_RSTB */
409 #elif defined(CONFIG_FB_ASR_MCU)
410 GPIO00 AF5 /* MCU_D0 */
411 GPIO01 AF5 /* MCU_D5 */
412 GPIO02 AF5 /* MCU_CS0 */
413 GPIO03 AF5 /* MCU_RDB */
414 GPIO06 AF5 /* MCU_WRB */
415 GPIO81 AF1 /* MCU_VSYNC */
416 GPIO82 AF1 /* MCU_RSTB */
417 GPIO16 AF5 /* MCU_D6 */
418 GPIO17 AF5 /* MCU_A0 */
419 GPIO18 AF5 /* MCU_D7 */
420 GPIO33 AF3 /* MCU_D3 */
421 GPIO34 AF3 /* MCU_D4 */
422 GPIO35 AF3 /* MCU_D1 */
423 GPIO36 AF3 /* MCU_D2 */
424 #elif defined(CONFIG_FB_ASR_MIPI)
425 GPIO81 AF1 /* MIPI_VSYNC */
426 GPIO82 AF1 /* MIPI_RSTB */
427 #endif
428 >;
429 /* NOTE: need to PULL_UP here */
430 DS_MEDIUM;PULL_UP;EDGE_NONE;LPM_NONE;
431 };
432#endif
433
434 ssp0_pmx_func: ssp0_pmx_func {
435 pinctrl-single,pins = <
436 GPIO36 AF1 /* TXD */
437 GPIO35 AF1 /* RXD */
438 GPIO34 AF1 /* FRM */
439 /*GPIO34 AF0*/ /* FRM *//* DXS101 Use the config of Cs-gpios */
440 GPIO33 AF1 /* SCLK */
441 >;
442 DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL;
443 };
444 lcd_bl_func: lcd_bl_func {
445 pinctrl-single,pins = <
446 VCXO_OUT AF1 /* GPIO126, lcd bl */
447 GPIO82 AF0 /* reset */
448 >;
449 MFP_DEFAULT;
450 };
451 twsi0_pmx_func: twsi0_pmx_func {
452 pinctrl-single,pins = <
453 GPIO49 AF1
454 GPIO50 AF1
455 >;
456 MFP_LPM_FLOAT;
457 };
458 twsi0_pmx_gpio: twsi0_pmx_gpio {
459 pinctrl-single,pins = <
460 GPIO49 AF0
461 GPIO50 AF0
462 >;
463 MFP_LPM_FLOAT;
464 };
465 twsi1_pmx_func: twsi1_pmx_func {
466 pinctrl-single,pins = <
467 GPIO10 AF1
468 GPIO11 AF1
469 >;
470 MFP_LPM_FLOAT;
471 };
472 twsi1_pmx_gpio: twsi1_pmx_gpio {
473 pinctrl-single,pins = <
474 GPIO10 AF0
475 GPIO11 AF0
476 >;
477 MFP_LPM_FLOAT;
478 };
479 /* no pull, no LPM */
480 dvc_pmx_func: dvc_pmx_func {
481 /* hw-dvc */
482 pinctrl-single,pins = <
483 TDS_DIO0 AF0
484 TDS_DIO1 AF0
485 >;
486 DS_MEDIUM;PULL_FLOAT;EDGE_NONE;SL_NORMAL;
487 };
488 leds_pmx_func: leds_pmx_func {
489 pinctrl-single,pins = <
490 DF_IO10 AF1
491 DF_IO11 AF1
492 DF_IO12 AF1
493 >;
494 DS_MEDIUM;PULL_FLOAT;EDGE_NONE;SL_NORMAL;
495 };
496
497 gps_pmx_onoff: gps_pmx_onoff {
498 pinctrl-single,pins = <
499 TDS_TXREV AF1
500 >;
501 DS_MEDIUM;PULL_DOWN;EDGE_NONE;SL_NORMAL;
502 };
503 gps_pmx_reset: gps_pmx_reset {
504 pinctrl-single,pins = <
505 TDS_RXON AF1
506 >;
507 DS_MEDIUM;PULL_DOWN;EDGE_NONE;SL_NORMAL;
508 };
509 gnss_clk_on: gnss_clk_on {
510 pinctrl-single,pins = <
511 GPIO43 AF2 /*GPIO[43] */
512 GPIO62 AF2 /*GPIO62->GPS_BLANK*/
513 VBUS_DRV AF1 /* GPIO[122] */
514 >;
515 DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_LOW;
516 };
517 uart1_pmx_func: uart1_pmx_func {
518 pinctrl-single,pins = <
519 GPIO37 AF1
520 GPIO38 AF1
521 >;
522 MFP_DEFAULT;
523 };
524 uart2_pmx_func: uart2_pmx_func {
525 pinctrl-single,pins = <
526 GPIO44 AF1
527 GPIO45 AF1
528 >;
529 MFP_DEFAULT;
530 };
531 uart3_pmx_func1: uart3_pmx_func1 {
532 pinctrl-single,pins = <
533 GPIO29 AF1
534 >;
535 MFP_DEFAULT;
536 };
537 uart3_pmx_func2: uart3_pmx_func2 {
538 pinctrl-single,pins = <
539 GPIO30 AF1
540 >;
541 MFP_DEFAULT;
542 };
543 uart3_pmx_func1_sleep: uart3_pmx_func1_sleep {
544 pinctrl-single,pins = <
545 GPIO29 AF1
546 >;
547 DS_MEDIUM;PULL_NONE;EDGE_BOTH;SL_NORMAL;
548 };
549 uart4_pmx_rxd: uart4_pmx_rxd {
550 /* gps dedicated uart */
551 pinctrl-single,pins = <
552 GPIO51 AF1
553 GPIO32 AF1
554 >;
555 MFP_DEFAULT;
556 };
557 uart4_pmx_txd: uart4_pmx_txd {
558 /* gps dedicated uart */
559 pinctrl-single,pins = <
560 GPIO52 AF1
561 GPIO31 AF1
562 >;
563 MFP_DEFAULT;
564 };
565 panel_rst_func: panel_rst_func {
566 pinctrl-single,pins = <
567 DF_nCS1 AF1
568 >;
569 DS_MEDIUM;PULL_FLOAT;EDGE_NONE;SL_NORMAL;
570 };
571
572 sd_ldo_en: sd_ldo_en {
573 pinctrl-single,pins = <
574 GPIO19 AF0
575 >;
576 MFP_PULL_DOWN;
577 };
578 sdh0_pmx_func1: sdh0_pmx_func1 {
579 pinctrl-single,pins = <
580 MMC1_DAT3 AF0
581 MMC1_DAT2 AF0
582 MMC1_DAT1 AF0
583 MMC1_DAT0 AF0
584 MMC1_CMD AF0
585 >;
586 DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL;
587 };
588 sdh0_pmx_func2: sdh0_pmx_func2 {
589 pinctrl-single,pins = <
590 MMC1_CLK AF0
591 >;
592 DS_MEDIUM;PULL_NONE;EDGE_NONE;
593 };
594 sdh0_pmx_func3: sdh0_pmx_func3 {
595 pinctrl-single,pins = <
596 MMC1_CD AF0
597 >;
598 MFP_PULL_UP;
599 };
600 sdh0_pmx_func1_slow: sdh0_pmx_func1_slow {
601 pinctrl-single,pins = <
602 MMC1_DAT3 AF0
603 MMC1_DAT2 AF0
604 MMC1_DAT1 AF0
605 MMC1_DAT0 AF0
606 MMC1_CMD AF0
607 >;
608 DS_FAST0;PULL_NONE;EDGE_NONE;SL_NORMAL;
609 };
610 sdh0_pmx_func2_slow: sdh0_pmx_func2_slow {
611 pinctrl-single,pins = <
612 MMC1_CLK AF0
613 >;
614 DS_FAST0;PULL_NONE;EDGE_NONE;
615 };
616 sdh0_pmx_func1_fast: sdh0_pmx_func1_fast {
617 pinctrl-single,pins = <
618 MMC1_DAT3 AF0
619 MMC1_DAT2 AF0
620 MMC1_DAT1 AF0
621 MMC1_DAT0 AF0
622 MMC1_CMD AF0
623 >;
624 DS_FAST1;PULL_NONE;EDGE_NONE;SL_NORMAL;
625 };
626 sdh0_pmx_func2_fast: sdh0_pmx_func2_fast {
627 pinctrl-single,pins = <
628 MMC1_CLK AF0
629 >;
630 DS_FAST1;PULL_NONE;EDGE_NONE;
631 };
632 sdh1_pmx_func1_fast: sdh1_pmx_func1_fast {
633 pinctrl-single,pins = <
634 TDS_DIO13 AF0 /* WLAN_DAT3 */
635 TDS_DIO14 AF0 /* WLAN_DAT2 */
636 TDS_DIO15 AF0 /* WLAN_DAT1 */
637 TDS_DIO16 AF0 /* WLAN_DAT0 */
638 TDS_DIO17 AF0 /* WLAN_CMD */
639 >;
640 DS_FAST0;PULL_NONE;EDGE_NONE;SL_NORMAL;
641 };
642 sdh1_pmx_func2_fast: sdh1_pmx_func2_fast {
643 pinctrl-single,pins = <
644 TDS_DIO18 AF0 /* WLAN_CLK */
645 >;
646 DS_FAST0;PULL_DOWN;EDGE_NONE;SL_NORMAL;
647 };
648 sdh1_pmx_func1: sdh1_pmx_func1 {
649 pinctrl-single,pins = <
650 TDS_DIO13 AF0 /* WLAN_DAT3 */
651 TDS_DIO14 AF0 /* WLAN_DAT2 */
652 TDS_DIO15 AF0 /* WLAN_DAT1 */
653 TDS_DIO16 AF0 /* WLAN_DAT0 */
654 TDS_DIO17 AF0 /* WLAN_CMD */
655 >;
656 DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_LOW;
657 };
658 sdh1_pmx_func2: sdh1_pmx_func2 {
659 pinctrl-single,pins = <
660 TDS_DIO18 AF0 /* WLAN_CLK */
661 >;
662 DS_MEDIUM;PULL_DOWN;EDGE_NONE;SL_LOW;
663 };
664 sdh1_pmx_func3: sdh1_pmx_func3 {
665 pinctrl-single,pins = <
666 GPIO37 AF0 /* VCXO_REQ AF1 WLAN_WAKE_HOST */
667 >;
668 MFP_PULL_DOWN;
669 };
670 sdh1_pmx_edge_wakeup: sdh1_pmx_edge_wakeup {
671 pinctrl-single,pins = <
672 GPIO37 AF0 /* VCXO_REQ AF1 */
673 >;
674 DS_MEDIUM;PULL_DOWN;EDGE_RISE;SL_NORMAL;
675 };
676 sdh1_pmx_pd_rst_off: sdh1_pmx_pd_rst_off {
677 pinctrl-single,pins = <
678 GPIO83 AF0 /* AF0 WLAN_PDn */
679 GPIO38 AF0 /* AF0 LDO_EN */
680 >;
681 MFP_PULL_DOWN;
682 };
683 sdh1_pmx_pd_rst_on: sdh1_pmx_pd_rst_on {
684 pinctrl-single,pins = <
685 GPIO83 AF0 /* AF0 WLAN_PDn */
686 GPIO38 AF0 /* AF0 LDO_EN */
687 >;
688 MFP_PULL_UP;
689 };
690 eta6005_charger_en: eta6005_charger_en {
691 pinctrl-single,pins = <
692 GPIO08 AF0
693 >;
694 MFP_PULL_UP;
695 };
696 eta6005_charger_stat: eta6005_charger_stat {
697 pinctrl-single,pins = <
698 GPIO04 AF0
699 >;
700 MFP_DEFAULT;
701 };
702
703 alc5616_pmx_func1: alc5616_pmx_func1 {
704 pinctrl-single,pins = <
705 GPIO08 AF0 /* AP_UART1_DCD_N -> CODEC_IRQ */
706 GPIO20 AF7 /* MCLK:I2S_SYSCLK */
707 >;
708 MFP_DEFAULT;
709 };
710 alc5616_pmx_func2: alc5616_pmx_func2 {
711 pinctrl-single,pins = <
712 GPIO08 AF0 /* AP_UART1_DCD_N -> CODEC_IRQ */
713 GPIO20 AF7 /* MCLK:I2S_SYSCLK */
714 >;
715 MFP_DEFAULT;
716 };
717
718 audio_pa_pmx_func: audio_pa_pmx_func {
719 pinctrl-single,pins = <
720 GPIO39 AF0 /* PA */
721 >;
722 MFP_DEFAULT;
723 };
724 ecall_pmx_func: ecall_pmx_func {
725 pinctrl-single,pins = <
726 GPIO08 AF0 /* auto mode ecall */
727 GPIO09 AF0 /* manual mode ecall */
728 >;
729 MFP_DEFAULT;
730 };
731 slic_pmx_func1: slic_pmx_func1 {
732 pinctrl-single,pins = <
733 GPIO24 AF0 /* SLIC_INT, GPIO24 */
734 VCXO_OUT AF1 /* GPIO127, SLIC_3V3LDO_EN/LCD_BK_EN */
735 >;
736 MFP_DEFAULT;
737 };
738 slic_pmx_func2: slic_pmx_func2 {
739 pinctrl-single,pins = <
740 GPIO23 AF0 /* SLIC_RESET, GPIO23 */
741 >;
742 MFP_DEFAULT;
743 };
744 slic_pmx_func1_sleep: slic_pmx_func1_sleep {
745 pinctrl-single,pins = <
746 GPIO24 AF0 /* SLIC_INT, GPIO24 */
747 >;
748 DS_MEDIUM;PULL_UP;EDGE_BOTH;SL_NORMAL;
749 };
750
751 otg_vbus_func: otg_vbus_func {
752 pinctrl-single,pins = <
753 VBUS_DRV AF1 /* GPIO[122] */
754 >;
755 DS_MEDIUM;PULL_DOWN;EDGE_NONE;
756 };
757
758 emac_pmx_func0: emac_pmx_func0 {
759 pinctrl-single,pins = <
760 GPIO00 AF1 /* GMAC1_RX_DV */
761 GPIO01 AF1 /* GMAC1_RX_D0 */
762 GPIO02 AF1 /* GMAC1_RX_D1 */
763 GPIO03 AF1 /* GMAC1_RX_CLK */
764 /* GPIO04 AF1 GMAC1_RX_D2 */
765 /* GPIO05 AF1 GMAC1_RX_D3 */
766 GPIO06 AF1 /* GMAC1_TX_D0 */
767 GPIO07 AF1 /* GMAC1_TX_D1 */
768 /* GPIO12 AF1 GMAC1_TX_CLK */
769 /* GPIO13 AF1 GMAC1_TX_D2 */
770 /* GPIO14 AF1 GMAC1_TX_D3 */
771 GPIO15 AF1 /* GMAC1_TX_EN */
772 GPIO16 AF1 /* GMAC1_TX_MDC */
773 /* GPIO17 AF1 GMAC1_TX_MDIO */
774 GPIO53 AF1 /* GNSS PPS input */
775 >;
776 DS_MEDIUM;PULL_DOWN;EDGE_NONE;SL_NORMAL;
777 };
778 emac_pmx_func1: emac_pmx_func1 {
779 pinctrl-single,pins = <
780 GPIO04 AF1 /* GMAC1_RX_D2 */
781 GPIO05 AF1 /* GMAC1_RX_D3 */
782 GPIO12 AF1 /* GMAC1_TX_CLK */
783 GPIO13 AF1 /* GMAC1_TX_D2 */
784 GPIO14 AF1 /* GMAC1_TX_D3 */
785 >;
786 DS_MEDIUM;PULL_DOWN;EDGE_NONE;SL_NORMAL;
787 };
788 emac_pmx_func2: emac_pmx_func2 {
789 pinctrl-single,pins = <
790 GPIO17 AF1 /* GMAC1_TX_MDIO */
791 GPIO18 AF1 /* GMAC1_TX_INT_N */
792 >;
793 DS_MEDIUM;PULL_UP;EDGE_NONE;SL_NORMAL;
794 };
795 emac_pmx_func3: emac_pmx_func3 {
796 pinctrl-single,pins = <
797 GPIO20 AF0 /* RESET */
798 /* GPIO54 AF0 LDO_EN */
799 >;
800 DS_SLOW0;PULL_FLOAT;EDGE_NONE;SL_NORMAL;
801 };
802 usim1_pmx_func: usim1_pmx_func {
803 pinctrl-single,pins = <
804 GPIO54 AF0
805 >;
806 DS_MEDIUM;PULL_UP;EDGE_NONE;SL_NORMAL;
807 };
808 usim1_pmx_func_sleep: usim1_pmx_func_sleep {
809 pinctrl-single,pins = <
810 GPIO54 AF0
811 >;
812 DS_MEDIUM;PULL_UP;EDGE_BOTH;SL_NORMAL;
813 };
814 usim2_pmx_func: usim2_pmx_func {
815 pinctrl-single,pins = <
816 GPIO53 AF0
817 >;
818 DS_MEDIUM;PULL_UP;EDGE_NONE;SL_NORMAL;
819 };
820 usim2_pmx_func_sleep: usim2_pmx_func_sleep {
821 pinctrl-single,pins = <
822 GPIO53 AF0
823 >;
824 DS_MEDIUM;PULL_UP;EDGE_BOTH;SL_NORMAL;
825 };
826 pcie_pmx_pd_rst_off: pcie_pmx_pd_rst_off {
827 pinctrl-single,pins = <
828 GPIO42 AF0 /* PERST_N */
829 GPIO48 AF0 /* DC_EN */
830 >;
831 MFP_PULL_DOWN;
832 };
833 pcie_pmx_pd_rst_on: pcie_pmx_pd_rst_on {
834 pinctrl-single,pins = <
835 GPIO42 AF0 /* PERST_N */
836 GPIO48 AF0 /* DC_EN */
837 >;
838 MFP_PULL_UP;
839 };
840 gc032a_pmx_func: gc032a_pmx_func {
841 pinctrl-single,pins = <
842 GPIO21 AF2 /* mclk */
843 GPIO40 AF0 /* CAM_LDO_EN */
844 GPIO32 AF0 /* CAM_PWDN */
845 >;
846 DS_SLOW0;PULL_FLOAT;EDGE_NONE;SL_NORMAL;
847 };
848 isp_spi_data: isp_spi_data {
849 pinctrl-single,pins = <
850 /* spi_data0 ... spi_data1 */
851 GPIO24 AF2
852 GPIO23 AF2
853 /* camera spi clk */
854 GPIO22 AF2
855 >;
856 DS_MEDIUM;PULL_FLOAT;EDGE_NONE;SL_NORMAL;
857 };
858 gpiokey_pmx_func: gpiokey_pmx_func {
859 pinctrl-single,pins = <
860 GPIO09 AF0
861 >;
862 DS_MEDIUM;PULL_UP;EDGE_NONE;SL_NORMAL;
863 };
864 usb_id_pinmux: usb_id_pinmux {
865 pinctrl-single,pins = <
866 USB_ID AF1 /* usbid-gpio99 */
867 >;
868 DS_MEDIUM;PULL_UP;EDGE_NONE;LPM_NONE;
869 };
870 usb_id_pinmux_slp: usb_id_pinmux_slp {
871 pinctrl-single,pins = <
872 USB_ID AF1 /* usbid-gpio99 */
873 >;
874 DS_MEDIUM;PULL_UP;EDGE_BOTH;LPM_NONE;
875 };
876 usb_host_pinmux: usb_host_pinmux {
877 pinctrl-single,pins = <
878 VBUS_DRV AF1 /* gpio-122 */
879 >;
880 DS_MEDIUM;PULL_FLOAT;EDGE_NONE;LPM_NONE;
881 };
882 i2s_func: i2s_func {
883 pinctrl-single,pins = <
884 GPIO25 AF1
885 GPIO26 AF1
886 GPIO27 AF1
887 GPIO28 AF1
888 >;
889 MFP_DEFAULT;
890 };
891 i2s_gpio: i2s_gpio {
892 pinctrl-single,pins = <
893 GPIO25 AF0
894 GPIO26 AF0
895 GPIO27 AF0
896 GPIO28 AF0
897 >;
898 MFP_LPM_FLOAT;
899 };
900 };
901
902 ssp0: spi@d401b000 {
903#ifdef CONFIG_FB_ASR_MCU
904 status = "disabled";
905#else
906 status = "okay";
907#endif
908 pinctrl-names = "default";
909 pinctrl-0 = <&ssp0_pmx_func>;
910 asr,spi-inc-mode;
911#ifdef CONFIG_FB_SPI_LCD
912 /* this enhancemnet feature is not suitable for
913 3 line 9bits spi lcd. */
914 /* asr,ssp-enhancement; */
915
916 lcd: spidev@0 {
917 #address-cells = <1>;
918 #size-cells = <1>;
919 compatible = "spilcd";
920 pinctrl-names = "default";
921 pinctrl-0 = <&lcd_bl_func>;
922 reg = <0>;
923 /* ST7735: need to set spi-max-frequency to 26M
924 * ST7789V: can set spi-max-frequency to 52M
925 */
926 spi-max-frequency = <26000000>;
927 xres = <128>;
928 yres = <128>;
929 bits = <8>; /* 8: 4line, 9: 3line */
930 rst_gpio = <&gpio 24 0>;
931 bl_gpio = <&gpio 126 0>;
932 rs_gpio = <&gpio 22 0>;
933 /* if comment the following statement, it means
934 * the avdd is sit on the "always-on" ldo.
935 */
936 /* avdd-supply = <&LDO1>; */
937 };
938#else
939 /*cs-gpios = <&gpio 34 0>;*//* DXS101 Use the config of Cs-gpios */
940 slic: spidev@0{
941 #address-cells = <1>;
942 #size-cells = <1>;
943 compatible = "asr,slic";
944 reg = <0>;
945 spi-cpol;
946 spi-cpha;
947 spi-max-frequency = <6500000>;
948 };
949#endif
950 };
951 twsi0: i2c@d4011000 {
952 status= "disabled";
953 alc5616@1b {
954 compatible = "asrmicro,alc5616";
955 reg = <0x1b>;
956 pinctrl-names = "default", "sleep";
957 pinctrl-0 = <&alc5616_pmx_func1>;
958 pinctrl-1 = <&alc5616_pmx_func2>;
959#if 0
960 3V3-gpio = <&gpio 23 0>;/* CODEC_LDO_EN */
961 irq-gpio = <&gpio 24 0>;/* CODEC_IRQ for headset detection */
962#else
963 irq-gpio = <&gpio 8 0>;/* CODEC_IRQ for headset detection */
964#endif
965 };
966
967 /*
968 pmic4: 88pm805@38 {
969 compatible = "marvell,88pm805";
970 reg = <0x38>;
971 };
972 */
973 };
974 twsi1: i2c@d4010800 {
975 pinctrl-names = "default","gpio";
976 pinctrl-0 = <&twsi1_pmx_func>;
977 pinctrl-1 = <&twsi1_pmx_gpio>;
978 i2c-gpio = <&gpio 10 0 &gpio 11 0>;
979 status= "okay";
980
981 gc032a: gc032a@21{
982 compatible = "galaxycore,gc032a";
983 reg = <0x21>;
984 pinctrl-names = "default";
985 pinctrl-0 = <&gc032a_pmx_func>;
986 pwdn-gpios = <&gpio 32 0>;
987 power-gpios = <&gpio 40 0>;
988
989 status = "okay";
990 port {
991 gc0312_out: endpoint {
992 remote-endpoint = <&spi_in_cam>;
993 };
994 };
995 };
996 };
997 twsi2: i2c@d4037000 {
998 status = "okay";
999
1000 pmic4: 88pm805@38 {
1001 compatible = "marvell,88pm805";
1002 reg = <0x38>;
1003 };
1004
1005 pmic5: pm802@0 {
1006 compatible = "asr,pm802";
1007 reg = <0x00>;
1008 interrupts = <4>;
1009 interrupt-parent = <&intc>;
1010 interrupt-controller;
1011 #interrupt-cells = <1>;
1012 chg_irq_from_exton;
1013 /* set scs-int-active-high depending on board connection */
1014 scs-int-active-high;
1015 battery {
1016 compatible = "asr,pm802-bat";
1017 status = "disabled";
1018
1019 online-gpadc = <1>;
1020 temperature-gpadc = <1>;
1021
1022 hi-volt-online = <1150>; /* mV */
1023 lo-volt-online = <20>; /* mV */
1024 hi-volt-temp = <1150>; /* mV */
1025 lo-volt-temp = <200>; /* mV */
1026
1027 sw-fg-use-ntc;
1028 full-capacity = <2050>; /* mAh */
1029 r1-resistor = <40>; /* mohm */
1030 r2-resistor = <30>; /* mohm */
1031 rs-resistor = <120>; /* mohm */
1032 roff-resistor = <0>; /* mohm */
1033 roff-initial-resistor = <0>; /* mohm */
1034
1035 times-in-zero-degree = <1>;
1036 offset-in-zero-degree = <0>;
1037
1038 times-in-ten-degree = <2>;
1039 offset-in-ten-degree = <100>;
1040
1041 power-off-threshold = <3350>; /* mV */
1042 safe-power-off-threshold = <3200>; /* mV */
1043
1044 online-gp-bias-curr = <11>; /* uA */
1045
1046 soc-ramp-up-interval = <150>; /* s */
1047 /* choose -20C, 0C, 10C, 40C, 45C, 55C as threshold */
1048 tbat-threshold = <20 0 10 40 45 55>; /* ohm */
1049 ntc-table-size = <88>;
1050 stop-chg-for-vbatmeas;
1051 /* -24C, -23C, ..., 62C, 63C */
1052 ntc-table = <
1053 89680 85130 80840 76790 72970 69360 65960 62740
1054 59700 56830 54130 51530 49100 46800 44610 42550
1055 40590 38730 36970 35300 33710 32210 30780 29420
1056 28130 26910 25750 24640 23590 22580 21630 20720
1057 19860 19030 18250 17500 16790 16110 15460 14840
1058 14250 13690 13150 12640 12150 11680 11230 10800
1059 10390 10000 9620 9270 8920 8590 8280 7980
1060 7690 7410 7150 6890 6650 6410 6190 5970
1061 5770 5570 5380 5190 5020 4850 4680 4530
1062 4380 4230 4100 3960 3830 3710 3590 3480
1063 3370 3260 3160 3060 2960 2870 2780 2700
1064 >;
1065 };
1066 usb {
1067 status = "disabled";
1068 vbus_gpio = <0xff>; /* set_vbus */
1069 id-gpadc = <0xff>; /* usb-id */
1070 vchg-from-exton = <1>;
1071 vbus-detect = <1>; /* vbus-irq */
1072 get-vbus = <1>; /* get-vbus */
1073 };
1074 };
1075 pmic6: pm803@30 {
1076 compatible = "asr,pm803";
1077 reg = <0x30>;
1078 interrupts = <4>;
1079 interrupt-parent = <&intc>;
1080 interrupt-controller;
1081 #interrupt-cells = <1>;
1082 chg_irq_from_exton;
1083 /* set scs-int-active-high depending on board connection */
1084 scs-int-active-high;
1085 battery {
1086 compatible = "asr,pm803-bat";
1087 status = "disabled";
1088
1089 online-gpadc = <1>;
1090 temperature-gpadc = <1>;
1091
1092 hi-volt-online = <1150>; /* mV */
1093 lo-volt-online = <20>; /* mV */
1094 hi-volt-temp = <1150>; /* mV */
1095 lo-volt-temp = <200>; /* mV */
1096
1097 sw-fg-use-ntc;
1098 full-capacity = <2050>; /* mAh */
1099 r1-resistor = <40>; /* mohm */
1100 r2-resistor = <30>; /* mohm */
1101 rs-resistor = <120>; /* mohm */
1102 roff-resistor = <0>; /* mohm */
1103 roff-initial-resistor = <0>; /* mohm */
1104
1105 times-in-zero-degree = <1>;
1106 offset-in-zero-degree = <0>;
1107
1108 times-in-ten-degree = <2>;
1109 offset-in-ten-degree = <100>;
1110
1111 power-off-threshold = <3350>; /* mV */
1112 safe-power-off-threshold = <3200>; /* mV */
1113
1114 online-gp-bias-curr = <11>; /* uA */
1115
1116 soc-ramp-up-interval = <150>; /* s */
1117 /* choose -20C, 0C, 10C, 40C, 45C, 55C as threshold */
1118 tbat-threshold = <20 0 10 40 45 55>; /* ohm */
1119 ntc-table-size = <88>;
1120 stop-chg-for-vbatmeas;
1121 /* -24C, -23C, ..., 62C, 63C */
1122 ntc-table = <
1123 89680 85130 80840 76790 72970 69360 65960 62740
1124 59700 56830 54130 51530 49100 46800 44610 42550
1125 40590 38730 36970 35300 33710 32210 30780 29420
1126 28130 26910 25750 24640 23590 22580 21630 20720
1127 19860 19030 18250 17500 16790 16110 15460 14840
1128 14250 13690 13150 12640 12150 11680 11230 10800
1129 10390 10000 9620 9270 8920 8590 8280 7980
1130 7690 7410 7150 6890 6650 6410 6190 5970
1131 5770 5570 5380 5190 5020 4850 4680 4530
1132 4380 4230 4100 3960 3830 3710 3590 3480
1133 3370 3260 3160 3060 2960 2870 2780 2700
1134 >;
1135 };
1136 usb {
1137 status = "disabled";
1138 vbus_gpio = <0xff>; /* set_vbus */
1139 id-gpadc = <0xff>; /* usb-id */
1140 vchg-from-exton = <1>;
1141 vbus-detect = <1>; /* vbus-irq */
1142 get-vbus = <1>; /* get-vbus */
1143 };
1144 };
1145 };
1146 };
1147 };
1148
1149 vcc_sdh1: sd-regulator {
1150 compatible = "regulator-fixed";
1151 pinctrl-names = "default";
1152 pinctrl-0 = <&sd_ldo_en>;
1153 regulator-name = "SDH1 VCC";
1154 regulator-min-microvolt = <3300000>;
1155 regulator-max-microvolt = <3300000>;
1156 gpio = <&gpio 19 0>;
1157 enable-active-high;
1158 };
1159
1160 asr-rfkill {
1161 compatible = "asr,asr-rfkill";
1162 pinctrl-names = "off", "on";
1163 pinctrl-0 = <&sdh1_pmx_pd_rst_off>;
1164 pinctrl-1 = <&sdh1_pmx_pd_rst_on>;
1165 sd-host = <&sdh1>;
1166 pd-gpio = <&gpio 83 0>;
1167 3v3-ldo-gpio = <&gpio 38 0>;
1168 edge-wakeup-gpio = <&gpio 37 0>;
1169 status = "okay";
1170 };
1171
1172 pcie-rfkill {
1173 compatible = "mrvl,pcie-rfkill";
1174 pinctrl-names = "off", "on";
1175 pinctrl-0 = <&pcie_pmx_pd_rst_off>;
1176 pinctrl-1 = <&pcie_pmx_pd_rst_on>;
1177 rst-gpio = <&gpio 42 0>;
1178 3v3-ldo-gpio = <&gpio 48 0>;
1179 status = "okay";
1180 };
1181
1182 asr-gps {
1183 compatible = "asr,asr-gnss";
1184 clocks = <&soc_clocks ASR1803_CLK_VCTCXO_REQ>;
1185 clock-names = "gnss_26m";
1186 pinctrl-names = "default";
1187 pinctrl-0 = <&gnss_clk_on>;
1188 host-wakeup-gnss-gpio = <&gpio 120 0>;
1189 gnss-wakeup-host-gpio = <&gpio 117 0>;
1190 rst-gpio = <&gpio 122 0>;
1191 status = "okay";
1192 };
1193 sound {
1194 compatible = "ASRMICRO,asrmicro-snd-card";
1195 ssp-controllers = <&ssp_dai1>;
1196 };
1197
1198 ecall {
1199 compatible = "asr,ecall-event";
1200 pinctrl-names = "default";
1201 pinctrl-0 = <&ecall_pmx_func>;
1202 gpio-auto-ecall = <8>;
1203 gpio-manual-ecall = <9>;
1204 status = "disabled";
1205 };
1206
1207 usim1: usim1 {
1208 compatible = "asr,usim1";
1209 pinctrl-names = "default", "sleep";
1210 pinctrl-0 = <&usim1_pmx_func>;
1211 pinctrl-1 = <&usim1_pmx_func_sleep>;
1212 edge_detect_gpio = <54>; /* GPIO54: SIM detect pin */
1213 status = "okay";
1214 };
1215 /* set okay for this node if usim2 is needed */
1216 usim2: usim2 {
1217 compatible = "asr,usim2";
1218 pinctrl-names = "default", "sleep";
1219 pinctrl-0 = <&usim2_pmx_func>;
1220 pinctrl-1 = <&usim2_pmx_func_sleep>;
1221 edge_detect_gpio = <53>; /* GPIO53: SIM detect pin */
1222#ifdef CONFIG_ASR_DSDS
1223 status = "okay";
1224#else
1225 status = "disabled";
1226#endif
1227 };
1228 gpio_keys {
1229 compatible = "gpio-keys";
1230 #address-cells = <1>;
1231 #size-cells = <0>;
1232 /* autorepeat; */
1233 pinctrl-names = "default";
1234 pinctrl-0 = <&gpiokey_pmx_func>;
1235 button@1 {
1236 label = "qrcode-key";
1237 linux,code = <139>; /* KEY_MENU, refer to linux/input.h */
1238 /* NOTE:
1239 * We use the FORCE DOWNLOAD key to implement the qrcode key in DKB.
1240 * Customer SHOULD change it to any other gpios.
1241 * Because user may do the misoperation that
1242 * powerup with FDL key pressed,
1243 * then the borad will enter force download mode.
1244 */
1245 gpios = <&gpio 9 1>;
1246 gpio-key,wakeup;
1247 };
1248 };
1249
1250 audio_pa {
1251 compatible = "asrmicro,audio-pa";
1252 pinctrl-names = "default";
1253 pinctrl-0 = <&audio_pa_pmx_func>;
1254 pa-gpio = <&gpio 39 0>;
1255 status = "okay";
1256 };
1257
1258 audio_regs {
1259 compatible = "ASRMICRO,audio-registers";
1260 reg = <0xD4050044 0x4>;
1261 status = "okay";
1262 };
1263
1264 nz3-slic {
1265 compatible = "asr,nz3-slic";
1266 pinctrl-names = "default", "sleep";
1267 pinctrl-0 = <&slic_pmx_func1 &slic_pmx_func2>;
1268 pinctrl-1 = <&slic_pmx_func1_sleep &slic_pmx_func2>;
1269 rst-gpio = <&gpio 23 0>;
1270 edge-wakeup-gpio = <&gpio 24 0>;
1271 vdd-3v3-gpio = <&gpio 127 0>;
1272 status = "disabled";
1273 };
1274 microsemi-slic {
1275 compatible = "asr,microsemi-slic";
1276 pinctrl-names = "default", "sleep";
1277 pinctrl-0 = <&slic_pmx_func1>;
1278 pinctrl-1 = <&slic_pmx_func1_sleep>;
1279 edge-wakeup-gpio = <&gpio 24 0>;
1280 vdd-3v3-gpio = <&gpio 127 0>;
1281 status = "disabled";
1282 };
1283 maxlinear-slic {
1284 compatible = "asr,maxlinear-slic";
1285 pinctrl-names = "default", "sleep";
1286 pinctrl-0 = <&slic_pmx_func1 &slic_pmx_func2>;
1287 pinctrl-1 = <&slic_pmx_func1_sleep &slic_pmx_func2>;
1288 rst-gpio = <&gpio 23 0>;
1289 edge-wakeup-gpio = <&gpio 24 0>;
1290 vdd-3v3-gpio = <&gpio 127 0>;
1291 status = "disabled";
1292 };
1293 /*
1294 lpm-board-cfg { deprecated, move to mfpr@d401e000
1295 compatible = "asr,lpm-board-cfg";
1296 wakeup-state-d1pp = <0x1>;
1297 udr-mfpr-config = <0x1B0 0xA040 0x0
1298 0x1B4 0xA040 0x0>;
1299 };
1300 */
1301};
1302#ifdef CONFIG_ASR_DSDS
1303#include "asr_pm802_2usim.dtsi"
1304#include "88pm805.dtsi"
1305#include "asr_pm803_2usim.dtsi"
1306#else
1307#include "asr_pm802.dtsi"
1308#include "88pm805.dtsi"
1309#include "asr_pm803.dtsi"
1310#endif
1311
1312#ifdef CONFIG_AB_SYSTEM
1313#include "asr1903_ab_flash_layout.dtsi"
1314#else
1315#include "asr1903_flash_layout.dtsi"
1316#endif