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192.168.1.100 / T108 / c2023d5d03be91dbb983606f0ec5e9e4ea36c8c2 / . / marvell / linux / arch / arm / boot / dts / asr1903.dtsi
blob: 22bf95682cec5bdef0bfdce020142339ca4761dc [file] [log] [blame]
b.liue9582032025-04-17 19:18:16 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2023 ASR Microelectronics
4 */
5
6#include "asr18xx-pinfunc.h"
7#include <dt-bindings/power/asr-pm.h>
8#include <dt-bindings/clock/asr,asr1803.h>
9#include <dt-bindings/clock/timer-mmp.h>
10#include <dt-bindings/mmc/asr_sdhci.h>
11#include <dt-bindings/phy/phy.h>
12#include <generated/autoconf.h>
13
14/ {
15 #address-cells = <1>;
16 #size-cells = <1>;
17
18 aliases {
19 serial0 = &uart1;
20 serial1 = &uart2;
21 serial2 = &uart3;
22 serial3 = &uart4;
23 i2c0 = &twsi0;
24 i2c1 = &twsi1;
25 i2c2 = &twsi2;
26 };
27
28 soc {
29 #address-cells = <1>;
30 #size-cells = <1>;
31 compatible = "simple-bus";
32 interrupt-parent = <&intc>;
33 ranges;
34 ddr@c0100000 { /* DDR memory controller */
35 compatible = "marvell,devfreq-ddr";
36 reg = <0xc0100000 0x880>,
37 <0xc0158500 0x80>;
38 interrupts = <26>;
39 interrupt-names = "nezas-mc-irq";
40 marvell,qos;
41 clocks = <&soc_clocks ASR1803_CLK_DDR>;
42 clock-names = "ddr";
43 status = "okay";
44 };
45
46 pmu {
47 compatible = "arm,cortex-a7-pmu";
48 interrupts = <23>;
49 };
50
51 axi@d4200000 { /* AXI */
52 compatible = "mrvl,axi-bus", "simple-bus";
53 #address-cells = <1>;
54 #size-cells = <1>;
55 reg = <0xd4200000 0x00200000>;
56 ranges;
57
58 intc: interrupt-controller@d4282000 {
59 compatible = "mrvl,mmp-intc";
60 interrupt-controller;
61 #interrupt-cells = <1>;
62 reg = <0xd4282000 0x1000>;
63 mrvl,intc-nr-irqs = <128>;
64 };
65
66 usb3phy: usb3phy@c0030000 {
67 compatible = "asr,asr-usb3-phy";
68 reg = <0xc0030000 0x1000>;
69 clocks = <&soc_clocks ASR1803_CLK_USB>;
70 clock-names = "usb_clk";
71 status = "disabled";
72 };
73#ifndef CONFIG_USB_DWC3_ASR_OTG
74 usb3_0: usb3-0 {
75 compatible = "asr,dwc3";
76 #address-cells = <1>;
77 #size-cells = <1>;
78 ranges;
79 interrupts = <110 2>;
80 clocks = <&soc_clocks ASR1803_CLK_USB>;
81 clock-names = "usb_clk";
82 status = "disabled";
83 usb_dwc3_0: dwc31@c0000000 {
84 compatible = "snps,dwc3";
85 reg = <0xc0000000 0x21000>;
86 interrupts = <44>;
87 usb-phy = <&usb3phy>;
88 maximum-speed = "high-speed";
89 dr_mode = "peripheral";
90 phy_type = "utmi";
91 lpm-qos = <PM_QOS_CPUIDLE_BLOCK_AXI>;
92 snps,dis_u3_susphy_quirk;
93 /* allow-suspend; */
94 status = "okay";
95 };
96 };
97#else
98 usb3_0_otg: usb3-0-otg {
99 compatible = "asr,dwc3";
100 #address-cells = <1>;
101 #size-cells = <1>;
102 ranges;
103 interrupts = <110 2>;
104 clocks = <&soc_clocks ASR1803_CLK_USB>;
105 clock-names = "usb_clk";
106 lpm-qos = <PM_QOS_CPUIDLE_BLOCK_AXI>;
107 status = "disabled";
108 usb_dwc3_0: dwc31@c0000000 {
109 compatible = "snps,dwc3";
110 reg = <0xc0000000 0x21000>;
111 interrupts = <44 44 44>;
112 interrupt-names = "peripheral",
113 "host",
114 "otg";
115 usb-phy = <&usb3phy>;
116 maximum-speed = "high-speed";
117 dr_mode = "otg";
118 phy_type = "utmi";
119 lpm-qos = <PM_QOS_CPUIDLE_BLOCK_AXI>;
120 snps,dis_u3_susphy_quirk;
121 snps,dis_enblslpm_quirk;
122 snps,dis_u2_susphy_quirk;
123 /* allow-suspend; */
124 status = "okay";
125 };
126 };
127#endif
128 sdh0: sdh@d4280000 {
129 compatible = "asr,sdhci";
130 reg = <0xd4280000 0x200>;
131 interrupts = <39>;
132 clocks = <&soc_clocks ASR1803_CLK_SDH0
133 &soc_clocks ASR1803_CLK_SDH_AXI
134 &soc_clocks ASR1803_CLK_SDH0_TUNE
135 >;
136 clock-names = "sdh-io", "sdh-core", "sdh-fclk-tuned";
137 lpm-qos = <PM_QOS_CPUIDLE_BLOCK_AXI>;
138 status = "disabled";
139 };
140 sdh1: sdh@d4280800 {
141 compatible = "asr,sdhci";
142 reg = <0xd4280800 0x200>;
143 interrupts = <39>;
144 clocks = <&soc_clocks ASR1803_CLK_SDH1
145 &soc_clocks ASR1803_CLK_SDH_AXI
146 &soc_clocks ASR1803_CLK_SDH1_TUNE
147 >;
148 clock-names = "sdh-io", "sdh-core", "sdh-fclk-tuned";
149 lpm-qos = <PM_QOS_CPUIDLE_BLOCK_AXI>;
150 status = "disabled";
151 };
152
153 sram: squ@d1000000 {
154 compatible = "mmio-sram";
155 #address-cells = <1>;
156 #size-cells = <1>;
157 no-memory-wc;
158 reg = <0xd1000000 0x10000>;
159 ranges;
160
161 /* Add reserved area below */
162 sram@d1000000 {
163 /*
164 * 0xd1000000 ~ 0xd10027ff: L1-CP IPC buff
165 * 0xd1002800 ~ 0xd1003fff: audio share mem
166 * 0xd1004000 ~ 0xd1005fff: PS share mem
167 *
168 * Add extra 4KB gap for safe
169 */
170 reg = <0xd1000000 0x7000>;
171 };
172
173 sram@d100ff00 {
174 /* reserved for obm special flags */
175 reg = <0xd100ff00 0x100>;
176 };
177 };
178
179 qspi: spi@0xd420b000 {
180 #address-cells = <1>;
181 #size-cells = <0>;
182 compatible = "asr,qspi";
183 reg = <0xd420b000 0x1000>, <0x80000000 0x8000000>;
184 reg-names = "qspi-base", "qspi-mmap";
185 asr,qspi-sfa1ad = <0x8000000>;
186 asr,qspi-sfa2ad = <0x8000000>;
187 asr,qspi-sfb1ad = <0x8000000>;
188 asr,qspi-sfb2ad = <0x8000000>;
189 clocks = <&soc_clocks ASR1803_CLK_QSPI
190 &soc_clocks ASR1803_CLK_QSPI_DTR
191 &soc_clocks ASR1803_CLK_QSPI_BUS>;
192 clock-names = "qspi_clk", "qspi_clk_dtr", "qspi_bus_clk";
193 asr,qspi-pmuap-reg = <0xd4282860>;
194 /* asr,qspi-id = <0>; */
195 asr,qspi-lpm-qos = <PM_QOS_CPUIDLE_BLOCK_AXI>;
196 interrupts = <45 28>;
197 dmas = <&pdma0 99 0x1c00>;
198 dma-names = "tx-dma";
199 asr,qspi-sram = <&sram>;
200 asr,qspi-support-dtr = <1>;
201 asr,qspi-dtr-tx-delay = <1>;
202 asr,qspi-dtr-rx-delay = <5>;
203 asr,qspi-support-dqs = <1>;
204 status = "disabled";
205 };
206 pcie0: pcie@0xd4288000{
207 compatible = "asr,falcon-pcie";
208 device_type = "pci";
209 #address-cells = <3>;
210 #size-cells = <2>;
211 bus-range = <0x00 0xff>;
212 linux,pci-domain = <0>;
213 reg = <0xd4210000 0x800>, /* Falcon PCIe PHY registers */
214 <0xd4288000 0x1000>; /* Falcon PCIe config space */
215 reg-names = "pciephy", "pciectrl";
216 phys = <&pcieport0 0>;
217 phy-names = "pcie-phy";
218 ranges = <0x81000000 0 0 0xE0010000 0 0x00010000 /* downstream I/O */
219 0x82000000 0 0xE0020000 0xE0020000 0 0x04000000>; /* memory */
220 lpm-qos = <PM_QOS_CPUIDLE_BLOCK_AXI>;
221 num-lanes = <1>;
222 interrupts = <8>;
223 #interrupt-cells = <1>;
224 interrupt-parent = <&intc>;
225 interrupt-map-mask = <0 0 0 0>;
226 interrupt-map = <0 0 0 0 &intc 8>;
227 clocks = <&soc_clocks ASR1803_CLK_PCIE0>;
228 status = "disabled";
229 };
230
231 pciephy0: pcie-phy@d4210000 {
232 compatible = "asr,falcon-pcie-phy";
233 reg = <0xd4210000 0x800>;
234 #address-cells = <1>;
235 #size-cells = <1>;
236 ranges;
237 status = "disabled";
238 pcieport0: pcie-phy@d4210000 {
239 reg = <0xd4210000 0x800>;
240 #phy-cells = <1>;
241 status = "okay";
242 };
243 };
244
245 debug: debug@d42a0000 {
246 compatible = "mrvl,mmp-debug";
247 reg = <0xd42a0000 0x800>;
248 };
249 geu: geu {
250 compatible = "asr,asr-geu";
251 reg = <0xD4201000 0x900>;
252 interrupts = <40>;
253 asr,asr-fuse;
254 asr,asr-aes;
255 asr,asr-hwrng;
256 asr,aes-int-mode;
257 dmas = <&pdma0 68 1
258 &pdma0 69 1>;
259 dma-names = "tx", "rx";
260 clocks = <&soc_clocks ASR1803_CLK_GEU>;
261 lpm-qos = <PM_QOS_CPUIDLE_BLOCK_AXI>;
262 status = "okay";
263 };
264 te200: te200 {
265 compatible = "asr,asr-te200";
266 reg = <0xD4220000 0x3880>;
267 asr,asr-cipher;
268 asr,asr-sha;
269 asr,asr-rsa;
270 interrupts = <40>;
271 clocks = <&soc_clocks ASR1803_CLK_GEU>;
272 lpm-qos = <PM_QOS_CPUIDLE_BLOCK_AXI>;
273 status = "okay";
274 };
275 };
276
277 apb@d4000000 { /* APB */
278 compatible = "mrvl,apb-bus", "simple-bus";
279 #address-cells = <1>;
280 #size-cells = <1>;
281 reg = <0xd4000000 0x00200000>;
282 ranges;
283
284 pdma0: pdma@d4000000 {
285 compatible = "asr,pdma-1.0";
286 reg = <0xd4000000 0x10000>;
287 interrupts = <47>;
288 #dma-cells= <2>;
289 #dma-channels = <32>;
290 #dma-channels-tz = <30>;
291 #dma-channels-dedicated = <0x10000000>;
292 #dma-channels-tz-reserved = <0x0000C000>;
293 lpm-qos = <PM_QOS_CPUIDLE_BLOCK_AXI>;
294 status = "okay";
295 };
296
297 thermal: thermal@d4013300 {
298 compatible = "asr,asr1806-thermal";
299 reg = <0xd4013300 0x3C>;
300 interrupts = <33>;
301 clocks = <&soc_clocks ASR1803_CLK_TSEN>;
302 clock-names = "tsen_clk";
303 polling-mode;
304 polling-interval-ms = <50>;
305 status = "okay";
306 };
307
308 timer0: timer@d4014000 {
309 compatible = "mrvl,mmp-timer";
310 reg = <0xd4014000 0x100>;
311 marvell,timer-id = <0>;
312 marvell,timer-flag = <0>;
313 marvell,timer-fastclk-frequency = <4800000>;
314 marvell,timer-apb-frequency = <104000000>;
315 clocks = <&soc_clocks ASR1803_CLK_TIMER0>;
316
317 counter0 {
318 interrupts = <13>;
319 marvell,timer-counter-id = <0>;
320 marvell,timer-counter-cpu = <0>;
321 marvell,timer-counter-frequency = <4800000>;
322 marvell,timer-counter-usage = <MMP_TIMER_COUNTER_CLKEVT>;
323 marvell,timer-counter-rating = <200>;
324 };
325
326 counter1 {
327 interrupts = <14>;
328 marvell,timer-counter-id = <1>;
329 marvell,timer-counter-frequency = <32768>;
330 marvell,timer-counter-usage = <MMP_TIMER_COUNTER_CLKSRC>;
331 marvell,timer-counter-rating = <200>;
332 };
333
334 counter2 {
335 interrupts = <18>;
336 marvell,timer-counter-id = <2>;
337 marvell,timer-counter-frequency = <4800000>;
338 marvell,timer-counter-usage = <MMP_TIMER_COUNTER_DELAY>;
339 };
340 };
341
342 uart1: uart@d4017000 {
343 compatible = "asr,mmp-uart";
344 reg = <0xd4017000 0x1000>;
345 interrupts = <27>;
346 uart-drcmr-rx = <21>;
347 uart-drcmr-tx = <22>;
348 dmas = <&pdma0 21 1
349 &pdma0 22 1>;
350 dma-names = "rx", "tx";
351 clocks = <&soc_clocks ASR1803_CLK_APUART1>;
352 resets = <&soc_clocks ASR1803_CLK_APUART1>;
353 lpm-qos = <PM_QOS_CPUIDLE_BLOCK_AXI>;
354 status = "disabled";
355 };
356 uart2: uart@d4018000 {
357 compatible = "asr,mmp-uart";
358 reg = <0xd4018000 0x1000>;
359 interrupts = <59>;
360 uart-drcmr-rx = <4>;
361 uart-drcmr-tx = <5>;
362 dmas = <&pdma0 4 1
363 &pdma0 5 1>;
364 dma-names = "rx", "tx";
365 clocks = <&soc_clocks ASR1803_CLK_APUART2>;
366 resets = <&soc_clocks ASR1803_CLK_APUART2>;
367 lpm-qos = <PM_QOS_CPUIDLE_BLOCK_AXI>;
368 status = "disabled";
369 };
370 uart3: uart@d401f000 {
371 compatible = "asr,mmp-uart";
372 reg = <0xd401f000 0x1000>;
373 interrupts = <95>;
374 uart-drcmr-rx = <23>;
375 uart-drcmr-tx = <24>;
376 dmas = <&pdma0 23 1
377 &pdma0 24 1>;
378 dma-names = "rx", "tx";
379 clocks = <&soc_clocks ASR1803_CLK_APUART3>;
380 resets = <&soc_clocks ASR1803_CLK_APUART3>;
381 lpm-qos = <PM_QOS_CPUIDLE_BLOCK_AXI>;
382 status = "disabled";
383 };
384 uart4: uart@d401f800 {
385 compatible = "asr,mmp-uart";
386 reg = <0xd401f800 0x1000>;
387 interrupts = <34>;
388 uart-drcmr-rx = <36>;
389 uart-drcmr-tx = <37>;
390 dmas = <&pdma0 36 1
391 &pdma0 37 1>;
392 dma-names = "rx", "tx";
393 clocks = <&soc_clocks ASR1803_CLK_APUART4>;
394 resets = <&soc_clocks ASR1803_CLK_APUART4>;
395 lpm-qos = <PM_QOS_CPUIDLE_BLOCK_AXI>;
396 status = "disabled";
397 };
398 gpio: gpio@d4019000 {
399 compatible = "marvell,mmp-gpio";
400 #address-cells = <1>;
401 #size-cells = <1>;
402 reg = <0xd4019000 0x1000>;
403 gpio-controller;
404 #gpio-cells = <2>;
405 interrupt-parent = <&intc>;
406 interrupts = <49>;
407 interrupt-controller;
408 #interrupt-cells = <2>;
409 interrupt-names = "gpio_mux";
410 clocks = <&soc_clocks ASR1803_CLK_GPIO>;
411 resets = <&soc_clocks ASR1803_CLK_GPIO>;
412 status = "okay";
413 gpio-ranges = <&pmx 0 55 32>, <&pmx 0 87 23>,
414 <&pmx 3 110 29>, <&pmx 0 139 3 >,
415 <&pmx 28 51 3>;
416 };
417
418 mfpr: mfpr@d401e000 {
419 compatible = "asr,mfp-leftover";
420 pinctrl-names = "default";
421 reg = <0xd401e000 0x280>;
422 /* pinctrl-0 = <&mfp_pins_group_0 &mfp_pins_group_1 &mfp_pins_group_2 >;*/
423 status = "disabled";
424 };
425
426 edgewakeup: edgewakeup@d4019800 {
427 compatible = "mrvl,mmp-edge-wakeup";
428 reg = <0xd4019800 0x10>;
429 status = "okay";
430 };
431
432 twsi0: i2c@d4011000 {
433 compatible = "mrvl,mmp-twsi";
434 #address-cells = <1>;
435 #size-cells = <0>;
436 reg = <0xd4011000 0x60>;
437 interrupts = <7>;
438 lpm-qos = <PM_QOS_CPUIDLE_BLOCK_DDR>;
439 mrvl,i2c-fast-mode;
440 /*
441 *ilcr: fast mode b17~9=0x23, 390k
442 * standard mode b8~0=0x9f, 97k
443 *iwcr: b5~0=b01010 recommended value from spec
444 */
445 marvell,i2c-ilcr = <0x82c469f>;
446 marvell,i2c-iwcr = <0x1434>;
447 pinctrl-names = "default","gpio";
448 pinctrl-0 = <&twsi0_pmx_func>;
449 pinctrl-1 = <&twsi0_pmx_gpio>;
450 i2c-gpio = <&gpio 49 0 &gpio 50 0>;
451 clocks = <&soc_clocks ASR1803_CLK_TWSI0>;
452 clock-names = "twsi0_clk";
453 status = "disabled";
454 };
455
456 twsi1: i2c@d4010800 {
457 compatible = "mrvl,mmp-twsi";
458 #address-cells = <1>;
459 #size-cells = <0>;
460 reg = <0xd4010800 0x60>;
461 interrupts = <15>;
462 lpm-qos = <PM_QOS_CPUIDLE_BLOCK_DDR>;
463 mrvl,i2c-fast-mode;
464 marvell,i2c-ilcr = <0x82c469f>;
465 marvell,i2c-iwcr = <0x1434>;
466 pinctrl-names = "default","gpio";
467 pinctrl-0 = <&twsi1_pmx_func>;
468 pinctrl-1 = <&twsi1_pmx_gpio>;
469 i2c-gpio = <&gpio 10 0 &gpio 11 0>;
470 clocks = <&soc_clocks ASR1803_CLK_TWSI1>;
471 clock-names = "twsi1_clk";
472 status = "disabled";
473 };
474
475 twsi2: i2c@d4037000 {
476 compatible = "mrvl,mmp-twsi";
477 #address-cells = <1>;
478 #size-cells = <0>;
479 reg = <0xd4037000 0x60>,
480 <0xd403d300 0x10>;
481 interrupts = <54>;
482 lpm-qos = <PM_QOS_CPUIDLE_BLOCK_DDR>;
483 marvell,i2c-always-on;
484 mrvl,i2c-fast-mode;
485 marvell,i2c-ilcr = <0x82c469f>;
486 marvell,i2c-iwcr = <0x1434>;
487 soc-bus-reset;
488 clocks = <&soc_clocks ASR1803_CLK_TWSI2>;
489 clock-names = "twsi2_clk";
490 status = "disabled";
491 };
492
493 twsi3: i2c@d403e000 {
494 compatible = "mrvl,mmp-twsi";
495 #address-cells = <1>;
496 #size-cells = <0>;
497 reg = <0xd403e000 0x60>;
498 interrupts = <93>;
499 lpm-qos = <PM_QOS_CPUIDLE_BLOCK_DDR>;
500 mrvl,i2c-fast-mode;
501 marvell,i2c-ilcr = <0x82c469f>;
502 marvell,i2c-iwcr = <0x1434>;
503 /* implement this part in board file
504 pinctrl-names = "default","gpio";
505 pinctrl-0 = <&twsi3_pmx_func>;
506 pinctrl-1 = <&twsi3_pmx_gpio>;
507 i2c-gpio = <&gpio 41 0 &gpio 42 0>; */
508 clocks = <&soc_clocks ASR1803_CLK_TWSI3>;
509 clock-names = "twsi3_clk";
510 status = "disabled";
511 };
512
513 rtc: rtc@d4010000 {
514 compatible = "mrvl,mmp-rtc";
515 reg = <0xd4010000 0x100>;
516 interrupts = <5 6>;
517 interrupt-names = "rtc 1Hz", "rtc alarm";
518 clocks = <&soc_clocks ASR1803_CLK_RTC>;
519 resets = <&soc_clocks ASR1803_CLK_RTC>;
520 status = "disabled";
521 };
522
523 pmx: pinmux@d401e000 {
524 compatible = "pinconf-single";
525 reg = <0xd401e000 0x330>;
526 #address-cells = <1>;
527 #size-cells = <1>;
528 #pinctrl-cells = <1>;
529 #gpio-range-cells = <3>;
530 ranges;
531
532 pinctrl-single,register-width = <32>;
533 pinctrl-single,function-mask = <7>;
534
535 range: gpio-range {
536 #pinctrl-single,gpio-range-cells = <3>;
537 };
538 };
539
540 ssp0: spi@d401b000 {
541 compatible = "asr,asr-spi";
542 #address-cells = <1>;
543 #size-cells = <0>;
544 reg = <0xd401b000 0x30>;
545
546 /* DMA: change 0x10000 to 0x0 in SPI slave mode */
547 dmas = <&pdma0 52 0x10000
548 &pdma0 53 0x10000>;
549 dma-names = "rx", "tx";
550
551 asr,ssp-lpm-qos = <PM_QOS_CPUIDLE_BLOCK_AXI>;
552 asr,ssp-clock-rate = <13000000>;
553 asr,ssp-id = <1>;
554 interrupts = <3>;
555 asr,ssp-enhancement;
556 asr,ssp-disable-dma;
557 /* asr,ssp-slave-mode; */
558 /* asr,slave-rxtimer-to-ms = <0>; */
559 /* asr,ssp-hold-frame-low; */
560 /* asr,spi-master-rxto = <8000>; */
561 /* asr,spi-slave-rxto = <262144>; */
562 /* asr,spi-pio-interval = <5>; */
563 /* asr,spi-1-cycle-delay; */
564 /* asr,spi-cs-comb-ctrl; */
565 clocks = <&soc_clocks ASR1803_CLK_SSP0>;
566 status = "disabled";
567 };
568#if 0
569 ssp1: spi@d401b800 {
570 compatible = "asr,asr-spi";
571 #address-cells = <1>;
572 #size-cells = <0>;
573 reg = <0xd401b800 0x30>;
574
575 /* DMA: change 0x10000 to 0x0 in SPI slave mode */
576 dmas = <&pdma0 54 0x10000
577 &pdma0 55 0x10000>;
578 dma-names = "rx", "tx";
579
580 asr,ssp-lpm-qos = <PM_QOS_CPUIDLE_BLOCK_AXI>;
581 asr,ssp-clock-rate = <13000000>;
582 asr,ssp-id = <2>;
583 interrupts = <2>;
584 asr,ssp-enhancement;
585 /* asr,ssp-disable-dma; */
586 /* asr,ssp-slave-mode; */
587 /* asr,slave-rxtimer-to-ms = <0>; */
588 /* asr,ssp-hold-frame-low; */
589 /* asr,spi-master-rxto = <8000>; */
590 /* asr,spi-slave-rxto = <262144>; */
591 /* asr,spi-pio-interval = <5>; */
592 /* asr,spi-1-cycle-delay; */
593 clocks = <&soc_clocks ASR1803_CLK_SSP1>;
594 status = "disabled";
595 };
596#else
597 ssp1: ssp@d401b800 {
598 status = "okay";
599 compatible = "asr,pxa910-ssp";
600 reg = <0xd401b800 0x90>;
601
602 ssp1-drcmr-rx = <54>;
603 ssp1-drcmr-tx = <55>;
604
605 ssp-id = <2>;
606 interrupts = <0>;
607 clocks = <&soc_clocks ASR1803_CLK_SSP1>;
608 clock-names = "ssp1_mclk";
609 };
610#endif
611 ssp2: spi@d401c000 {
612 compatible = "asr,asr-spi";
613 #address-cells = <1>;
614 #size-cells = <0>;
615 reg = <0xd401c000 0x30>;
616
617 /* DMA: change 0x10000 to 0x0 in SPI slave mode */
618 dmas = <&pdma0 60 0x10000
619 &pdma0 61 0x10000>;
620 dma-names = "rx", "tx";
621
622 asr,ssp-lpm-qos = <PM_QOS_CPUIDLE_BLOCK_AXI>;
623 asr,ssp-clock-rate = <13000000>;
624 asr,ssp-id = <3>;
625 interrupts = <1>;
626 asr,ssp-enhancement;
627 /* asr,ssp-disable-dma; */
628 /* asr,ssp-slave-mode; */
629 /* asr,slave-rxtimer-to-ms = <0>; */
630 /* asr,ssp-hold-frame-low; */
631 /* asr,spi-master-rxto = <8000>; */
632 /* asr,spi-slave-rxto = <262144>; */
633 /* asr,spi-pio-interval = <5>; */
634 /* asr,spi-1-cycle-delay; */
635 clocks = <&soc_clocks ASR1803_CLK_SSP2>;
636 status = "disabled";
637 };
638
639 acipc: acipc@d401d000 {
640 compatible = "mrvl,mmp-acipc";
641 reg = <0xd401d000 0x100>;
642 interrupts = <20>;
643 interrupt-names = "IPC_AP_MUX";
644 status = "okay";
645 };
646
647 seh {
648 compatible = "mrvl,seh";
649 /* <0xd403d300 0x4> is RIPC status register for RIPC lock
650 * when AP-CP sharing PI2C
651 * The CP timer interrupt is not routed to AP on 1802s,
652 * CP use AP timer2@0xD4016000
653 * the d403d000 is used for ripc wakeup by dsp
654 */
655 reg = <0xd4016000 0xD0>, <0xd403d300 0x4>, <0xd403d000 0x4>;
656 interrupts = <19 56>;
657 interrupt-names = "AP_TIMER2_3", "RIPC0_WAKEUP";
658 watchdog-type = <1>; /* wdt AP timer1 */
659 timer-num = <2>; /* timer num */
660 match-num = <0>; /* match num */
661 status = "okay";
662 };
663 sulog: ripc1@d403d100 {
664 compatible = "mrvl,mmp-sulog";
665 #address-cells = <1>;
666 #size-cells = <0>;
667 reg = <0xd403d100 0x20> ,
668 <0xd4050210 0x4>;
669 interrupts = <56>;
670 interrupt-names = "RIPC1_INT";
671 status = "disabled";
672 };
673 cp-load {
674 compatible = "marvell,cp_load";
675 cp-type = <0x30393838>; /* NZ_MODEM */
676 lpm-qos = <PM_QOS_CPUIDLE_BLOCK_AXI>;
677 status = "okay";
678 };
679
680 data-path {
681 compatible = "marvell,data-path";
682 version = <3>;
683 status = "okay";
684 };
685
686 pwm0: pwm@d401a000 {
687 compatible = "marvell,pxa250-pwm";
688 reg = <0xd401a000 0x10>;
689 #pwm-cells = <1>;
690 clocks = <&soc_clocks ASR1803_CLK_PWM0>;
691 clock-names = "pwm0_clk";
692 status = "disabled";
693 };
694
695 pwm1: pwm@d401a400 {
696 compatible = "marvell,pxa250-pwm";
697 reg = <0xd401a400 0x10>;
698 #pwm-cells = <1>;
699 clocks = <&soc_clocks ASR1803_CLK_PWM1>;
700 clock-names = "pwm1_clk";
701 status = "disabled";
702 };
703
704 pwm2: pwm@d401a800 {
705 compatible = "marvell,pxa250-pwm";
706 reg = <0xd401a800 0x10>;
707 #pwm-cells = <1>;
708 clocks = <&soc_clocks ASR1803_CLK_PWM2>;
709 clock-names = "pwm2_clk";
710 status = "disabled";
711 };
712
713 pwm3: pwm@d401ac00 {
714 compatible = "marvell,pxa250-pwm";
715 reg = <0xd401ac00 0x10>;
716 #pwm-cells = <1>;
717 clocks = <&soc_clocks ASR1803_CLK_PWM3>;
718 clock-names = "pwm3_clk";
719 status = "disabled";
720 };
721 auxadc: auxadc@d4013380 {
722 compatible = "asr,auxadc";
723 reg = <0xd4013380 0x80>;
724 clocks = <&soc_clocks ASR1803_CLK_TSEN>;
725 clock-names = "tsen_clk";
726 status = "okay";
727 };
728 };
729
730 soc_clocks: clocks{
731 compatible = "asr,asr1803-clock";
732 reg = <0xd4050000 0x3000>,
733 <0xd4282800 0x400>,
734 <0xd4015000 0x1000>,
735 <0xd403b000 0x1000>,
736 <0xd4090000 0x1000>,
737 <0xd4282c00 0x400>,
738 <0xc0100000 0x5000>;
739 reg-names = "mpmu", "apmu", "apbc", "apbcp", "apbs", "ciu", "ddrc";
740 #clock-cells = <1>;
741 #reset-cells = <1>;
742 };
743 };
744 shared-timer {
745 compatible = "marvell,timer1";
746 dev_name = "timer1_TS";
747 version = "build1";
748 timer-cnt=<2>;
749 reg = <0xD4080000 0xD0>;
750 status = "okay";
751 };
752 regs_addr_ioremap {
753 #address-cells = <1>;
754 #size-cells = <1>;
755 ranges;
756
757 mpmu: pmu@d4050000 {
758 compatible = "marvell,mmp-pmu-mpmu";
759 reg = <0xd4050000 0x2000>;
760 };
761 apmu: pmu@d4282800 {
762 compatible = "marvell,mmp-pmu-apmu";
763 reg = <0xd4282800 0x400>;
764 };
765 apbc: pmu@d4015000 {
766 compatible = "marvell,mmp-pmu-apbc";
767 reg = <0xd4015000 0x100>;
768 };
769 apbs: pmu@d4090000 {
770 compatible = "marvell,mmp-apb-spare";
771 reg = <0xd4090000 0x200>;
772 };
773 ciu: ciu@d4282c00 {
774 compatible = "marvell,mmp-ciu";
775 reg = <0xd4282c00 0x300>;
776 };
777 squ: squ@0xd42a0000 {
778 compatible = "marvell,mmp-squ";
779 reg = <0xd42a0000 0x1000>;
780 };
781 mcu: mcu@0xc0100000 {
782 compatible = "marvell,mmp-mcu";
783 reg = <0xc0100000 0x5000>;
784 };
785 };
786 profile {
787 compatible = "marvell,profile";
788 marvell,profile-number = <0>;
789 };
790
791 mmplog {
792 compatible = "marvell,mmplog-heap";
793 mmplog-base = <0x01f00000>;
794 mmplog-size = <0x8000>;
795 status = "okay";
796 };
797
798 optee-loglevel {
799 compatible = "asr,log-level";
800 status = "ok";
801 };
802};