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192.168.1.100 / T108 / c2023d5d03be91dbb983606f0ec5e9e4ea36c8c2 / . / marvell / linux / arch / arm / boot / dts / imx7d-sdb.dts
blob: 88e62801b82e17147e134915da2acd67b2f9073d [file] [log] [blame]
b.liue9582032025-04-17 19:18:16 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+ OR MIT
2//
3// Copyright (C) 2015 Freescale Semiconductor, Inc.
4
5/dts-v1/;
6
7#include "imx7d.dtsi"
8
9/ {
10 model = "Freescale i.MX7 SabreSD Board";
11 compatible = "fsl,imx7d-sdb", "fsl,imx7d";
12
13 chosen {
14 stdout-path = &uart1;
15 };
16
17 memory@80000000 {
18 device_type = "memory";
19 reg = <0x80000000 0x80000000>;
20 };
21
22 gpio-keys {
23 compatible = "gpio-keys";
24 pinctrl-names = "default";
25 pinctrl-0 = <&pinctrl_gpio_keys>;
26
27 volume-up {
28 label = "Volume Up";
29 gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
30 linux,code = <KEY_VOLUMEUP>;
31 wakeup-source;
32 };
33
34 volume-down {
35 label = "Volume Down";
36 gpios = <&gpio5 10 GPIO_ACTIVE_LOW>;
37 linux,code = <KEY_VOLUMEDOWN>;
38 wakeup-source;
39 };
40 };
41
42 spi4 {
43 compatible = "spi-gpio";
44 pinctrl-names = "default";
45 pinctrl-0 = <&pinctrl_spi4>;
46 gpio-sck = <&gpio1 13 GPIO_ACTIVE_HIGH>;
47 gpio-mosi = <&gpio1 9 GPIO_ACTIVE_HIGH>;
48 cs-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
49 num-chipselects = <1>;
50 #address-cells = <1>;
51 #size-cells = <0>;
52
53 extended_io: gpio-expander@0 {
54 compatible = "fairchild,74hc595";
55 gpio-controller;
56 #gpio-cells = <2>;
57 reg = <0>;
58 registers-number = <1>;
59 spi-max-frequency = <100000>;
60 };
61 };
62
63 reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
64 compatible = "regulator-fixed";
65 regulator-name = "usb_otg1_vbus";
66 regulator-min-microvolt = <5000000>;
67 regulator-max-microvolt = <5000000>;
68 gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
69 enable-active-high;
70 };
71
72 reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
73 compatible = "regulator-fixed";
74 regulator-name = "usb_otg2_vbus";
75 pinctrl-names = "default";
76 pinctrl-0 = <&pinctrl_usb_otg2_vbus_reg>;
77 regulator-min-microvolt = <5000000>;
78 regulator-max-microvolt = <5000000>;
79 gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
80 enable-active-high;
81 };
82
83 reg_vref_1v8: regulator-vref-1v8 {
84 compatible = "regulator-fixed";
85 regulator-name = "vref-1v8";
86 regulator-min-microvolt = <1800000>;
87 regulator-max-microvolt = <1800000>;
88 };
89
90 reg_brcm: regulator-brcm {
91 compatible = "regulator-fixed";
92 gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
93 enable-active-high;
94 regulator-name = "brcm_reg";
95 pinctrl-names = "default";
96 pinctrl-0 = <&pinctrl_brcm_reg>;
97 regulator-min-microvolt = <3300000>;
98 regulator-max-microvolt = <3300000>;
99 startup-delay-us = <200000>;
100 };
101
102 reg_lcd_3v3: regulator-lcd-3v3 {
103 compatible = "regulator-fixed";
104 regulator-name = "lcd-3v3";
105 regulator-min-microvolt = <3300000>;
106 regulator-max-microvolt = <3300000>;
107 gpio = <&extended_io 7 GPIO_ACTIVE_LOW>;
108 };
109
110 reg_can2_3v3: regulator-can2-3v3 {
111 compatible = "regulator-fixed";
112 regulator-name = "can2-3v3";
113 pinctrl-names = "default";
114 pinctrl-0 = <&pinctrl_flexcan2_reg>;
115 regulator-min-microvolt = <3300000>;
116 regulator-max-microvolt = <3300000>;
117 gpio = <&gpio2 14 GPIO_ACTIVE_LOW>;
118 };
119
120 reg_fec2_3v3: regulator-fec2-3v3 {
121 compatible = "regulator-fixed";
122 regulator-name = "fec2-3v3";
123 pinctrl-names = "default";
124 pinctrl-0 = <&pinctrl_enet2_reg>;
125 regulator-min-microvolt = <3300000>;
126 regulator-max-microvolt = <3300000>;
127 gpio = <&gpio1 4 GPIO_ACTIVE_LOW>;
128 };
129
130 backlight: backlight {
131 compatible = "pwm-backlight";
132 pwms = <&pwm1 0 5000000 0>;
133 brightness-levels = <0 4 8 16 32 64 128 255>;
134 default-brightness-level = <6>;
135 status = "okay";
136 };
137
138 panel {
139 compatible = "innolux,at043tn24";
140 backlight = <&backlight>;
141 power-supply = <&reg_lcd_3v3>;
142
143 port {
144 panel_in: endpoint {
145 remote-endpoint = <&display_out>;
146 };
147 };
148 };
149};
150
151&adc1 {
152 vref-supply = <&reg_vref_1v8>;
153 status = "okay";
154};
155
156&adc2 {
157 vref-supply = <&reg_vref_1v8>;
158 status = "okay";
159};
160
161&cpu0 {
162 cpu-supply = <&sw1a_reg>;
163};
164
165&ecspi3 {
166 pinctrl-names = "default";
167 pinctrl-0 = <&pinctrl_ecspi3>;
168 cs-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
169 status = "okay";
170
171 tsc2046@0 {
172 compatible = "ti,tsc2046";
173 reg = <0>;
174 spi-max-frequency = <1000000>;
175 pinctrl-names ="default";
176 pinctrl-0 = <&pinctrl_tsc2046_pendown>;
177 interrupt-parent = <&gpio2>;
178 interrupts = <29 0>;
179 pendown-gpio = <&gpio2 29 GPIO_ACTIVE_LOW>;
180 touchscreen-max-pressure = <255>;
181 wakeup-source;
182 };
183};
184
185&fec1 {
186 pinctrl-names = "default";
187 pinctrl-0 = <&pinctrl_enet1>;
188 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
189 <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
190 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
191 assigned-clock-rates = <0>, <100000000>;
192 phy-mode = "rgmii";
193 phy-handle = <&ethphy0>;
194 fsl,magic-packet;
195 phy-reset-gpios = <&extended_io 5 GPIO_ACTIVE_LOW>;
196 status = "okay";
197
198 mdio {
199 #address-cells = <1>;
200 #size-cells = <0>;
201
202 ethphy0: ethernet-phy@0 {
203 reg = <0>;
204 };
205
206 ethphy1: ethernet-phy@1 {
207 reg = <1>;
208 };
209 };
210};
211
212&fec2 {
213 pinctrl-names = "default";
214 pinctrl-0 = <&pinctrl_enet2>;
215 assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
216 <&clks IMX7D_ENET2_TIME_ROOT_CLK>;
217 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
218 assigned-clock-rates = <0>, <100000000>;
219 phy-mode = "rgmii";
220 phy-handle = <&ethphy1>;
221 phy-supply = <&reg_fec2_3v3>;
222 fsl,magic-packet;
223 status = "okay";
224};
225
226&flexcan2 {
227 pinctrl-names = "default";
228 pinctrl-0 = <&pinctrl_flexcan2>;
229 xceiver-supply = <&reg_can2_3v3>;
230 status = "okay";
231};
232
233&i2c1 {
234 pinctrl-names = "default";
235 pinctrl-0 = <&pinctrl_i2c1>;
236 status = "okay";
237
238 pmic: pfuze3000@8 {
239 compatible = "fsl,pfuze3000";
240 reg = <0x08>;
241
242 regulators {
243 sw1a_reg: sw1a {
244 regulator-min-microvolt = <700000>;
245 regulator-max-microvolt = <1475000>;
246 regulator-boot-on;
247 regulator-always-on;
248 regulator-ramp-delay = <6250>;
249 };
250
251 /* use sw1c_reg to align with pfuze100/pfuze200 */
252 sw1c_reg: sw1b {
253 regulator-min-microvolt = <700000>;
254 regulator-max-microvolt = <1475000>;
255 regulator-boot-on;
256 regulator-always-on;
257 regulator-ramp-delay = <6250>;
258 };
259
260 sw2_reg: sw2 {
261 regulator-min-microvolt = <1800000>;
262 regulator-max-microvolt = <1800000>;
263 regulator-boot-on;
264 regulator-always-on;
265 };
266
267 sw3a_reg: sw3 {
268 regulator-min-microvolt = <900000>;
269 regulator-max-microvolt = <1650000>;
270 regulator-boot-on;
271 regulator-always-on;
272 };
273
274 swbst_reg: swbst {
275 regulator-min-microvolt = <5000000>;
276 regulator-max-microvolt = <5150000>;
277 };
278
279 snvs_reg: vsnvs {
280 regulator-min-microvolt = <1000000>;
281 regulator-max-microvolt = <3000000>;
282 regulator-boot-on;
283 regulator-always-on;
284 };
285
286 vref_reg: vrefddr {
287 regulator-boot-on;
288 regulator-always-on;
289 };
290
291 vgen1_reg: vldo1 {
292 regulator-min-microvolt = <1800000>;
293 regulator-max-microvolt = <3300000>;
294 regulator-always-on;
295 };
296
297 vgen2_reg: vldo2 {
298 regulator-min-microvolt = <800000>;
299 regulator-max-microvolt = <1550000>;
300 };
301
302 vgen3_reg: vccsd {
303 regulator-min-microvolt = <2850000>;
304 regulator-max-microvolt = <3300000>;
305 regulator-always-on;
306 };
307
308 vgen4_reg: v33 {
309 regulator-min-microvolt = <2850000>;
310 regulator-max-microvolt = <3300000>;
311 regulator-always-on;
312 };
313
314 vgen5_reg: vldo3 {
315 regulator-min-microvolt = <1800000>;
316 regulator-max-microvolt = <3300000>;
317 regulator-always-on;
318 };
319
320 vgen6_reg: vldo4 {
321 regulator-min-microvolt = <2800000>;
322 regulator-max-microvolt = <2800000>;
323 regulator-always-on;
324 };
325 };
326 };
327};
328
329&i2c2 {
330 pinctrl-names = "default";
331 pinctrl-0 = <&pinctrl_i2c2>;
332 status = "okay";
333
334 mpl3115@60 {
335 compatible = "fsl,mpl3115";
336 reg = <0x60>;
337 };
338};
339
340&i2c3 {
341 pinctrl-names = "default";
342 pinctrl-0 = <&pinctrl_i2c3>;
343 status = "okay";
344};
345
346&i2c4 {
347 pinctrl-names = "default";
348 pinctrl-0 = <&pinctrl_i2c4>;
349 status = "okay";
350
351 codec: wm8960@1a {
352 compatible = "wlf,wm8960";
353 reg = <0x1a>;
354 clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>;
355 clock-names = "mclk";
356 wlf,shared-lrclk;
357 };
358};
359
360&lcdif {
361 pinctrl-names = "default";
362 pinctrl-0 = <&pinctrl_lcdif>;
363 status = "okay";
364
365 port {
366 display_out: endpoint {
367 remote-endpoint = <&panel_in>;
368 };
369 };
370};
371
372&pcie {
373 reset-gpio = <&extended_io 1 GPIO_ACTIVE_LOW>;
374 status = "okay";
375};
376
377&reg_1p0d {
378 vin-supply = <&sw2_reg>;
379};
380
381&reg_1p2 {
382 vin-supply = <&sw2_reg>;
383};
384
385&snvs_pwrkey {
386 status = "okay";
387};
388
389&uart1 {
390 pinctrl-names = "default";
391 pinctrl-0 = <&pinctrl_uart1>;
392 assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
393 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
394 status = "okay";
395};
396
397&uart6 {
398 pinctrl-names = "default";
399 pinctrl-0 = <&pinctrl_uart6>;
400 assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
401 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
402 uart-has-rtscts;
403 status = "okay";
404};
405
406&usbotg1 {
407 vbus-supply = <&reg_usb_otg1_vbus>;
408 status = "okay";
409};
410
411&usbotg2 {
412 vbus-supply = <&reg_usb_otg2_vbus>;
413 dr_mode = "host";
414 status = "okay";
415};
416
417&usdhc1 {
418 pinctrl-names = "default";
419 pinctrl-0 = <&pinctrl_usdhc1>;
420 cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
421 wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
422 wakeup-source;
423 keep-power-in-suspend;
424 status = "okay";
425};
426
427&usdhc2 {
428 pinctrl-names = "default", "state_100mhz", "state_200mhz";
429 pinctrl-0 = <&pinctrl_usdhc2>;
430 pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
431 pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
432 wakeup-source;
433 keep-power-in-suspend;
434 non-removable;
435 vmmc-supply = <&reg_brcm>;
436 fsl,tuning-step = <2>;
437 status = "okay";
438};
439
440&usdhc3 {
441 pinctrl-names = "default", "state_100mhz", "state_200mhz";
442 pinctrl-0 = <&pinctrl_usdhc3>;
443 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
444 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
445 assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
446 assigned-clock-rates = <400000000>;
447 bus-width = <8>;
448 fsl,tuning-step = <2>;
449 non-removable;
450 status = "okay";
451};
452
453&wdog1 {
454 pinctrl-names = "default";
455 pinctrl-0 = <&pinctrl_wdog>;
456 fsl,ext-reset-output;
457};
458
459&iomuxc {
460 pinctrl-names = "default";
461 pinctrl-0 = <&pinctrl_hog>;
462
463 imx7d-sdb {
464 pinctrl_brcm_reg: brcmreggrp {
465 fsl,pins = <
466 MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x14
467 >;
468 };
469
470 pinctrl_ecspi3: ecspi3grp {
471 fsl,pins = <
472 MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO 0x2
473 MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI 0x2
474 MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK 0x2
475 MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x59
476 >;
477 };
478
479 pinctrl_enet1: enet1grp {
480 fsl,pins = <
481 MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x3
482 MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x3
483 MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1
484 MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1
485 MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1
486 MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1
487 MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1
488 MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1
489 MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1
490 MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1
491 MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1
492 MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1
493 MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1
494 MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1
495 >;
496 };
497
498 pinctrl_enet2: enet2grp {
499 fsl,pins = <
500 MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x1
501 MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x1
502 MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x1
503 MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x1
504 MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x1
505 MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x1
506 MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x1
507 MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x1
508 MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x1
509 MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x1
510 MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x1
511 MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x1
512 >;
513 };
514
515 pinctrl_enet2_reg: enet2reggrp {
516 fsl,pins = <
517 MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x14
518 >;
519 };
520
521 pinctrl_flexcan2: flexcan2grp {
522 fsl,pins = <
523 MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x59
524 MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x59
525 >;
526 };
527
528 pinctrl_flexcan2_reg: flexcan2reggrp {
529 fsl,pins = <
530 MX7D_PAD_EPDC_DATA14__GPIO2_IO14 0x59 /* CAN_STBY */
531 >;
532 };
533
534 pinctrl_gpio_keys: gpio_keysgrp {
535 fsl,pins = <
536 MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x59
537 MX7D_PAD_SD2_WP__GPIO5_IO10 0x59
538 >;
539 };
540
541 pinctrl_hog: hoggrp {
542 fsl,pins = <
543 MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x34 /* bt reg on */
544 >;
545 };
546
547 pinctrl_i2c1: i2c1grp {
548 fsl,pins = <
549 MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f
550 MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f
551 >;
552 };
553
554 pinctrl_i2c2: i2c2grp {
555 fsl,pins = <
556 MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f
557 MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f
558 >;
559 };
560
561 pinctrl_i2c3: i2c3grp {
562 fsl,pins = <
563 MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f
564 MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f
565 >;
566 };
567
568 pinctrl_i2c4: i2c4grp {
569 fsl,pins = <
570 MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x4000007f
571 MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x4000007f
572 >;
573 };
574
575 pinctrl_lcdif: lcdifgrp {
576 fsl,pins = <
577 MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79
578 MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79
579 MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79
580 MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79
581 MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79
582 MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79
583 MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79
584 MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79
585 MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79
586 MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79
587 MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79
588 MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79
589 MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79
590 MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79
591 MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79
592 MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79
593 MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79
594 MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79
595 MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79
596 MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79
597 MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79
598 MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79
599 MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79
600 MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79
601 MX7D_PAD_LCD_CLK__LCD_CLK 0x79
602 MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79
603 MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79
604 MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79
605 MX7D_PAD_LCD_RESET__LCD_RESET 0x79
606 >;
607 };
608
609 pinctrl_spi4: spi4grp {
610 fsl,pins = <
611 MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x59
612 MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x59
613 MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x59
614 >;
615 };
616
617 pinctrl_tsc2046_pendown: tsc2046_pendown {
618 fsl,pins = <
619 MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x59
620 >;
621 };
622
623 pinctrl_uart1: uart1grp {
624 fsl,pins = <
625 MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79
626 MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79
627 >;
628 };
629
630 pinctrl_uart5: uart5grp {
631 fsl,pins = <
632 MX7D_PAD_SAI1_TX_BCLK__UART5_DCE_TX 0x79
633 MX7D_PAD_SAI1_RX_DATA__UART5_DCE_RX 0x79
634 MX7D_PAD_SAI1_TX_SYNC__UART5_DCE_CTS 0x79
635 MX7D_PAD_SAI1_TX_DATA__UART5_DCE_RTS 0x79
636 >;
637 };
638
639 pinctrl_uart6: uart6grp {
640 fsl,pins = <
641 MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX 0x79
642 MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX 0x79
643 MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS 0x79
644 MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS 0x79
645 >;
646 };
647
648 pinctrl_usdhc1: usdhc1grp {
649 fsl,pins = <
650 MX7D_PAD_SD1_CMD__SD1_CMD 0x59
651 MX7D_PAD_SD1_CLK__SD1_CLK 0x19
652 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
653 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
654 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
655 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
656 MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */
657 MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */
658 MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */
659 >;
660 };
661
662 pinctrl_usdhc2: usdhc2grp {
663 fsl,pins = <
664 MX7D_PAD_SD2_CMD__SD2_CMD 0x59
665 MX7D_PAD_SD2_CLK__SD2_CLK 0x19
666 MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59
667 MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59
668 MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59
669 MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59
670 >;
671 };
672
673 pinctrl_usdhc2_100mhz: usdhc2grp_100mhz {
674 fsl,pins = <
675 MX7D_PAD_SD2_CMD__SD2_CMD 0x5a
676 MX7D_PAD_SD2_CLK__SD2_CLK 0x1a
677 MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5a
678 MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5a
679 MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5a
680 MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5a
681 >;
682 };
683
684 pinctrl_usdhc2_200mhz: usdhc2grp_200mhz {
685 fsl,pins = <
686 MX7D_PAD_SD2_CMD__SD2_CMD 0x5b
687 MX7D_PAD_SD2_CLK__SD2_CLK 0x1b
688 MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5b
689 MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5b
690 MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5b
691 MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5b
692 >;
693 };
694
695
696 pinctrl_usdhc3: usdhc3grp {
697 fsl,pins = <
698 MX7D_PAD_SD3_CMD__SD3_CMD 0x59
699 MX7D_PAD_SD3_CLK__SD3_CLK 0x19
700 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
701 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
702 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
703 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
704 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
705 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
706 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
707 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
708 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19
709 >;
710 };
711
712 pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
713 fsl,pins = <
714 MX7D_PAD_SD3_CMD__SD3_CMD 0x5a
715 MX7D_PAD_SD3_CLK__SD3_CLK 0x1a
716 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a
717 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a
718 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a
719 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a
720 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a
721 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a
722 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a
723 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a
724 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a
725 >;
726 };
727
728 pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
729 fsl,pins = <
730 MX7D_PAD_SD3_CMD__SD3_CMD 0x5b
731 MX7D_PAD_SD3_CLK__SD3_CLK 0x1b
732 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b
733 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b
734 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b
735 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b
736 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b
737 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b
738 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b
739 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b
740 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b
741 >;
742 };
743 };
744};
745
746&pwm1 {
747 pinctrl-names = "default";
748 pinctrl-0 = <&pinctrl_pwm1>;
749 status = "okay";
750};
751
752&iomuxc_lpsr {
753 pinctrl_wdog: wdoggrp {
754 fsl,pins = <
755 MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74
756 >;
757 };
758
759 pinctrl_pwm1: pwm1grp {
760 fsl,pins = <
761 MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x30
762 >;
763 };
764
765 pinctrl_usb_otg2_vbus_reg: usbotg2vbusreggrp {
766 fsl,pins = <
767 MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x14
768 >;
769 };
770};