| b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
| 2 | /* |
| 3 | * plat smp support for CSR Marco dual-core SMP SoCs |
| 4 | * |
| 5 | * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company. |
| 6 | */ |
| 7 | |
| 8 | #include <linux/init.h> |
| 9 | #include <linux/smp.h> |
| 10 | #include <linux/delay.h> |
| 11 | #include <linux/of.h> |
| 12 | #include <linux/of_address.h> |
| 13 | #include <asm/page.h> |
| 14 | #include <asm/mach/map.h> |
| 15 | #include <asm/smp_plat.h> |
| 16 | #include <asm/smp_scu.h> |
| 17 | #include <asm/cacheflush.h> |
| 18 | #include <asm/cputype.h> |
| 19 | |
| 20 | #include "common.h" |
| 21 | |
| 22 | static void __iomem *clk_base; |
| 23 | |
| 24 | static DEFINE_SPINLOCK(boot_lock); |
| 25 | |
| 26 | /* XXX prima2_pen_release is cargo culted code - DO NOT COPY XXX */ |
| 27 | volatile int prima2_pen_release = -1; |
| 28 | |
| 29 | static void sirfsoc_secondary_init(unsigned int cpu) |
| 30 | { |
| 31 | /* |
| 32 | * let the primary processor know we're out of the |
| 33 | * pen, then head off into the C entry point |
| 34 | */ |
| 35 | prima2_pen_release = -1; |
| 36 | smp_wmb(); |
| 37 | |
| 38 | /* |
| 39 | * Synchronise with the boot thread. |
| 40 | */ |
| 41 | spin_lock(&boot_lock); |
| 42 | spin_unlock(&boot_lock); |
| 43 | } |
| 44 | |
| 45 | static const struct of_device_id clk_ids[] = { |
| 46 | { .compatible = "sirf,atlas7-clkc" }, |
| 47 | {}, |
| 48 | }; |
| 49 | |
| 50 | static int sirfsoc_boot_secondary(unsigned int cpu, struct task_struct *idle) |
| 51 | { |
| 52 | unsigned long timeout; |
| 53 | struct device_node *np; |
| 54 | |
| 55 | np = of_find_matching_node(NULL, clk_ids); |
| 56 | if (!np) |
| 57 | return -ENODEV; |
| 58 | |
| 59 | clk_base = of_iomap(np, 0); |
| 60 | if (!clk_base) |
| 61 | return -ENOMEM; |
| 62 | |
| 63 | /* |
| 64 | * write the address of secondary startup into the clkc register |
| 65 | * at offset 0x2bC, then write the magic number 0x3CAF5D62 to the |
| 66 | * clkc register at offset 0x2b8, which is what boot rom code is |
| 67 | * waiting for. This would wake up the secondary core from WFE |
| 68 | */ |
| 69 | #define SIRFSOC_CPU1_JUMPADDR_OFFSET 0x2bc |
| 70 | __raw_writel(__pa_symbol(sirfsoc_secondary_startup), |
| 71 | clk_base + SIRFSOC_CPU1_JUMPADDR_OFFSET); |
| 72 | |
| 73 | #define SIRFSOC_CPU1_WAKEMAGIC_OFFSET 0x2b8 |
| 74 | __raw_writel(0x3CAF5D62, |
| 75 | clk_base + SIRFSOC_CPU1_WAKEMAGIC_OFFSET); |
| 76 | |
| 77 | /* make sure write buffer is drained */ |
| 78 | mb(); |
| 79 | |
| 80 | spin_lock(&boot_lock); |
| 81 | |
| 82 | /* |
| 83 | * The secondary processor is waiting to be released from |
| 84 | * the holding pen - release it, then wait for it to flag |
| 85 | * that it has been released by resetting prima2_pen_release. |
| 86 | * |
| 87 | * Note that "prima2_pen_release" is the hardware CPU ID, whereas |
| 88 | * "cpu" is Linux's internal ID. |
| 89 | */ |
| 90 | prima2_pen_release = cpu_logical_map(cpu); |
| 91 | sync_cache_w(&prima2_pen_release); |
| 92 | |
| 93 | /* |
| 94 | * Send the secondary CPU SEV, thereby causing the boot monitor to read |
| 95 | * the JUMPADDR and WAKEMAGIC, and branch to the address found there. |
| 96 | */ |
| 97 | dsb_sev(); |
| 98 | |
| 99 | timeout = jiffies + (1 * HZ); |
| 100 | while (time_before(jiffies, timeout)) { |
| 101 | smp_rmb(); |
| 102 | if (prima2_pen_release == -1) |
| 103 | break; |
| 104 | |
| 105 | udelay(10); |
| 106 | } |
| 107 | |
| 108 | /* |
| 109 | * now the secondary core is starting up let it run its |
| 110 | * calibrations, then wait for it to finish |
| 111 | */ |
| 112 | spin_unlock(&boot_lock); |
| 113 | |
| 114 | return prima2_pen_release != -1 ? -ENOSYS : 0; |
| 115 | } |
| 116 | |
| 117 | const struct smp_operations sirfsoc_smp_ops __initconst = { |
| 118 | .smp_secondary_init = sirfsoc_secondary_init, |
| 119 | .smp_boot_secondary = sirfsoc_boot_secondary, |
| 120 | #ifdef CONFIG_HOTPLUG_CPU |
| 121 | .cpu_die = sirfsoc_cpu_die, |
| 122 | #endif |
| 123 | }; |