| b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* |
| 3 | * Copyright (c) 2003-2004 Simtec Electronics <linux@simtec.co.uk> |
| 4 | * http://www.simtec.co.uk/products/SWLINUX/ |
| 5 | * |
| 6 | * S3C2410 GPIO register definitions |
| 7 | */ |
| 8 | |
| 9 | |
| 10 | #ifndef __ASM_ARCH_REGS_GPIO_H |
| 11 | #define __ASM_ARCH_REGS_GPIO_H |
| 12 | |
| 13 | #define S3C24XX_MISCCR S3C24XX_GPIOREG2(0x80) |
| 14 | |
| 15 | /* general configuration options */ |
| 16 | |
| 17 | #define S3C2410_GPIO_LEAVE (0xFFFFFFFF) |
| 18 | #define S3C2410_GPIO_INPUT (0xFFFFFFF0) /* not available on A */ |
| 19 | #define S3C2410_GPIO_OUTPUT (0xFFFFFFF1) |
| 20 | #define S3C2410_GPIO_IRQ (0xFFFFFFF2) /* not available for all */ |
| 21 | #define S3C2410_GPIO_SFN2 (0xFFFFFFF2) /* bank A => addr/cs/nand */ |
| 22 | #define S3C2410_GPIO_SFN3 (0xFFFFFFF3) /* not available on A */ |
| 23 | |
| 24 | /* register address for the GPIO registers. |
| 25 | * S3C24XX_GPIOREG2 is for the second set of registers in the |
| 26 | * GPIO which move between s3c2410 and s3c2412 type systems */ |
| 27 | |
| 28 | #define S3C2410_GPIOREG(x) ((x) + S3C24XX_VA_GPIO) |
| 29 | #define S3C24XX_GPIOREG2(x) ((x) + S3C24XX_VA_GPIO2) |
| 30 | |
| 31 | |
| 32 | /* configure GPIO ports A..G */ |
| 33 | |
| 34 | /* port A - S3C2410: 22bits, zero in bit X makes pin X output |
| 35 | * 1 makes port special function, this is default |
| 36 | */ |
| 37 | #define S3C2410_GPACON S3C2410_GPIOREG(0x00) |
| 38 | #define S3C2410_GPADAT S3C2410_GPIOREG(0x04) |
| 39 | |
| 40 | #define S3C2410_GPA0_ADDR0 (1<<0) |
| 41 | #define S3C2410_GPA1_ADDR16 (1<<1) |
| 42 | #define S3C2410_GPA2_ADDR17 (1<<2) |
| 43 | #define S3C2410_GPA3_ADDR18 (1<<3) |
| 44 | #define S3C2410_GPA4_ADDR19 (1<<4) |
| 45 | #define S3C2410_GPA5_ADDR20 (1<<5) |
| 46 | #define S3C2410_GPA6_ADDR21 (1<<6) |
| 47 | #define S3C2410_GPA7_ADDR22 (1<<7) |
| 48 | #define S3C2410_GPA8_ADDR23 (1<<8) |
| 49 | #define S3C2410_GPA9_ADDR24 (1<<9) |
| 50 | #define S3C2410_GPA10_ADDR25 (1<<10) |
| 51 | #define S3C2410_GPA11_ADDR26 (1<<11) |
| 52 | #define S3C2410_GPA12_nGCS1 (1<<12) |
| 53 | #define S3C2410_GPA13_nGCS2 (1<<13) |
| 54 | #define S3C2410_GPA14_nGCS3 (1<<14) |
| 55 | #define S3C2410_GPA15_nGCS4 (1<<15) |
| 56 | #define S3C2410_GPA16_nGCS5 (1<<16) |
| 57 | #define S3C2410_GPA17_CLE (1<<17) |
| 58 | #define S3C2410_GPA18_ALE (1<<18) |
| 59 | #define S3C2410_GPA19_nFWE (1<<19) |
| 60 | #define S3C2410_GPA20_nFRE (1<<20) |
| 61 | #define S3C2410_GPA21_nRSTOUT (1<<21) |
| 62 | #define S3C2410_GPA22_nFCE (1<<22) |
| 63 | |
| 64 | /* 0x08 and 0x0c are reserved on S3C2410 */ |
| 65 | |
| 66 | /* S3C2410: |
| 67 | * GPB is 10 IO pins, each configured by 2 bits each in GPBCON. |
| 68 | * 00 = input, 01 = output, 10=special function, 11=reserved |
| 69 | |
| 70 | * bit 0,1 = pin 0, 2,3= pin 1... |
| 71 | * |
| 72 | * CPBUP = pull up resistor control, 1=disabled, 0=enabled |
| 73 | */ |
| 74 | |
| 75 | #define S3C2410_GPBCON S3C2410_GPIOREG(0x10) |
| 76 | #define S3C2410_GPBDAT S3C2410_GPIOREG(0x14) |
| 77 | #define S3C2410_GPBUP S3C2410_GPIOREG(0x18) |
| 78 | |
| 79 | /* no i/o pin in port b can have value 3 (unless it is a s3c2443) ! */ |
| 80 | |
| 81 | #define S3C2410_GPB0_TOUT0 (0x02 << 0) |
| 82 | |
| 83 | #define S3C2410_GPB1_TOUT1 (0x02 << 2) |
| 84 | |
| 85 | #define S3C2410_GPB2_TOUT2 (0x02 << 4) |
| 86 | |
| 87 | #define S3C2410_GPB3_TOUT3 (0x02 << 6) |
| 88 | |
| 89 | #define S3C2410_GPB4_TCLK0 (0x02 << 8) |
| 90 | #define S3C2410_GPB4_MASK (0x03 << 8) |
| 91 | |
| 92 | #define S3C2410_GPB5_nXBACK (0x02 << 10) |
| 93 | #define S3C2443_GPB5_XBACK (0x03 << 10) |
| 94 | |
| 95 | #define S3C2410_GPB6_nXBREQ (0x02 << 12) |
| 96 | #define S3C2443_GPB6_XBREQ (0x03 << 12) |
| 97 | |
| 98 | #define S3C2410_GPB7_nXDACK1 (0x02 << 14) |
| 99 | #define S3C2443_GPB7_XDACK1 (0x03 << 14) |
| 100 | |
| 101 | #define S3C2410_GPB8_nXDREQ1 (0x02 << 16) |
| 102 | |
| 103 | #define S3C2410_GPB9_nXDACK0 (0x02 << 18) |
| 104 | #define S3C2443_GPB9_XDACK0 (0x03 << 18) |
| 105 | |
| 106 | #define S3C2410_GPB10_nXDRE0 (0x02 << 20) |
| 107 | #define S3C2443_GPB10_XDREQ0 (0x03 << 20) |
| 108 | |
| 109 | #define S3C2410_GPB_PUPDIS(x) (1<<(x)) |
| 110 | |
| 111 | /* Port C consits of 16 GPIO/Special function |
| 112 | * |
| 113 | * almost identical setup to port b, but the special functions are mostly |
| 114 | * to do with the video system's sync/etc. |
| 115 | */ |
| 116 | |
| 117 | #define S3C2410_GPCCON S3C2410_GPIOREG(0x20) |
| 118 | #define S3C2410_GPCDAT S3C2410_GPIOREG(0x24) |
| 119 | #define S3C2410_GPCUP S3C2410_GPIOREG(0x28) |
| 120 | #define S3C2410_GPC0_LEND (0x02 << 0) |
| 121 | #define S3C2410_GPC1_VCLK (0x02 << 2) |
| 122 | #define S3C2410_GPC2_VLINE (0x02 << 4) |
| 123 | #define S3C2410_GPC3_VFRAME (0x02 << 6) |
| 124 | #define S3C2410_GPC4_VM (0x02 << 8) |
| 125 | #define S3C2410_GPC5_LCDVF0 (0x02 << 10) |
| 126 | #define S3C2410_GPC6_LCDVF1 (0x02 << 12) |
| 127 | #define S3C2410_GPC7_LCDVF2 (0x02 << 14) |
| 128 | #define S3C2410_GPC8_VD0 (0x02 << 16) |
| 129 | #define S3C2410_GPC9_VD1 (0x02 << 18) |
| 130 | #define S3C2410_GPC10_VD2 (0x02 << 20) |
| 131 | #define S3C2410_GPC11_VD3 (0x02 << 22) |
| 132 | #define S3C2410_GPC12_VD4 (0x02 << 24) |
| 133 | #define S3C2410_GPC13_VD5 (0x02 << 26) |
| 134 | #define S3C2410_GPC14_VD6 (0x02 << 28) |
| 135 | #define S3C2410_GPC15_VD7 (0x02 << 30) |
| 136 | #define S3C2410_GPC_PUPDIS(x) (1<<(x)) |
| 137 | |
| 138 | /* |
| 139 | * S3C2410: Port D consists of 16 GPIO/Special function |
| 140 | * |
| 141 | * almost identical setup to port b, but the special functions are mostly |
| 142 | * to do with the video system's data. |
| 143 | * |
| 144 | * almost identical setup to port c |
| 145 | */ |
| 146 | |
| 147 | #define S3C2410_GPDCON S3C2410_GPIOREG(0x30) |
| 148 | #define S3C2410_GPDDAT S3C2410_GPIOREG(0x34) |
| 149 | #define S3C2410_GPDUP S3C2410_GPIOREG(0x38) |
| 150 | |
| 151 | #define S3C2410_GPD0_VD8 (0x02 << 0) |
| 152 | #define S3C2442_GPD0_nSPICS1 (0x03 << 0) |
| 153 | |
| 154 | #define S3C2410_GPD1_VD9 (0x02 << 2) |
| 155 | #define S3C2442_GPD1_SPICLK1 (0x03 << 2) |
| 156 | |
| 157 | #define S3C2410_GPD2_VD10 (0x02 << 4) |
| 158 | |
| 159 | #define S3C2410_GPD3_VD11 (0x02 << 6) |
| 160 | |
| 161 | #define S3C2410_GPD4_VD12 (0x02 << 8) |
| 162 | |
| 163 | #define S3C2410_GPD5_VD13 (0x02 << 10) |
| 164 | |
| 165 | #define S3C2410_GPD6_VD14 (0x02 << 12) |
| 166 | |
| 167 | #define S3C2410_GPD7_VD15 (0x02 << 14) |
| 168 | |
| 169 | #define S3C2410_GPD8_VD16 (0x02 << 16) |
| 170 | #define S3C2440_GPD8_SPIMISO1 (0x03 << 16) |
| 171 | |
| 172 | #define S3C2410_GPD9_VD17 (0x02 << 18) |
| 173 | #define S3C2440_GPD9_SPIMOSI1 (0x03 << 18) |
| 174 | |
| 175 | #define S3C2410_GPD10_VD18 (0x02 << 20) |
| 176 | #define S3C2440_GPD10_SPICLK1 (0x03 << 20) |
| 177 | |
| 178 | #define S3C2410_GPD11_VD19 (0x02 << 22) |
| 179 | |
| 180 | #define S3C2410_GPD12_VD20 (0x02 << 24) |
| 181 | |
| 182 | #define S3C2410_GPD13_VD21 (0x02 << 26) |
| 183 | |
| 184 | #define S3C2410_GPD14_VD22 (0x02 << 28) |
| 185 | #define S3C2410_GPD14_nSS1 (0x03 << 28) |
| 186 | |
| 187 | #define S3C2410_GPD15_VD23 (0x02 << 30) |
| 188 | #define S3C2410_GPD15_nSS0 (0x03 << 30) |
| 189 | |
| 190 | #define S3C2410_GPD_PUPDIS(x) (1<<(x)) |
| 191 | |
| 192 | /* S3C2410: |
| 193 | * Port E consists of 16 GPIO/Special function |
| 194 | * |
| 195 | * again, the same as port B, but dealing with I2S, SDI, and |
| 196 | * more miscellaneous functions |
| 197 | * |
| 198 | * GPIO / interrupt inputs |
| 199 | */ |
| 200 | |
| 201 | #define S3C2410_GPECON S3C2410_GPIOREG(0x40) |
| 202 | #define S3C2410_GPEDAT S3C2410_GPIOREG(0x44) |
| 203 | #define S3C2410_GPEUP S3C2410_GPIOREG(0x48) |
| 204 | |
| 205 | #define S3C2410_GPE0_I2SLRCK (0x02 << 0) |
| 206 | #define S3C2443_GPE0_AC_nRESET (0x03 << 0) |
| 207 | #define S3C2410_GPE0_MASK (0x03 << 0) |
| 208 | |
| 209 | #define S3C2410_GPE1_I2SSCLK (0x02 << 2) |
| 210 | #define S3C2443_GPE1_AC_SYNC (0x03 << 2) |
| 211 | #define S3C2410_GPE1_MASK (0x03 << 2) |
| 212 | |
| 213 | #define S3C2410_GPE2_CDCLK (0x02 << 4) |
| 214 | #define S3C2443_GPE2_AC_BITCLK (0x03 << 4) |
| 215 | |
| 216 | #define S3C2410_GPE3_I2SSDI (0x02 << 6) |
| 217 | #define S3C2443_GPE3_AC_SDI (0x03 << 6) |
| 218 | #define S3C2410_GPE3_nSS0 (0x03 << 6) |
| 219 | #define S3C2410_GPE3_MASK (0x03 << 6) |
| 220 | |
| 221 | #define S3C2410_GPE4_I2SSDO (0x02 << 8) |
| 222 | #define S3C2443_GPE4_AC_SDO (0x03 << 8) |
| 223 | #define S3C2410_GPE4_I2SSDI (0x03 << 8) |
| 224 | #define S3C2410_GPE4_MASK (0x03 << 8) |
| 225 | |
| 226 | #define S3C2410_GPE5_SDCLK (0x02 << 10) |
| 227 | #define S3C2443_GPE5_SD1_CLK (0x02 << 10) |
| 228 | #define S3C2443_GPE5_AC_BITCLK (0x03 << 10) |
| 229 | |
| 230 | #define S3C2410_GPE6_SDCMD (0x02 << 12) |
| 231 | #define S3C2443_GPE6_SD1_CMD (0x02 << 12) |
| 232 | #define S3C2443_GPE6_AC_SDI (0x03 << 12) |
| 233 | |
| 234 | #define S3C2410_GPE7_SDDAT0 (0x02 << 14) |
| 235 | #define S3C2443_GPE5_SD1_DAT0 (0x02 << 14) |
| 236 | #define S3C2443_GPE7_AC_SDO (0x03 << 14) |
| 237 | |
| 238 | #define S3C2410_GPE8_SDDAT1 (0x02 << 16) |
| 239 | #define S3C2443_GPE8_SD1_DAT1 (0x02 << 16) |
| 240 | #define S3C2443_GPE8_AC_SYNC (0x03 << 16) |
| 241 | |
| 242 | #define S3C2410_GPE9_SDDAT2 (0x02 << 18) |
| 243 | #define S3C2443_GPE9_SD1_DAT2 (0x02 << 18) |
| 244 | #define S3C2443_GPE9_AC_nRESET (0x03 << 18) |
| 245 | |
| 246 | #define S3C2410_GPE10_SDDAT3 (0x02 << 20) |
| 247 | #define S3C2443_GPE10_SD1_DAT3 (0x02 << 20) |
| 248 | |
| 249 | #define S3C2410_GPE11_SPIMISO0 (0x02 << 22) |
| 250 | |
| 251 | #define S3C2410_GPE12_SPIMOSI0 (0x02 << 24) |
| 252 | |
| 253 | #define S3C2410_GPE13_SPICLK0 (0x02 << 26) |
| 254 | |
| 255 | #define S3C2410_GPE14_IICSCL (0x02 << 28) |
| 256 | #define S3C2410_GPE14_MASK (0x03 << 28) |
| 257 | |
| 258 | #define S3C2410_GPE15_IICSDA (0x02 << 30) |
| 259 | #define S3C2410_GPE15_MASK (0x03 << 30) |
| 260 | |
| 261 | #define S3C2440_GPE0_ACSYNC (0x03 << 0) |
| 262 | #define S3C2440_GPE1_ACBITCLK (0x03 << 2) |
| 263 | #define S3C2440_GPE2_ACRESET (0x03 << 4) |
| 264 | #define S3C2440_GPE3_ACIN (0x03 << 6) |
| 265 | #define S3C2440_GPE4_ACOUT (0x03 << 8) |
| 266 | |
| 267 | #define S3C2410_GPE_PUPDIS(x) (1<<(x)) |
| 268 | |
| 269 | /* S3C2410: |
| 270 | * Port F consists of 8 GPIO/Special function |
| 271 | * |
| 272 | * GPIO / interrupt inputs |
| 273 | * |
| 274 | * GPFCON has 2 bits for each of the input pins on port F |
| 275 | * 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 undefined |
| 276 | * |
| 277 | * pull up works like all other ports. |
| 278 | * |
| 279 | * GPIO/serial/misc pins |
| 280 | */ |
| 281 | |
| 282 | #define S3C2410_GPFCON S3C2410_GPIOREG(0x50) |
| 283 | #define S3C2410_GPFDAT S3C2410_GPIOREG(0x54) |
| 284 | #define S3C2410_GPFUP S3C2410_GPIOREG(0x58) |
| 285 | |
| 286 | #define S3C2410_GPF0_EINT0 (0x02 << 0) |
| 287 | #define S3C2410_GPF1_EINT1 (0x02 << 2) |
| 288 | #define S3C2410_GPF2_EINT2 (0x02 << 4) |
| 289 | #define S3C2410_GPF3_EINT3 (0x02 << 6) |
| 290 | #define S3C2410_GPF4_EINT4 (0x02 << 8) |
| 291 | #define S3C2410_GPF5_EINT5 (0x02 << 10) |
| 292 | #define S3C2410_GPF6_EINT6 (0x02 << 12) |
| 293 | #define S3C2410_GPF7_EINT7 (0x02 << 14) |
| 294 | #define S3C2410_GPF_PUPDIS(x) (1<<(x)) |
| 295 | |
| 296 | /* S3C2410: |
| 297 | * Port G consists of 8 GPIO/IRQ/Special function |
| 298 | * |
| 299 | * GPGCON has 2 bits for each of the input pins on port G |
| 300 | * 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func |
| 301 | * |
| 302 | * pull up works like all other ports. |
| 303 | */ |
| 304 | |
| 305 | #define S3C2410_GPGCON S3C2410_GPIOREG(0x60) |
| 306 | #define S3C2410_GPGDAT S3C2410_GPIOREG(0x64) |
| 307 | #define S3C2410_GPGUP S3C2410_GPIOREG(0x68) |
| 308 | |
| 309 | #define S3C2410_GPG0_EINT8 (0x02 << 0) |
| 310 | |
| 311 | #define S3C2410_GPG1_EINT9 (0x02 << 2) |
| 312 | |
| 313 | #define S3C2410_GPG2_EINT10 (0x02 << 4) |
| 314 | #define S3C2410_GPG2_nSS0 (0x03 << 4) |
| 315 | |
| 316 | #define S3C2410_GPG3_EINT11 (0x02 << 6) |
| 317 | #define S3C2410_GPG3_nSS1 (0x03 << 6) |
| 318 | |
| 319 | #define S3C2410_GPG4_EINT12 (0x02 << 8) |
| 320 | #define S3C2410_GPG4_LCDPWREN (0x03 << 8) |
| 321 | #define S3C2443_GPG4_LCDPWRDN (0x03 << 8) |
| 322 | |
| 323 | #define S3C2410_GPG5_EINT13 (0x02 << 10) |
| 324 | #define S3C2410_GPG5_SPIMISO1 (0x03 << 10) /* not s3c2443 */ |
| 325 | |
| 326 | #define S3C2410_GPG6_EINT14 (0x02 << 12) |
| 327 | #define S3C2410_GPG6_SPIMOSI1 (0x03 << 12) |
| 328 | |
| 329 | #define S3C2410_GPG7_EINT15 (0x02 << 14) |
| 330 | #define S3C2410_GPG7_SPICLK1 (0x03 << 14) |
| 331 | |
| 332 | #define S3C2410_GPG8_EINT16 (0x02 << 16) |
| 333 | |
| 334 | #define S3C2410_GPG9_EINT17 (0x02 << 18) |
| 335 | |
| 336 | #define S3C2410_GPG10_EINT18 (0x02 << 20) |
| 337 | |
| 338 | #define S3C2410_GPG11_EINT19 (0x02 << 22) |
| 339 | #define S3C2410_GPG11_TCLK1 (0x03 << 22) |
| 340 | #define S3C2443_GPG11_CF_nIREQ (0x03 << 22) |
| 341 | |
| 342 | #define S3C2410_GPG12_EINT20 (0x02 << 24) |
| 343 | #define S3C2410_GPG12_XMON (0x03 << 24) |
| 344 | #define S3C2442_GPG12_nSPICS0 (0x03 << 24) |
| 345 | #define S3C2443_GPG12_nINPACK (0x03 << 24) |
| 346 | |
| 347 | #define S3C2410_GPG13_EINT21 (0x02 << 26) |
| 348 | #define S3C2410_GPG13_nXPON (0x03 << 26) |
| 349 | #define S3C2443_GPG13_CF_nREG (0x03 << 26) |
| 350 | |
| 351 | #define S3C2410_GPG14_EINT22 (0x02 << 28) |
| 352 | #define S3C2410_GPG14_YMON (0x03 << 28) |
| 353 | #define S3C2443_GPG14_CF_RESET (0x03 << 28) |
| 354 | |
| 355 | #define S3C2410_GPG15_EINT23 (0x02 << 30) |
| 356 | #define S3C2410_GPG15_nYPON (0x03 << 30) |
| 357 | #define S3C2443_GPG15_CF_PWR (0x03 << 30) |
| 358 | |
| 359 | #define S3C2410_GPG_PUPDIS(x) (1<<(x)) |
| 360 | |
| 361 | /* Port H consists of11 GPIO/serial/Misc pins |
| 362 | * |
| 363 | * GPHCON has 2 bits for each of the input pins on port H |
| 364 | * 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func |
| 365 | * |
| 366 | * pull up works like all other ports. |
| 367 | */ |
| 368 | |
| 369 | #define S3C2410_GPHCON S3C2410_GPIOREG(0x70) |
| 370 | #define S3C2410_GPHDAT S3C2410_GPIOREG(0x74) |
| 371 | #define S3C2410_GPHUP S3C2410_GPIOREG(0x78) |
| 372 | |
| 373 | #define S3C2410_GPH0_nCTS0 (0x02 << 0) |
| 374 | #define S3C2416_GPH0_TXD0 (0x02 << 0) |
| 375 | |
| 376 | #define S3C2410_GPH1_nRTS0 (0x02 << 2) |
| 377 | #define S3C2416_GPH1_RXD0 (0x02 << 2) |
| 378 | |
| 379 | #define S3C2410_GPH2_TXD0 (0x02 << 4) |
| 380 | #define S3C2416_GPH2_TXD1 (0x02 << 4) |
| 381 | |
| 382 | #define S3C2410_GPH3_RXD0 (0x02 << 6) |
| 383 | #define S3C2416_GPH3_RXD1 (0x02 << 6) |
| 384 | |
| 385 | #define S3C2410_GPH4_TXD1 (0x02 << 8) |
| 386 | #define S3C2416_GPH4_TXD2 (0x02 << 8) |
| 387 | |
| 388 | #define S3C2410_GPH5_RXD1 (0x02 << 10) |
| 389 | #define S3C2416_GPH5_RXD2 (0x02 << 10) |
| 390 | |
| 391 | #define S3C2410_GPH6_TXD2 (0x02 << 12) |
| 392 | #define S3C2416_GPH6_TXD3 (0x02 << 12) |
| 393 | #define S3C2410_GPH6_nRTS1 (0x03 << 12) |
| 394 | #define S3C2416_GPH6_nRTS2 (0x03 << 12) |
| 395 | |
| 396 | #define S3C2410_GPH7_RXD2 (0x02 << 14) |
| 397 | #define S3C2416_GPH7_RXD3 (0x02 << 14) |
| 398 | #define S3C2410_GPH7_nCTS1 (0x03 << 14) |
| 399 | #define S3C2416_GPH7_nCTS2 (0x03 << 14) |
| 400 | |
| 401 | #define S3C2410_GPH8_UCLK (0x02 << 16) |
| 402 | #define S3C2416_GPH8_nCTS0 (0x02 << 16) |
| 403 | |
| 404 | #define S3C2410_GPH9_CLKOUT0 (0x02 << 18) |
| 405 | #define S3C2442_GPH9_nSPICS0 (0x03 << 18) |
| 406 | #define S3C2416_GPH9_nRTS0 (0x02 << 18) |
| 407 | |
| 408 | #define S3C2410_GPH10_CLKOUT1 (0x02 << 20) |
| 409 | #define S3C2416_GPH10_nCTS1 (0x02 << 20) |
| 410 | |
| 411 | #define S3C2416_GPH11_nRTS1 (0x02 << 22) |
| 412 | |
| 413 | #define S3C2416_GPH12_EXTUARTCLK (0x02 << 24) |
| 414 | |
| 415 | #define S3C2416_GPH13_CLKOUT0 (0x02 << 26) |
| 416 | |
| 417 | #define S3C2416_GPH14_CLKOUT1 (0x02 << 28) |
| 418 | |
| 419 | /* The S3C2412 and S3C2413 move the GPJ register set to after |
| 420 | * GPH, which means all registers after 0x80 are now offset by 0x10 |
| 421 | * for the 2412/2413 from the 2410/2440/2442 |
| 422 | */ |
| 423 | |
| 424 | /* |
| 425 | * Port J consists of 13 GPIO/Camera pins. GPJCON has 2 bits |
| 426 | * for each of the pins on port J. |
| 427 | * 00 - input, 01 output, 10 - camera |
| 428 | * |
| 429 | * Pull up works like all other ports. |
| 430 | */ |
| 431 | |
| 432 | #define S3C2413_GPJCON S3C2410_GPIOREG(0x80) |
| 433 | #define S3C2413_GPJDAT S3C2410_GPIOREG(0x84) |
| 434 | #define S3C2413_GPJUP S3C2410_GPIOREG(0x88) |
| 435 | #define S3C2413_GPJSLPCON S3C2410_GPIOREG(0x8C) |
| 436 | |
| 437 | /* S3C2443 and above */ |
| 438 | #define S3C2440_GPJCON S3C2410_GPIOREG(0xD0) |
| 439 | #define S3C2440_GPJDAT S3C2410_GPIOREG(0xD4) |
| 440 | #define S3C2440_GPJUP S3C2410_GPIOREG(0xD8) |
| 441 | |
| 442 | #define S3C2443_GPKCON S3C2410_GPIOREG(0xE0) |
| 443 | #define S3C2443_GPKDAT S3C2410_GPIOREG(0xE4) |
| 444 | #define S3C2443_GPKUP S3C2410_GPIOREG(0xE8) |
| 445 | |
| 446 | #define S3C2443_GPLCON S3C2410_GPIOREG(0xF0) |
| 447 | #define S3C2443_GPLDAT S3C2410_GPIOREG(0xF4) |
| 448 | #define S3C2443_GPLUP S3C2410_GPIOREG(0xF8) |
| 449 | |
| 450 | #define S3C2443_GPMCON S3C2410_GPIOREG(0x100) |
| 451 | #define S3C2443_GPMDAT S3C2410_GPIOREG(0x104) |
| 452 | #define S3C2443_GPMUP S3C2410_GPIOREG(0x108) |
| 453 | |
| 454 | /* miscellaneous control */ |
| 455 | #define S3C2410_MISCCR S3C2410_GPIOREG(0x80) |
| 456 | |
| 457 | /* see clock.h for dclk definitions */ |
| 458 | |
| 459 | /* pullup control on databus */ |
| 460 | #define S3C2410_MISCCR_SPUCR_HEN (0<<0) |
| 461 | #define S3C2410_MISCCR_SPUCR_HDIS (1<<0) |
| 462 | #define S3C2410_MISCCR_SPUCR_LEN (0<<1) |
| 463 | #define S3C2410_MISCCR_SPUCR_LDIS (1<<1) |
| 464 | |
| 465 | #define S3C2410_MISCCR_USBDEV (0<<3) |
| 466 | #define S3C2410_MISCCR_USBHOST (1<<3) |
| 467 | |
| 468 | #define S3C2410_MISCCR_CLK0_MPLL (0<<4) |
| 469 | #define S3C2410_MISCCR_CLK0_UPLL (1<<4) |
| 470 | #define S3C2410_MISCCR_CLK0_FCLK (2<<4) |
| 471 | #define S3C2410_MISCCR_CLK0_HCLK (3<<4) |
| 472 | #define S3C2410_MISCCR_CLK0_PCLK (4<<4) |
| 473 | #define S3C2410_MISCCR_CLK0_DCLK0 (5<<4) |
| 474 | #define S3C2410_MISCCR_CLK0_MASK (7<<4) |
| 475 | |
| 476 | #define S3C2412_MISCCR_CLK0_RTC (2<<4) |
| 477 | |
| 478 | #define S3C2410_MISCCR_CLK1_MPLL (0<<8) |
| 479 | #define S3C2410_MISCCR_CLK1_UPLL (1<<8) |
| 480 | #define S3C2410_MISCCR_CLK1_FCLK (2<<8) |
| 481 | #define S3C2410_MISCCR_CLK1_HCLK (3<<8) |
| 482 | #define S3C2410_MISCCR_CLK1_PCLK (4<<8) |
| 483 | #define S3C2410_MISCCR_CLK1_DCLK1 (5<<8) |
| 484 | #define S3C2410_MISCCR_CLK1_MASK (7<<8) |
| 485 | |
| 486 | #define S3C2412_MISCCR_CLK1_CLKsrc (0<<8) |
| 487 | |
| 488 | #define S3C2410_MISCCR_USBSUSPND0 (1<<12) |
| 489 | #define S3C2416_MISCCR_SEL_SUSPND (1<<12) |
| 490 | #define S3C2410_MISCCR_USBSUSPND1 (1<<13) |
| 491 | |
| 492 | #define S3C2410_MISCCR_nRSTCON (1<<16) |
| 493 | |
| 494 | #define S3C2410_MISCCR_nEN_SCLK0 (1<<17) |
| 495 | #define S3C2410_MISCCR_nEN_SCLK1 (1<<18) |
| 496 | #define S3C2410_MISCCR_nEN_SCLKE (1<<19) /* not 2412 */ |
| 497 | #define S3C2410_MISCCR_SDSLEEP (7<<17) |
| 498 | |
| 499 | #define S3C2416_MISCCR_FLT_I2C (1<<24) |
| 500 | #define S3C2416_MISCCR_HSSPI_EN2 (1<<31) |
| 501 | |
| 502 | /* external interrupt control... */ |
| 503 | /* S3C2410_EXTINT0 -> irq sense control for EINT0..EINT7 |
| 504 | * S3C2410_EXTINT1 -> irq sense control for EINT8..EINT15 |
| 505 | * S3C2410_EXTINT2 -> irq sense control for EINT16..EINT23 |
| 506 | * |
| 507 | * note S3C2410_EXTINT2 has filtering options for EINT16..EINT23 |
| 508 | * |
| 509 | * Samsung datasheet p9-25 |
| 510 | */ |
| 511 | #define S3C2410_EXTINT0 S3C2410_GPIOREG(0x88) |
| 512 | #define S3C2410_EXTINT1 S3C2410_GPIOREG(0x8C) |
| 513 | #define S3C2410_EXTINT2 S3C2410_GPIOREG(0x90) |
| 514 | |
| 515 | #define S3C24XX_EXTINT0 S3C24XX_GPIOREG2(0x88) |
| 516 | #define S3C24XX_EXTINT1 S3C24XX_GPIOREG2(0x8C) |
| 517 | #define S3C24XX_EXTINT2 S3C24XX_GPIOREG2(0x90) |
| 518 | |
| 519 | /* interrupt filtering control for EINT16..EINT23 */ |
| 520 | #define S3C2410_EINFLT0 S3C2410_GPIOREG(0x94) |
| 521 | #define S3C2410_EINFLT1 S3C2410_GPIOREG(0x98) |
| 522 | #define S3C2410_EINFLT2 S3C2410_GPIOREG(0x9C) |
| 523 | #define S3C2410_EINFLT3 S3C2410_GPIOREG(0xA0) |
| 524 | |
| 525 | #define S3C24XX_EINFLT0 S3C24XX_GPIOREG2(0x94) |
| 526 | #define S3C24XX_EINFLT1 S3C24XX_GPIOREG2(0x98) |
| 527 | #define S3C24XX_EINFLT2 S3C24XX_GPIOREG2(0x9C) |
| 528 | #define S3C24XX_EINFLT3 S3C24XX_GPIOREG2(0xA0) |
| 529 | |
| 530 | /* values for interrupt filtering */ |
| 531 | #define S3C2410_EINTFLT_PCLK (0x00) |
| 532 | #define S3C2410_EINTFLT_EXTCLK (1<<7) |
| 533 | #define S3C2410_EINTFLT_WIDTHMSK(x) ((x) & 0x3f) |
| 534 | |
| 535 | /* removed EINTxxxx defs from here, not meant for this */ |
| 536 | |
| 537 | /* GSTATUS have miscellaneous information in them |
| 538 | * |
| 539 | * These move between s3c2410 and s3c2412 style systems. |
| 540 | */ |
| 541 | |
| 542 | #define S3C2410_GSTATUS0 S3C2410_GPIOREG(0x0AC) |
| 543 | #define S3C2410_GSTATUS1 S3C2410_GPIOREG(0x0B0) |
| 544 | #define S3C2410_GSTATUS2 S3C2410_GPIOREG(0x0B4) |
| 545 | #define S3C2410_GSTATUS3 S3C2410_GPIOREG(0x0B8) |
| 546 | #define S3C2410_GSTATUS4 S3C2410_GPIOREG(0x0BC) |
| 547 | |
| 548 | #define S3C2412_GSTATUS0 S3C2410_GPIOREG(0x0BC) |
| 549 | #define S3C2412_GSTATUS1 S3C2410_GPIOREG(0x0C0) |
| 550 | #define S3C2412_GSTATUS2 S3C2410_GPIOREG(0x0C4) |
| 551 | #define S3C2412_GSTATUS3 S3C2410_GPIOREG(0x0C8) |
| 552 | #define S3C2412_GSTATUS4 S3C2410_GPIOREG(0x0CC) |
| 553 | |
| 554 | #define S3C24XX_GSTATUS0 S3C24XX_GPIOREG2(0x0AC) |
| 555 | #define S3C24XX_GSTATUS1 S3C24XX_GPIOREG2(0x0B0) |
| 556 | #define S3C24XX_GSTATUS2 S3C24XX_GPIOREG2(0x0B4) |
| 557 | #define S3C24XX_GSTATUS3 S3C24XX_GPIOREG2(0x0B8) |
| 558 | #define S3C24XX_GSTATUS4 S3C24XX_GPIOREG2(0x0BC) |
| 559 | |
| 560 | #define S3C2410_GSTATUS0_nWAIT (1<<3) |
| 561 | #define S3C2410_GSTATUS0_NCON (1<<2) |
| 562 | #define S3C2410_GSTATUS0_RnB (1<<1) |
| 563 | #define S3C2410_GSTATUS0_nBATTFLT (1<<0) |
| 564 | |
| 565 | #define S3C2410_GSTATUS1_IDMASK (0xffff0000) |
| 566 | #define S3C2410_GSTATUS1_2410 (0x32410000) |
| 567 | #define S3C2410_GSTATUS1_2412 (0x32412001) |
| 568 | #define S3C2410_GSTATUS1_2416 (0x32416003) |
| 569 | #define S3C2410_GSTATUS1_2440 (0x32440000) |
| 570 | #define S3C2410_GSTATUS1_2442 (0x32440aaa) |
| 571 | /* some 2416 CPUs report this value also */ |
| 572 | #define S3C2410_GSTATUS1_2450 (0x32450003) |
| 573 | |
| 574 | #define S3C2410_GSTATUS2_WTRESET (1<<2) |
| 575 | #define S3C2410_GSTATUS2_OFFRESET (1<<1) |
| 576 | #define S3C2410_GSTATUS2_PONRESET (1<<0) |
| 577 | |
| 578 | /* 2412/2413 sleep configuration registers */ |
| 579 | |
| 580 | #define S3C2412_GPBSLPCON S3C2410_GPIOREG(0x1C) |
| 581 | #define S3C2412_GPCSLPCON S3C2410_GPIOREG(0x2C) |
| 582 | #define S3C2412_GPDSLPCON S3C2410_GPIOREG(0x3C) |
| 583 | #define S3C2412_GPFSLPCON S3C2410_GPIOREG(0x5C) |
| 584 | #define S3C2412_GPGSLPCON S3C2410_GPIOREG(0x6C) |
| 585 | #define S3C2412_GPHSLPCON S3C2410_GPIOREG(0x7C) |
| 586 | |
| 587 | /* definitions for each pin bit */ |
| 588 | #define S3C2412_GPIO_SLPCON_LOW ( 0x00 ) |
| 589 | #define S3C2412_GPIO_SLPCON_HIGH ( 0x01 ) |
| 590 | #define S3C2412_GPIO_SLPCON_IN ( 0x02 ) |
| 591 | #define S3C2412_GPIO_SLPCON_PULL ( 0x03 ) |
| 592 | |
| 593 | #define S3C2412_SLPCON_LOW(x) ( 0x00 << ((x) * 2)) |
| 594 | #define S3C2412_SLPCON_HIGH(x) ( 0x01 << ((x) * 2)) |
| 595 | #define S3C2412_SLPCON_IN(x) ( 0x02 << ((x) * 2)) |
| 596 | #define S3C2412_SLPCON_PULL(x) ( 0x03 << ((x) * 2)) |
| 597 | #define S3C2412_SLPCON_EINT(x) ( 0x02 << ((x) * 2)) /* only IRQ pins */ |
| 598 | #define S3C2412_SLPCON_MASK(x) ( 0x03 << ((x) * 2)) |
| 599 | |
| 600 | #define S3C2412_SLPCON_ALL_LOW (0x0) |
| 601 | #define S3C2412_SLPCON_ALL_HIGH (0x11111111 | 0x44444444) |
| 602 | #define S3C2412_SLPCON_ALL_IN (0x22222222 | 0x88888888) |
| 603 | #define S3C2412_SLPCON_ALL_PULL (0x33333333) |
| 604 | |
| 605 | #endif /* __ASM_ARCH_REGS_GPIO_H */ |
| 606 | |