| b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* |
| 3 | * Copyright 2009 Andy Green <andy@warmcat.com> |
| 4 | * |
| 5 | * S3C64XX SROM definitions |
| 6 | */ |
| 7 | |
| 8 | #ifndef __MACH_S3C64XX_REGS_SROM_H |
| 9 | #define __MACH_S3C64XX_REGS_SROM_H __FILE__ |
| 10 | |
| 11 | #define S3C64XX_SROMREG(x) (S3C_VA_MEM + (x)) |
| 12 | |
| 13 | #define S3C64XX_SROM_BW S3C64XX_SROMREG(0) |
| 14 | #define S3C64XX_SROM_BC0 S3C64XX_SROMREG(4) |
| 15 | #define S3C64XX_SROM_BC1 S3C64XX_SROMREG(8) |
| 16 | #define S3C64XX_SROM_BC2 S3C64XX_SROMREG(0xc) |
| 17 | #define S3C64XX_SROM_BC3 S3C64XX_SROMREG(0x10) |
| 18 | #define S3C64XX_SROM_BC4 S3C64XX_SROMREG(0x14) |
| 19 | #define S3C64XX_SROM_BC5 S3C64XX_SROMREG(0x18) |
| 20 | |
| 21 | /* |
| 22 | * one register BW holds 5 x 4-bit packed settings for NCS0 - NCS4 |
| 23 | */ |
| 24 | |
| 25 | #define S3C64XX_SROM_BW__DATAWIDTH__SHIFT 0 |
| 26 | #define S3C64XX_SROM_BW__WAITENABLE__SHIFT 2 |
| 27 | #define S3C64XX_SROM_BW__BYTEENABLE__SHIFT 3 |
| 28 | #define S3C64XX_SROM_BW__CS_MASK 0xf |
| 29 | |
| 30 | #define S3C64XX_SROM_BW__NCS0__SHIFT 0 |
| 31 | #define S3C64XX_SROM_BW__NCS1__SHIFT 4 |
| 32 | #define S3C64XX_SROM_BW__NCS2__SHIFT 8 |
| 33 | #define S3C64XX_SROM_BW__NCS3__SHIFT 0xc |
| 34 | #define S3C64XX_SROM_BW__NCS4__SHIFT 0x10 |
| 35 | |
| 36 | /* |
| 37 | * applies to same to BCS0 - BCS4 |
| 38 | */ |
| 39 | |
| 40 | #define S3C64XX_SROM_BCX__PMC__SHIFT 0 |
| 41 | #define S3C64XX_SROM_BCX__PMC__MASK 3 |
| 42 | #define S3C64XX_SROM_BCX__TACP__SHIFT 4 |
| 43 | #define S3C64XX_SROM_BCX__TACP__MASK 0xf |
| 44 | #define S3C64XX_SROM_BCX__TCAH__SHIFT 8 |
| 45 | #define S3C64XX_SROM_BCX__TCAH__MASK 0xf |
| 46 | #define S3C64XX_SROM_BCX__TCOH__SHIFT 12 |
| 47 | #define S3C64XX_SROM_BCX__TCOH__MASK 0xf |
| 48 | #define S3C64XX_SROM_BCX__TACC__SHIFT 16 |
| 49 | #define S3C64XX_SROM_BCX__TACC__MASK 0x1f |
| 50 | #define S3C64XX_SROM_BCX__TCOS__SHIFT 24 |
| 51 | #define S3C64XX_SROM_BCX__TCOS__MASK 0xf |
| 52 | #define S3C64XX_SROM_BCX__TACS__SHIFT 28 |
| 53 | #define S3C64XX_SROM_BCX__TACS__MASK 0xf |
| 54 | |
| 55 | #endif /* __MACH_S3C64XX_REGS_SROM_H */ |