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192.168.1.100 / T108 / c2023d5d03be91dbb983606f0ec5e9e4ea36c8c2 / . / marvell / linux / arch / arm64 / boot / dts / freescale / imx8mq-nitrogen.dts
blob: c832bf0fcc6070cd63925116537214639a3629fa [file] [log] [blame]
b.liue9582032025-04-17 19:18:16 +0800[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2018 Boundary Devices
4 */
5
6/dts-v1/;
7
8#include <dt-bindings/input/input.h>
9#include "imx8mq.dtsi"
10
11/ {
12 model = "Boundary Devices i.MX8MQ Nitrogen8M";
13 compatible = "boundary,imx8mq-nitrogen8m", "fsl,imx8mq";
14
15 chosen {
16 stdout-path = "serial0:115200n8";
17 };
18
19 memory@40000000 {
20 device_type = "memory";
21 reg = <0x00000000 0x40000000 0 0x80000000>;
22 };
23
24 gpio-keys {
25 compatible = "gpio-keys";
26 pinctrl-names = "default";
27 pinctrl-0 = <&pinctrl_gpio_keys>;
28
29 power {
30 label = "Power Button";
31 gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
32 linux,code = <KEY_POWER>;
33 wakeup-source;
34 };
35 };
36
37 reg_vref_0v9: regulator-vref-0v9 {
38 compatible = "regulator-fixed";
39 regulator-name = "vref-0v9";
40 regulator-min-microvolt = <900000>;
41 regulator-max-microvolt = <900000>;
42 };
43
44 reg_vref_1v8: regulator-vref-1v8 {
45 compatible = "regulator-fixed";
46 regulator-name = "vref-1v8";
47 regulator-min-microvolt = <1800000>;
48 regulator-max-microvolt = <1800000>;
49 };
50
51 reg_vref_2v5: regulator-vref-2v5 {
52 compatible = "regulator-fixed";
53 regulator-name = "vref-2v5";
54 regulator-min-microvolt = <2500000>;
55 regulator-max-microvolt = <2500000>;
56 };
57
58 reg_vref_3v3: regulator-vref-3v3 {
59 compatible = "regulator-fixed";
60 regulator-name = "vref-3v3";
61 regulator-min-microvolt = <3300000>;
62 regulator-max-microvolt = <3300000>;
63 };
64
65 reg_vref_5v: regulator-vref-5v {
66 compatible = "regulator-fixed";
67 regulator-name = "vref-5v";
68 regulator-min-microvolt = <5000000>;
69 regulator-max-microvolt = <5000000>;
70 };
71};
72
73
74&fec1 {
75 pinctrl-names = "default";
76 pinctrl-0 = <&pinctrl_fec1>;
77 phy-mode = "rgmii-id";
78 phy-handle = <&ethphy0>;
79 fsl,magic-packet;
80 status = "okay";
81
82 mdio {
83 #address-cells = <1>;
84 #size-cells = <0>;
85
86 ethphy0: ethernet-phy@4 {
87 compatible = "ethernet-phy-ieee802.3-c22";
88 reg = <4>;
89 interrupts-extended = <&gpio1 11 IRQ_TYPE_LEVEL_LOW>;
90 };
91 };
92};
93
94&i2c1 {
95 clock-frequency = <400000>;
96 pinctrl-names = "default";
97 pinctrl-0 = <&pinctrl_i2c1>;
98 status = "okay";
99
100 i2cmux@70 {
101 compatible = "nxp,pca9546";
102 pinctrl-names = "default";
103 pinctrl-0 = <&pinctrl_i2c1_pca9546>;
104 reg = <0x70>;
105 reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
106 #address-cells = <1>;
107 #size-cells = <0>;
108
109 i2c1a: i2c1@0 {
110 reg = <0>;
111 #address-cells = <1>;
112 #size-cells = <0>;
113
114 reg_arm_dram: regulator@60 {
115 compatible = "fcs,fan53555";
116 pinctrl-names = "default";
117 pinctrl-0 = <&pinctrl_reg_arm_dram>;
118 reg = <0x60>;
119 regulator-min-microvolt = <900000>;
120 regulator-max-microvolt = <1000000>;
121 regulator-always-on;
122 vsel-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
123 };
124 };
125
126 i2c1b: i2c1@1 {
127 reg = <1>;
128 #address-cells = <1>;
129 #size-cells = <0>;
130
131 reg_dram_1p1v: regulator@60 {
132 compatible = "fcs,fan53555";
133 pinctrl-names = "default";
134 pinctrl-0 = <&pinctrl_reg_dram_1p1v>;
135 reg = <0x60>;
136 regulator-min-microvolt = <1100000>;
137 regulator-max-microvolt = <1100000>;
138 regulator-always-on;
139 vsel-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>;
140 };
141 };
142
143 i2c1c: i2c1@2 {
144 reg = <2>;
145 #address-cells = <1>;
146 #size-cells = <0>;
147
148 reg_soc_gpu_vpu: regulator@60 {
149 compatible = "fcs,fan53555";
150 pinctrl-names = "default";
151 pinctrl-0 = <&pinctrl_reg_soc_gpu_vpu>;
152 reg = <0x60>;
153 regulator-min-microvolt = <900000>;
154 regulator-max-microvolt = <1000000>;
155 regulator-always-on;
156 vsel-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
157 };
158 };
159
160 i2c1d: i2c1@3 {
161 reg = <3>;
162 #address-cells = <1>;
163 #size-cells = <0>;
164
165 rtc@68 {
166 compatible = "microcrystal,rv4162";
167 pinctrl-names = "default";
168 pinctrl-0 = <&pinctrl_i2c1d_rv4162>;
169 reg = <0x68>;
170 interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_LOW>;
171 wakeup-source;
172 };
173 };
174 };
175};
176
177&uart1 { /* console */
178 pinctrl-names = "default";
179 pinctrl-0 = <&pinctrl_uart1>;
180 assigned-clocks = <&clk IMX8MQ_CLK_UART1>;
181 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
182 status = "okay";
183};
184
185&uart2 {
186 pinctrl-names = "default";
187 pinctrl-0 = <&pinctrl_uart2>;
188 assigned-clocks = <&clk IMX8MQ_CLK_UART2>;
189 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
190 status = "okay";
191};
192
193&usdhc1 {
194 bus-width = <8>;
195 pinctrl-names = "default";
196 pinctrl-0 = <&pinctrl_usdhc1>;
197 non-removable;
198 vmmc-supply = <&reg_vref_1v8>;
199 status = "okay";
200};
201
202&wdog1 {
203 pinctrl-names = "default";
204 pinctrl-0 = <&pinctrl_wdog>;
205 fsl,ext-reset-output;
206 status = "okay";
207};
208
209&iomuxc {
210 pinctrl-names = "default";
211 pinctrl-0 = <&pinctrl_hog>;
212
213 pinctrl_hog: hoggrp {
214 fsl,pins = <
215 /* J17 connector, odd */
216 MX8MQ_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x19 /* Pin 19 */
217 MX8MQ_IOMUXC_SAI1_RXC_GPIO4_IO1 0x19 /* Pin 21 */
218 MX8MQ_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x19 /* Pin 23 */
219 MX8MQ_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x19 /* Pin 25 */
220 MX8MQ_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x19 /* Pin 27 */
221 MX8MQ_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x19 /* Pin 29 */
222 MX8MQ_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x19 /* Pin 31 */
223 MX8MQ_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x19 /* Pin 33 */
224 MX8MQ_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x19 /* Pin 35 */
225 MX8MQ_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x19 /* Pin 39 */
226 MX8MQ_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x19 /* Pin 41 */
227 MX8MQ_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x19 /* Pin 43 */
228 MX8MQ_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x19 /* Pin 45 */
229 MX8MQ_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x19 /* Pin 47 */
230 MX8MQ_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x19 /* Pin 49 */
231 MX8MQ_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x19 /* Pin 51 */
232
233 /* J17 connector, even */
234 MX8MQ_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19 /* Pin 44 */
235 MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29 0x19 /* Pin 48 */
236 MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 /* Pin 50 */
237 MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19 /* Pin 54 */
238 MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 /* Pin 56 */
239
240 /* J18 connector, odd */
241 MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x19 /* Pin 41 */
242 MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x19 /* Pin 43 */
243 MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 /* Pin 45 */
244 MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x19 /* Pin 47 */
245 MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18 0x19 /* Pin 49 */
246 MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14 0x19 /* Pin 53 */
247
248 /* J18 connector, even */
249 MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0 0x19 /* Pin 32 */
250 MX8MQ_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x19 /* Pin 36 */
251 MX8MQ_IOMUXC_NAND_DATA00_GPIO3_IO6 0x19 /* Pin 38 */
252 MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7 0x19 /* Pin 40 */
253 MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8 0x19 /* Pin 42 */
254 MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0x19 /* Pin 44 */
255 MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x19 /* Pin 46 */
256
257 /* J13 Pin 2, WL_WAKE */
258 MX8MQ_IOMUXC_SAI5_RXD2_GPIO3_IO23 0xd6
259 /* J13 Pin 4, WL_IRQ, not needed for Silex */
260 MX8MQ_IOMUXC_SAI5_RXD0_GPIO3_IO21 0xd6
261 /* J13 pin 9, unused */
262 MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19
263 /* J13 Pin 41, BT_CLK_REQ */
264 MX8MQ_IOMUXC_SAI5_RXD1_GPIO3_IO22 0xd6
265 /* J13 Pin 42, BT_HOST_WAKE */
266 MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25 0xd6
267
268 /* Clock for both CSI1 and CSI2 */
269 MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x07
270 /* test points */
271 MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0xc1 /* TP87 */
272 >;
273 };
274
275 pinctrl_fec1: fec1grp {
276 fsl,pins = <
277 MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
278 MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
279 MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
280 MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
281 MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
282 MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
283 MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
284 MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
285 MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
286 MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
287 MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
288 MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
289 MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
290 MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
291 MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
292 MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x59
293 >;
294 };
295
296 pinctrl_gpio_keys: gpio-keysgrp {
297 fsl,pins = <
298 MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19
299 >;
300 };
301
302
303 pinctrl_i2c1: i2c1grp {
304 fsl,pins = <
305 MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
306 MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
307 >;
308 };
309
310 pinctrl_i2c1_pca9546: i2c1-pca9546grp {
311 fsl,pins = <
312 MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x49
313 >;
314 };
315
316 pinctrl_i2c1d_rv4162: i2c1d-rv4162grp {
317 fsl,pins = <
318 MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x49
319 >;
320 };
321
322 pinctrl_reg_arm_dram: reg-arm-dramgrp {
323 fsl,pins = <
324 MX8MQ_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x16
325 >;
326 };
327
328 pinctrl_reg_dram_1p1v: reg-dram-1p1vgrp {
329 fsl,pins = <
330 MX8MQ_IOMUXC_SD1_STROBE_GPIO2_IO11 0x16
331 >;
332 };
333
334 pinctrl_reg_soc_gpu_vpu: reg-soc-gpu-vpugrp {
335 fsl,pins = <
336 MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x16
337 >;
338 };
339
340 pinctrl_uart1: uart1grp {
341 fsl,pins = <
342 MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x45
343 MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x45
344 >;
345 };
346
347 pinctrl_uart2: uart2grp {
348 fsl,pins = <
349 MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x45
350 MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x45
351 >;
352 };
353
354 pinctrl_usdhc1: usdhc1grp {
355 fsl,pins = <
356 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
357 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
358 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
359 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
360 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
361 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
362 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
363 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
364 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
365 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
366 MX8MQ_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41
367 >;
368 };
369
370 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
371 fsl,pins = <
372 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
373 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
374 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
375 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
376 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
377 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
378 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
379 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
380 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
381 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
382 >;
383 };
384
385 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
386 fsl,pins = <
387 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
388 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
389 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
390 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
391 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
392 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
393 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf
394 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf
395 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf
396 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf
397 >;
398 };
399
400 pinctrl_wdog: wdoggrp {
401 fsl,pins = <
402 MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
403 >;
404 };
405};