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192.168.1.100 / T108 / c2023d5d03be91dbb983606f0ec5e9e4ea36c8c2 / . / marvell / linux / arch / mips / include / asm / octeon / cvmx-pcsx-defs.h
blob: 5f013269a89d640543b632b5bdc536a30fbf6466 [file] [log] [blame]
b.liue9582032025-04-17 19:18:16 +0800[diff] [blame]1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (C) 2003-2018 Cavium, Inc.
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_PCSX_DEFS_H__
29#define __CVMX_PCSX_DEFS_H__
30
31static inline uint64_t CVMX_PCSX_ANX_ADV_REG(unsigned long offset, unsigned long block_id)
32{
33 switch (cvmx_get_octeon_family()) {
34 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
35 return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
36 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
37 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
38 return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
39 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
40 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
41 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
42 return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
43 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
44 return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
45 }
46 return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
47}
48
49static inline uint64_t CVMX_PCSX_ANX_EXT_ST_REG(unsigned long offset, unsigned long block_id)
50{
51 switch (cvmx_get_octeon_family()) {
52 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
53 return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
54 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
55 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
56 return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
57 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
58 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
59 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
60 return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
61 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
62 return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
63 }
64 return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
65}
66
67static inline uint64_t CVMX_PCSX_ANX_LP_ABIL_REG(unsigned long offset, unsigned long block_id)
68{
69 switch (cvmx_get_octeon_family()) {
70 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
71 return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
72 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
73 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
74 return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
75 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
76 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
77 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
78 return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
79 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
80 return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
81 }
82 return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
83}
84
85static inline uint64_t CVMX_PCSX_ANX_RESULTS_REG(unsigned long offset, unsigned long block_id)
86{
87 switch (cvmx_get_octeon_family()) {
88 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
89 return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
90 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
91 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
92 return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
93 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
94 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
95 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
96 return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
97 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
98 return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
99 }
100 return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
101}
102
103static inline uint64_t CVMX_PCSX_INTX_EN_REG(unsigned long offset, unsigned long block_id)
104{
105 switch (cvmx_get_octeon_family()) {
106 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
107 return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
108 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
109 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
110 return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
111 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
112 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
113 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
114 return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
115 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
116 return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
117 }
118 return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
119}
120
121static inline uint64_t CVMX_PCSX_INTX_REG(unsigned long offset, unsigned long block_id)
122{
123 switch (cvmx_get_octeon_family()) {
124 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
125 return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
126 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
127 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
128 return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
129 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
130 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
131 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
132 return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
133 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
134 return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
135 }
136 return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
137}
138
139static inline uint64_t CVMX_PCSX_LINKX_TIMER_COUNT_REG(unsigned long offset, unsigned long block_id)
140{
141 switch (cvmx_get_octeon_family()) {
142 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
143 return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
144 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
145 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
146 return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
147 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
148 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
149 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
150 return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
151 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
152 return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
153 }
154 return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
155}
156
157static inline uint64_t CVMX_PCSX_LOG_ANLX_REG(unsigned long offset, unsigned long block_id)
158{
159 switch (cvmx_get_octeon_family()) {
160 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
161 return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
162 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
163 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
164 return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
165 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
166 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
167 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
168 return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
169 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
170 return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
171 }
172 return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
173}
174
175static inline uint64_t CVMX_PCSX_MISCX_CTL_REG(unsigned long offset, unsigned long block_id)
176{
177 switch (cvmx_get_octeon_family()) {
178 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
179 return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
180 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
181 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
182 return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
183 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
184 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
185 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
186 return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
187 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
188 return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
189 }
190 return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
191}
192
193static inline uint64_t CVMX_PCSX_MRX_CONTROL_REG(unsigned long offset, unsigned long block_id)
194{
195 switch (cvmx_get_octeon_family()) {
196 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
197 return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
198 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
199 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
200 return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
201 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
202 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
203 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
204 return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
205 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
206 return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
207 }
208 return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
209}
210
211static inline uint64_t CVMX_PCSX_MRX_STATUS_REG(unsigned long offset, unsigned long block_id)
212{
213 switch (cvmx_get_octeon_family()) {
214 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
215 return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
216 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
217 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
218 return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
219 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
220 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
221 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
222 return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
223 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
224 return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
225 }
226 return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
227}
228
229static inline uint64_t CVMX_PCSX_RXX_STATES_REG(unsigned long offset, unsigned long block_id)
230{
231 switch (cvmx_get_octeon_family()) {
232 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
233 return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
234 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
235 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
236 return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
237 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
238 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
239 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
240 return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
241 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
242 return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
243 }
244 return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
245}
246
247static inline uint64_t CVMX_PCSX_RXX_SYNC_REG(unsigned long offset, unsigned long block_id)
248{
249 switch (cvmx_get_octeon_family()) {
250 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
251 return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
252 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
253 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
254 return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
255 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
256 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
257 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
258 return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
259 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
260 return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
261 }
262 return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
263}
264
265static inline uint64_t CVMX_PCSX_SGMX_AN_ADV_REG(unsigned long offset, unsigned long block_id)
266{
267 switch (cvmx_get_octeon_family()) {
268 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
269 return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
270 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
271 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
272 return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
273 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
274 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
275 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
276 return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
277 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
278 return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
279 }
280 return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
281}
282
283static inline uint64_t CVMX_PCSX_SGMX_LP_ADV_REG(unsigned long offset, unsigned long block_id)
284{
285 switch (cvmx_get_octeon_family()) {
286 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
287 return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
288 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
289 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
290 return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
291 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
292 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
293 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
294 return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
295 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
296 return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
297 }
298 return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
299}
300
301static inline uint64_t CVMX_PCSX_TXX_STATES_REG(unsigned long offset, unsigned long block_id)
302{
303 switch (cvmx_get_octeon_family()) {
304 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
305 return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
306 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
307 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
308 return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
309 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
310 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
311 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
312 return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
313 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
314 return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
315 }
316 return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
317}
318
319static inline uint64_t CVMX_PCSX_TX_RXX_POLARITY_REG(unsigned long offset, unsigned long block_id)
320{
321 switch (cvmx_get_octeon_family()) {
322 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
323 return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
324 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
325 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
326 return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
327 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
328 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
329 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
330 return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
331 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
332 return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
333 }
334 return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
335}
336
337void __cvmx_interrupt_pcsx_intx_en_reg_enable(int index, int block);
338
339union cvmx_pcsx_anx_adv_reg {
340 uint64_t u64;
341 struct cvmx_pcsx_anx_adv_reg_s {
342#ifdef __BIG_ENDIAN_BITFIELD
343 uint64_t reserved_16_63:48;
344 uint64_t np:1;
345 uint64_t reserved_14_14:1;
346 uint64_t rem_flt:2;
347 uint64_t reserved_9_11:3;
348 uint64_t pause:2;
349 uint64_t hfd:1;
350 uint64_t fd:1;
351 uint64_t reserved_0_4:5;
352#else
353 uint64_t reserved_0_4:5;
354 uint64_t fd:1;
355 uint64_t hfd:1;
356 uint64_t pause:2;
357 uint64_t reserved_9_11:3;
358 uint64_t rem_flt:2;
359 uint64_t reserved_14_14:1;
360 uint64_t np:1;
361 uint64_t reserved_16_63:48;
362#endif
363 } s;
364};
365
366union cvmx_pcsx_anx_ext_st_reg {
367 uint64_t u64;
368 struct cvmx_pcsx_anx_ext_st_reg_s {
369#ifdef __BIG_ENDIAN_BITFIELD
370 uint64_t reserved_16_63:48;
371 uint64_t thou_xfd:1;
372 uint64_t thou_xhd:1;
373 uint64_t thou_tfd:1;
374 uint64_t thou_thd:1;
375 uint64_t reserved_0_11:12;
376#else
377 uint64_t reserved_0_11:12;
378 uint64_t thou_thd:1;
379 uint64_t thou_tfd:1;
380 uint64_t thou_xhd:1;
381 uint64_t thou_xfd:1;
382 uint64_t reserved_16_63:48;
383#endif
384 } s;
385};
386
387union cvmx_pcsx_anx_lp_abil_reg {
388 uint64_t u64;
389 struct cvmx_pcsx_anx_lp_abil_reg_s {
390#ifdef __BIG_ENDIAN_BITFIELD
391 uint64_t reserved_16_63:48;
392 uint64_t np:1;
393 uint64_t ack:1;
394 uint64_t rem_flt:2;
395 uint64_t reserved_9_11:3;
396 uint64_t pause:2;
397 uint64_t hfd:1;
398 uint64_t fd:1;
399 uint64_t reserved_0_4:5;
400#else
401 uint64_t reserved_0_4:5;
402 uint64_t fd:1;
403 uint64_t hfd:1;
404 uint64_t pause:2;
405 uint64_t reserved_9_11:3;
406 uint64_t rem_flt:2;
407 uint64_t ack:1;
408 uint64_t np:1;
409 uint64_t reserved_16_63:48;
410#endif
411 } s;
412};
413
414union cvmx_pcsx_anx_results_reg {
415 uint64_t u64;
416 struct cvmx_pcsx_anx_results_reg_s {
417#ifdef __BIG_ENDIAN_BITFIELD
418 uint64_t reserved_7_63:57;
419 uint64_t pause:2;
420 uint64_t spd:2;
421 uint64_t an_cpt:1;
422 uint64_t dup:1;
423 uint64_t link_ok:1;
424#else
425 uint64_t link_ok:1;
426 uint64_t dup:1;
427 uint64_t an_cpt:1;
428 uint64_t spd:2;
429 uint64_t pause:2;
430 uint64_t reserved_7_63:57;
431#endif
432 } s;
433};
434
435union cvmx_pcsx_intx_en_reg {
436 uint64_t u64;
437 struct cvmx_pcsx_intx_en_reg_s {
438#ifdef __BIG_ENDIAN_BITFIELD
439 uint64_t reserved_13_63:51;
440 uint64_t dbg_sync_en:1;
441 uint64_t dup:1;
442 uint64_t sync_bad_en:1;
443 uint64_t an_bad_en:1;
444 uint64_t rxlock_en:1;
445 uint64_t rxbad_en:1;
446 uint64_t rxerr_en:1;
447 uint64_t txbad_en:1;
448 uint64_t txfifo_en:1;
449 uint64_t txfifu_en:1;
450 uint64_t an_err_en:1;
451 uint64_t xmit_en:1;
452 uint64_t lnkspd_en:1;
453#else
454 uint64_t lnkspd_en:1;
455 uint64_t xmit_en:1;
456 uint64_t an_err_en:1;
457 uint64_t txfifu_en:1;
458 uint64_t txfifo_en:1;
459 uint64_t txbad_en:1;
460 uint64_t rxerr_en:1;
461 uint64_t rxbad_en:1;
462 uint64_t rxlock_en:1;
463 uint64_t an_bad_en:1;
464 uint64_t sync_bad_en:1;
465 uint64_t dup:1;
466 uint64_t dbg_sync_en:1;
467 uint64_t reserved_13_63:51;
468#endif
469 } s;
470 struct cvmx_pcsx_intx_en_reg_cn52xx {
471#ifdef __BIG_ENDIAN_BITFIELD
472 uint64_t reserved_12_63:52;
473 uint64_t dup:1;
474 uint64_t sync_bad_en:1;
475 uint64_t an_bad_en:1;
476 uint64_t rxlock_en:1;
477 uint64_t rxbad_en:1;
478 uint64_t rxerr_en:1;
479 uint64_t txbad_en:1;
480 uint64_t txfifo_en:1;
481 uint64_t txfifu_en:1;
482 uint64_t an_err_en:1;
483 uint64_t xmit_en:1;
484 uint64_t lnkspd_en:1;
485#else
486 uint64_t lnkspd_en:1;
487 uint64_t xmit_en:1;
488 uint64_t an_err_en:1;
489 uint64_t txfifu_en:1;
490 uint64_t txfifo_en:1;
491 uint64_t txbad_en:1;
492 uint64_t rxerr_en:1;
493 uint64_t rxbad_en:1;
494 uint64_t rxlock_en:1;
495 uint64_t an_bad_en:1;
496 uint64_t sync_bad_en:1;
497 uint64_t dup:1;
498 uint64_t reserved_12_63:52;
499#endif
500 } cn52xx;
501};
502
503union cvmx_pcsx_intx_reg {
504 uint64_t u64;
505 struct cvmx_pcsx_intx_reg_s {
506#ifdef __BIG_ENDIAN_BITFIELD
507 uint64_t reserved_13_63:51;
508 uint64_t dbg_sync:1;
509 uint64_t dup:1;
510 uint64_t sync_bad:1;
511 uint64_t an_bad:1;
512 uint64_t rxlock:1;
513 uint64_t rxbad:1;
514 uint64_t rxerr:1;
515 uint64_t txbad:1;
516 uint64_t txfifo:1;
517 uint64_t txfifu:1;
518 uint64_t an_err:1;
519 uint64_t xmit:1;
520 uint64_t lnkspd:1;
521#else
522 uint64_t lnkspd:1;
523 uint64_t xmit:1;
524 uint64_t an_err:1;
525 uint64_t txfifu:1;
526 uint64_t txfifo:1;
527 uint64_t txbad:1;
528 uint64_t rxerr:1;
529 uint64_t rxbad:1;
530 uint64_t rxlock:1;
531 uint64_t an_bad:1;
532 uint64_t sync_bad:1;
533 uint64_t dup:1;
534 uint64_t dbg_sync:1;
535 uint64_t reserved_13_63:51;
536#endif
537 } s;
538 struct cvmx_pcsx_intx_reg_cn52xx {
539#ifdef __BIG_ENDIAN_BITFIELD
540 uint64_t reserved_12_63:52;
541 uint64_t dup:1;
542 uint64_t sync_bad:1;
543 uint64_t an_bad:1;
544 uint64_t rxlock:1;
545 uint64_t rxbad:1;
546 uint64_t rxerr:1;
547 uint64_t txbad:1;
548 uint64_t txfifo:1;
549 uint64_t txfifu:1;
550 uint64_t an_err:1;
551 uint64_t xmit:1;
552 uint64_t lnkspd:1;
553#else
554 uint64_t lnkspd:1;
555 uint64_t xmit:1;
556 uint64_t an_err:1;
557 uint64_t txfifu:1;
558 uint64_t txfifo:1;
559 uint64_t txbad:1;
560 uint64_t rxerr:1;
561 uint64_t rxbad:1;
562 uint64_t rxlock:1;
563 uint64_t an_bad:1;
564 uint64_t sync_bad:1;
565 uint64_t dup:1;
566 uint64_t reserved_12_63:52;
567#endif
568 } cn52xx;
569};
570
571union cvmx_pcsx_linkx_timer_count_reg {
572 uint64_t u64;
573 struct cvmx_pcsx_linkx_timer_count_reg_s {
574#ifdef __BIG_ENDIAN_BITFIELD
575 uint64_t reserved_16_63:48;
576 uint64_t count:16;
577#else
578 uint64_t count:16;
579 uint64_t reserved_16_63:48;
580#endif
581 } s;
582};
583
584union cvmx_pcsx_log_anlx_reg {
585 uint64_t u64;
586 struct cvmx_pcsx_log_anlx_reg_s {
587#ifdef __BIG_ENDIAN_BITFIELD
588 uint64_t reserved_4_63:60;
589 uint64_t lafifovfl:1;
590 uint64_t la_en:1;
591 uint64_t pkt_sz:2;
592#else
593 uint64_t pkt_sz:2;
594 uint64_t la_en:1;
595 uint64_t lafifovfl:1;
596 uint64_t reserved_4_63:60;
597#endif
598 } s;
599};
600
601union cvmx_pcsx_miscx_ctl_reg {
602 uint64_t u64;
603 struct cvmx_pcsx_miscx_ctl_reg_s {
604#ifdef __BIG_ENDIAN_BITFIELD
605 uint64_t reserved_13_63:51;
606 uint64_t sgmii:1;
607 uint64_t gmxeno:1;
608 uint64_t loopbck2:1;
609 uint64_t mac_phy:1;
610 uint64_t mode:1;
611 uint64_t an_ovrd:1;
612 uint64_t samp_pt:7;
613#else
614 uint64_t samp_pt:7;
615 uint64_t an_ovrd:1;
616 uint64_t mode:1;
617 uint64_t mac_phy:1;
618 uint64_t loopbck2:1;
619 uint64_t gmxeno:1;
620 uint64_t sgmii:1;
621 uint64_t reserved_13_63:51;
622#endif
623 } s;
624};
625
626union cvmx_pcsx_mrx_control_reg {
627 uint64_t u64;
628 struct cvmx_pcsx_mrx_control_reg_s {
629#ifdef __BIG_ENDIAN_BITFIELD
630 uint64_t reserved_16_63:48;
631 uint64_t reset:1;
632 uint64_t loopbck1:1;
633 uint64_t spdlsb:1;
634 uint64_t an_en:1;
635 uint64_t pwr_dn:1;
636 uint64_t reserved_10_10:1;
637 uint64_t rst_an:1;
638 uint64_t dup:1;
639 uint64_t coltst:1;
640 uint64_t spdmsb:1;
641 uint64_t uni:1;
642 uint64_t reserved_0_4:5;
643#else
644 uint64_t reserved_0_4:5;
645 uint64_t uni:1;
646 uint64_t spdmsb:1;
647 uint64_t coltst:1;
648 uint64_t dup:1;
649 uint64_t rst_an:1;
650 uint64_t reserved_10_10:1;
651 uint64_t pwr_dn:1;
652 uint64_t an_en:1;
653 uint64_t spdlsb:1;
654 uint64_t loopbck1:1;
655 uint64_t reset:1;
656 uint64_t reserved_16_63:48;
657#endif
658 } s;
659};
660
661union cvmx_pcsx_mrx_status_reg {
662 uint64_t u64;
663 struct cvmx_pcsx_mrx_status_reg_s {
664#ifdef __BIG_ENDIAN_BITFIELD
665 uint64_t reserved_16_63:48;
666 uint64_t hun_t4:1;
667 uint64_t hun_xfd:1;
668 uint64_t hun_xhd:1;
669 uint64_t ten_fd:1;
670 uint64_t ten_hd:1;
671 uint64_t hun_t2fd:1;
672 uint64_t hun_t2hd:1;
673 uint64_t ext_st:1;
674 uint64_t reserved_7_7:1;
675 uint64_t prb_sup:1;
676 uint64_t an_cpt:1;
677 uint64_t rm_flt:1;
678 uint64_t an_abil:1;
679 uint64_t lnk_st:1;
680 uint64_t reserved_1_1:1;
681 uint64_t extnd:1;
682#else
683 uint64_t extnd:1;
684 uint64_t reserved_1_1:1;
685 uint64_t lnk_st:1;
686 uint64_t an_abil:1;
687 uint64_t rm_flt:1;
688 uint64_t an_cpt:1;
689 uint64_t prb_sup:1;
690 uint64_t reserved_7_7:1;
691 uint64_t ext_st:1;
692 uint64_t hun_t2hd:1;
693 uint64_t hun_t2fd:1;
694 uint64_t ten_hd:1;
695 uint64_t ten_fd:1;
696 uint64_t hun_xhd:1;
697 uint64_t hun_xfd:1;
698 uint64_t hun_t4:1;
699 uint64_t reserved_16_63:48;
700#endif
701 } s;
702};
703
704union cvmx_pcsx_rxx_states_reg {
705 uint64_t u64;
706 struct cvmx_pcsx_rxx_states_reg_s {
707#ifdef __BIG_ENDIAN_BITFIELD
708 uint64_t reserved_16_63:48;
709 uint64_t rx_bad:1;
710 uint64_t rx_st:5;
711 uint64_t sync_bad:1;
712 uint64_t sync:4;
713 uint64_t an_bad:1;
714 uint64_t an_st:4;
715#else
716 uint64_t an_st:4;
717 uint64_t an_bad:1;
718 uint64_t sync:4;
719 uint64_t sync_bad:1;
720 uint64_t rx_st:5;
721 uint64_t rx_bad:1;
722 uint64_t reserved_16_63:48;
723#endif
724 } s;
725};
726
727union cvmx_pcsx_rxx_sync_reg {
728 uint64_t u64;
729 struct cvmx_pcsx_rxx_sync_reg_s {
730#ifdef __BIG_ENDIAN_BITFIELD
731 uint64_t reserved_2_63:62;
732 uint64_t sync:1;
733 uint64_t bit_lock:1;
734#else
735 uint64_t bit_lock:1;
736 uint64_t sync:1;
737 uint64_t reserved_2_63:62;
738#endif
739 } s;
740};
741
742union cvmx_pcsx_sgmx_an_adv_reg {
743 uint64_t u64;
744 struct cvmx_pcsx_sgmx_an_adv_reg_s {
745#ifdef __BIG_ENDIAN_BITFIELD
746 uint64_t reserved_16_63:48;
747 uint64_t link:1;
748 uint64_t ack:1;
749 uint64_t reserved_13_13:1;
750 uint64_t dup:1;
751 uint64_t speed:2;
752 uint64_t reserved_1_9:9;
753 uint64_t one:1;
754#else
755 uint64_t one:1;
756 uint64_t reserved_1_9:9;
757 uint64_t speed:2;
758 uint64_t dup:1;
759 uint64_t reserved_13_13:1;
760 uint64_t ack:1;
761 uint64_t link:1;
762 uint64_t reserved_16_63:48;
763#endif
764 } s;
765};
766
767union cvmx_pcsx_sgmx_lp_adv_reg {
768 uint64_t u64;
769 struct cvmx_pcsx_sgmx_lp_adv_reg_s {
770#ifdef __BIG_ENDIAN_BITFIELD
771 uint64_t reserved_16_63:48;
772 uint64_t link:1;
773 uint64_t reserved_13_14:2;
774 uint64_t dup:1;
775 uint64_t speed:2;
776 uint64_t reserved_1_9:9;
777 uint64_t one:1;
778#else
779 uint64_t one:1;
780 uint64_t reserved_1_9:9;
781 uint64_t speed:2;
782 uint64_t dup:1;
783 uint64_t reserved_13_14:2;
784 uint64_t link:1;
785 uint64_t reserved_16_63:48;
786#endif
787 } s;
788};
789
790union cvmx_pcsx_txx_states_reg {
791 uint64_t u64;
792 struct cvmx_pcsx_txx_states_reg_s {
793#ifdef __BIG_ENDIAN_BITFIELD
794 uint64_t reserved_7_63:57;
795 uint64_t xmit:2;
796 uint64_t tx_bad:1;
797 uint64_t ord_st:4;
798#else
799 uint64_t ord_st:4;
800 uint64_t tx_bad:1;
801 uint64_t xmit:2;
802 uint64_t reserved_7_63:57;
803#endif
804 } s;
805};
806
807union cvmx_pcsx_tx_rxx_polarity_reg {
808 uint64_t u64;
809 struct cvmx_pcsx_tx_rxx_polarity_reg_s {
810#ifdef __BIG_ENDIAN_BITFIELD
811 uint64_t reserved_4_63:60;
812 uint64_t rxovrd:1;
813 uint64_t autorxpl:1;
814 uint64_t rxplrt:1;
815 uint64_t txplrt:1;
816#else
817 uint64_t txplrt:1;
818 uint64_t rxplrt:1;
819 uint64_t autorxpl:1;
820 uint64_t rxovrd:1;
821 uint64_t reserved_4_63:60;
822#endif
823 } s;
824};
825
826#endif