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192.168.1.100 / T108 / c2023d5d03be91dbb983606f0ec5e9e4ea36c8c2 / . / marvell / linux / arch / mips / include / asm / octeon / cvmx-spxx-defs.h
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b.liue9582032025-04-17 19:18:16 +0800[diff] [blame]1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (C) 2003-2018 Cavium, Inc.
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_SPXX_DEFS_H__
29#define __CVMX_SPXX_DEFS_H__
30
31#define CVMX_SPXX_BCKPRS_CNT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000340ull) + ((block_id) & 1) * 0x8000000ull)
32#define CVMX_SPXX_BIST_STAT(block_id) (CVMX_ADD_IO_SEG(0x00011800900007F8ull) + ((block_id) & 1) * 0x8000000ull)
33#define CVMX_SPXX_CLK_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000348ull) + ((block_id) & 1) * 0x8000000ull)
34#define CVMX_SPXX_CLK_STAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000350ull) + ((block_id) & 1) * 0x8000000ull)
35#define CVMX_SPXX_DBG_DESKEW_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000368ull) + ((block_id) & 1) * 0x8000000ull)
36#define CVMX_SPXX_DBG_DESKEW_STATE(block_id) (CVMX_ADD_IO_SEG(0x0001180090000370ull) + ((block_id) & 1) * 0x8000000ull)
37#define CVMX_SPXX_DRV_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000358ull) + ((block_id) & 1) * 0x8000000ull)
38#define CVMX_SPXX_ERR_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000320ull) + ((block_id) & 1) * 0x8000000ull)
39#define CVMX_SPXX_INT_DAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000318ull) + ((block_id) & 1) * 0x8000000ull)
40#define CVMX_SPXX_INT_MSK(block_id) (CVMX_ADD_IO_SEG(0x0001180090000308ull) + ((block_id) & 1) * 0x8000000ull)
41#define CVMX_SPXX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x0001180090000300ull) + ((block_id) & 1) * 0x8000000ull)
42#define CVMX_SPXX_INT_SYNC(block_id) (CVMX_ADD_IO_SEG(0x0001180090000310ull) + ((block_id) & 1) * 0x8000000ull)
43#define CVMX_SPXX_TPA_ACC(block_id) (CVMX_ADD_IO_SEG(0x0001180090000338ull) + ((block_id) & 1) * 0x8000000ull)
44#define CVMX_SPXX_TPA_MAX(block_id) (CVMX_ADD_IO_SEG(0x0001180090000330ull) + ((block_id) & 1) * 0x8000000ull)
45#define CVMX_SPXX_TPA_SEL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000328ull) + ((block_id) & 1) * 0x8000000ull)
46#define CVMX_SPXX_TRN4_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000360ull) + ((block_id) & 1) * 0x8000000ull)
47
48void __cvmx_interrupt_spxx_int_msk_enable(int index);
49
50union cvmx_spxx_bckprs_cnt {
51 uint64_t u64;
52 struct cvmx_spxx_bckprs_cnt_s {
53#ifdef __BIG_ENDIAN_BITFIELD
54 uint64_t reserved_32_63:32;
55 uint64_t cnt:32;
56#else
57 uint64_t cnt:32;
58 uint64_t reserved_32_63:32;
59#endif
60 } s;
61};
62
63union cvmx_spxx_bist_stat {
64 uint64_t u64;
65 struct cvmx_spxx_bist_stat_s {
66#ifdef __BIG_ENDIAN_BITFIELD
67 uint64_t reserved_3_63:61;
68 uint64_t stat2:1;
69 uint64_t stat1:1;
70 uint64_t stat0:1;
71#else
72 uint64_t stat0:1;
73 uint64_t stat1:1;
74 uint64_t stat2:1;
75 uint64_t reserved_3_63:61;
76#endif
77 } s;
78};
79
80union cvmx_spxx_clk_ctl {
81 uint64_t u64;
82 struct cvmx_spxx_clk_ctl_s {
83#ifdef __BIG_ENDIAN_BITFIELD
84 uint64_t reserved_17_63:47;
85 uint64_t seetrn:1;
86 uint64_t reserved_12_15:4;
87 uint64_t clkdly:5;
88 uint64_t runbist:1;
89 uint64_t statdrv:1;
90 uint64_t statrcv:1;
91 uint64_t sndtrn:1;
92 uint64_t drptrn:1;
93 uint64_t rcvtrn:1;
94 uint64_t srxdlck:1;
95#else
96 uint64_t srxdlck:1;
97 uint64_t rcvtrn:1;
98 uint64_t drptrn:1;
99 uint64_t sndtrn:1;
100 uint64_t statrcv:1;
101 uint64_t statdrv:1;
102 uint64_t runbist:1;
103 uint64_t clkdly:5;
104 uint64_t reserved_12_15:4;
105 uint64_t seetrn:1;
106 uint64_t reserved_17_63:47;
107#endif
108 } s;
109};
110
111union cvmx_spxx_clk_stat {
112 uint64_t u64;
113 struct cvmx_spxx_clk_stat_s {
114#ifdef __BIG_ENDIAN_BITFIELD
115 uint64_t reserved_11_63:53;
116 uint64_t stxcal:1;
117 uint64_t reserved_9_9:1;
118 uint64_t srxtrn:1;
119 uint64_t s4clk1:1;
120 uint64_t s4clk0:1;
121 uint64_t d4clk1:1;
122 uint64_t d4clk0:1;
123 uint64_t reserved_0_3:4;
124#else
125 uint64_t reserved_0_3:4;
126 uint64_t d4clk0:1;
127 uint64_t d4clk1:1;
128 uint64_t s4clk0:1;
129 uint64_t s4clk1:1;
130 uint64_t srxtrn:1;
131 uint64_t reserved_9_9:1;
132 uint64_t stxcal:1;
133 uint64_t reserved_11_63:53;
134#endif
135 } s;
136};
137
138union cvmx_spxx_dbg_deskew_ctl {
139 uint64_t u64;
140 struct cvmx_spxx_dbg_deskew_ctl_s {
141#ifdef __BIG_ENDIAN_BITFIELD
142 uint64_t reserved_30_63:34;
143 uint64_t fallnop:1;
144 uint64_t fall8:1;
145 uint64_t reserved_26_27:2;
146 uint64_t sstep_go:1;
147 uint64_t sstep:1;
148 uint64_t reserved_22_23:2;
149 uint64_t clrdly:1;
150 uint64_t dec:1;
151 uint64_t inc:1;
152 uint64_t mux:1;
153 uint64_t offset:5;
154 uint64_t bitsel:5;
155 uint64_t offdly:6;
156 uint64_t dllfrc:1;
157 uint64_t dlldis:1;
158#else
159 uint64_t dlldis:1;
160 uint64_t dllfrc:1;
161 uint64_t offdly:6;
162 uint64_t bitsel:5;
163 uint64_t offset:5;
164 uint64_t mux:1;
165 uint64_t inc:1;
166 uint64_t dec:1;
167 uint64_t clrdly:1;
168 uint64_t reserved_22_23:2;
169 uint64_t sstep:1;
170 uint64_t sstep_go:1;
171 uint64_t reserved_26_27:2;
172 uint64_t fall8:1;
173 uint64_t fallnop:1;
174 uint64_t reserved_30_63:34;
175#endif
176 } s;
177};
178
179union cvmx_spxx_dbg_deskew_state {
180 uint64_t u64;
181 struct cvmx_spxx_dbg_deskew_state_s {
182#ifdef __BIG_ENDIAN_BITFIELD
183 uint64_t reserved_9_63:55;
184 uint64_t testres:1;
185 uint64_t unxterm:1;
186 uint64_t muxsel:2;
187 uint64_t offset:5;
188#else
189 uint64_t offset:5;
190 uint64_t muxsel:2;
191 uint64_t unxterm:1;
192 uint64_t testres:1;
193 uint64_t reserved_9_63:55;
194#endif
195 } s;
196};
197
198union cvmx_spxx_drv_ctl {
199 uint64_t u64;
200 struct cvmx_spxx_drv_ctl_s {
201#ifdef __BIG_ENDIAN_BITFIELD
202 uint64_t reserved_0_63:64;
203#else
204 uint64_t reserved_0_63:64;
205#endif
206 } s;
207 struct cvmx_spxx_drv_ctl_cn38xx {
208#ifdef __BIG_ENDIAN_BITFIELD
209 uint64_t reserved_16_63:48;
210 uint64_t stx4ncmp:4;
211 uint64_t stx4pcmp:4;
212 uint64_t srx4cmp:8;
213#else
214 uint64_t srx4cmp:8;
215 uint64_t stx4pcmp:4;
216 uint64_t stx4ncmp:4;
217 uint64_t reserved_16_63:48;
218#endif
219 } cn38xx;
220 struct cvmx_spxx_drv_ctl_cn58xx {
221#ifdef __BIG_ENDIAN_BITFIELD
222 uint64_t reserved_24_63:40;
223 uint64_t stx4ncmp:4;
224 uint64_t stx4pcmp:4;
225 uint64_t reserved_10_15:6;
226 uint64_t srx4cmp:10;
227#else
228 uint64_t srx4cmp:10;
229 uint64_t reserved_10_15:6;
230 uint64_t stx4pcmp:4;
231 uint64_t stx4ncmp:4;
232 uint64_t reserved_24_63:40;
233#endif
234 } cn58xx;
235};
236
237union cvmx_spxx_err_ctl {
238 uint64_t u64;
239 struct cvmx_spxx_err_ctl_s {
240#ifdef __BIG_ENDIAN_BITFIELD
241 uint64_t reserved_9_63:55;
242 uint64_t prtnxa:1;
243 uint64_t dipcls:1;
244 uint64_t dippay:1;
245 uint64_t reserved_4_5:2;
246 uint64_t errcnt:4;
247#else
248 uint64_t errcnt:4;
249 uint64_t reserved_4_5:2;
250 uint64_t dippay:1;
251 uint64_t dipcls:1;
252 uint64_t prtnxa:1;
253 uint64_t reserved_9_63:55;
254#endif
255 } s;
256};
257
258union cvmx_spxx_int_dat {
259 uint64_t u64;
260 struct cvmx_spxx_int_dat_s {
261#ifdef __BIG_ENDIAN_BITFIELD
262 uint64_t reserved_32_63:32;
263 uint64_t mul:1;
264 uint64_t reserved_14_30:17;
265 uint64_t calbnk:2;
266 uint64_t rsvop:4;
267 uint64_t prt:8;
268#else
269 uint64_t prt:8;
270 uint64_t rsvop:4;
271 uint64_t calbnk:2;
272 uint64_t reserved_14_30:17;
273 uint64_t mul:1;
274 uint64_t reserved_32_63:32;
275#endif
276 } s;
277};
278
279union cvmx_spxx_int_msk {
280 uint64_t u64;
281 struct cvmx_spxx_int_msk_s {
282#ifdef __BIG_ENDIAN_BITFIELD
283 uint64_t reserved_12_63:52;
284 uint64_t calerr:1;
285 uint64_t syncerr:1;
286 uint64_t diperr:1;
287 uint64_t tpaovr:1;
288 uint64_t rsverr:1;
289 uint64_t drwnng:1;
290 uint64_t clserr:1;
291 uint64_t spiovr:1;
292 uint64_t reserved_2_3:2;
293 uint64_t abnorm:1;
294 uint64_t prtnxa:1;
295#else
296 uint64_t prtnxa:1;
297 uint64_t abnorm:1;
298 uint64_t reserved_2_3:2;
299 uint64_t spiovr:1;
300 uint64_t clserr:1;
301 uint64_t drwnng:1;
302 uint64_t rsverr:1;
303 uint64_t tpaovr:1;
304 uint64_t diperr:1;
305 uint64_t syncerr:1;
306 uint64_t calerr:1;
307 uint64_t reserved_12_63:52;
308#endif
309 } s;
310};
311
312union cvmx_spxx_int_reg {
313 uint64_t u64;
314 struct cvmx_spxx_int_reg_s {
315#ifdef __BIG_ENDIAN_BITFIELD
316 uint64_t reserved_32_63:32;
317 uint64_t spf:1;
318 uint64_t reserved_12_30:19;
319 uint64_t calerr:1;
320 uint64_t syncerr:1;
321 uint64_t diperr:1;
322 uint64_t tpaovr:1;
323 uint64_t rsverr:1;
324 uint64_t drwnng:1;
325 uint64_t clserr:1;
326 uint64_t spiovr:1;
327 uint64_t reserved_2_3:2;
328 uint64_t abnorm:1;
329 uint64_t prtnxa:1;
330#else
331 uint64_t prtnxa:1;
332 uint64_t abnorm:1;
333 uint64_t reserved_2_3:2;
334 uint64_t spiovr:1;
335 uint64_t clserr:1;
336 uint64_t drwnng:1;
337 uint64_t rsverr:1;
338 uint64_t tpaovr:1;
339 uint64_t diperr:1;
340 uint64_t syncerr:1;
341 uint64_t calerr:1;
342 uint64_t reserved_12_30:19;
343 uint64_t spf:1;
344 uint64_t reserved_32_63:32;
345#endif
346 } s;
347};
348
349union cvmx_spxx_int_sync {
350 uint64_t u64;
351 struct cvmx_spxx_int_sync_s {
352#ifdef __BIG_ENDIAN_BITFIELD
353 uint64_t reserved_12_63:52;
354 uint64_t calerr:1;
355 uint64_t syncerr:1;
356 uint64_t diperr:1;
357 uint64_t tpaovr:1;
358 uint64_t rsverr:1;
359 uint64_t drwnng:1;
360 uint64_t clserr:1;
361 uint64_t spiovr:1;
362 uint64_t reserved_2_3:2;
363 uint64_t abnorm:1;
364 uint64_t prtnxa:1;
365#else
366 uint64_t prtnxa:1;
367 uint64_t abnorm:1;
368 uint64_t reserved_2_3:2;
369 uint64_t spiovr:1;
370 uint64_t clserr:1;
371 uint64_t drwnng:1;
372 uint64_t rsverr:1;
373 uint64_t tpaovr:1;
374 uint64_t diperr:1;
375 uint64_t syncerr:1;
376 uint64_t calerr:1;
377 uint64_t reserved_12_63:52;
378#endif
379 } s;
380};
381
382union cvmx_spxx_tpa_acc {
383 uint64_t u64;
384 struct cvmx_spxx_tpa_acc_s {
385#ifdef __BIG_ENDIAN_BITFIELD
386 uint64_t reserved_32_63:32;
387 uint64_t cnt:32;
388#else
389 uint64_t cnt:32;
390 uint64_t reserved_32_63:32;
391#endif
392 } s;
393};
394
395union cvmx_spxx_tpa_max {
396 uint64_t u64;
397 struct cvmx_spxx_tpa_max_s {
398#ifdef __BIG_ENDIAN_BITFIELD
399 uint64_t reserved_32_63:32;
400 uint64_t max:32;
401#else
402 uint64_t max:32;
403 uint64_t reserved_32_63:32;
404#endif
405 } s;
406};
407
408union cvmx_spxx_tpa_sel {
409 uint64_t u64;
410 struct cvmx_spxx_tpa_sel_s {
411#ifdef __BIG_ENDIAN_BITFIELD
412 uint64_t reserved_4_63:60;
413 uint64_t prtsel:4;
414#else
415 uint64_t prtsel:4;
416 uint64_t reserved_4_63:60;
417#endif
418 } s;
419};
420
421union cvmx_spxx_trn4_ctl {
422 uint64_t u64;
423 struct cvmx_spxx_trn4_ctl_s {
424#ifdef __BIG_ENDIAN_BITFIELD
425 uint64_t reserved_13_63:51;
426 uint64_t trntest:1;
427 uint64_t jitter:3;
428 uint64_t clr_boot:1;
429 uint64_t set_boot:1;
430 uint64_t maxdist:5;
431 uint64_t macro_en:1;
432 uint64_t mux_en:1;
433#else
434 uint64_t mux_en:1;
435 uint64_t macro_en:1;
436 uint64_t maxdist:5;
437 uint64_t set_boot:1;
438 uint64_t clr_boot:1;
439 uint64_t jitter:3;
440 uint64_t trntest:1;
441 uint64_t reserved_13_63:51;
442#endif
443 } s;
444};
445
446#endif