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192.168.1.100 / T108 / c2023d5d03be91dbb983606f0ec5e9e4ea36c8c2 / . / marvell / linux / arch / powerpc / platforms / powermac / sleep.S
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b.liue9582032025-04-17 19:18:16 +0800[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * This file contains sleep low-level functions for PowerBook G3.
4 * Copyright (C) 1999 Benjamin Herrenschmidt (benh@kernel.crashing.org)
5 * and Paul Mackerras (paulus@samba.org).
6 */
7
8#include <asm/processor.h>
9#include <asm/page.h>
10#include <asm/ppc_asm.h>
11#include <asm/cputable.h>
12#include <asm/cache.h>
13#include <asm/thread_info.h>
14#include <asm/asm-offsets.h>
15#include <asm/mmu.h>
16#include <asm/feature-fixups.h>
17
18#define MAGIC 0x4c617273 /* 'Lars' */
19
20/*
21 * Structure for storing CPU registers on the stack.
22 */
23#define SL_SP 0
24#define SL_PC 4
25#define SL_MSR 8
26#define SL_SDR1 0xc
27#define SL_SPRG0 0x10 /* 4 sprg's */
28#define SL_DBAT0 0x20
29#define SL_IBAT0 0x28
30#define SL_DBAT1 0x30
31#define SL_IBAT1 0x38
32#define SL_DBAT2 0x40
33#define SL_IBAT2 0x48
34#define SL_DBAT3 0x50
35#define SL_IBAT3 0x58
36#define SL_DBAT4 0x60
37#define SL_IBAT4 0x68
38#define SL_DBAT5 0x70
39#define SL_IBAT5 0x78
40#define SL_DBAT6 0x80
41#define SL_IBAT6 0x88
42#define SL_DBAT7 0x90
43#define SL_IBAT7 0x98
44#define SL_TB 0xa0
45#define SL_R2 0xa8
46#define SL_CR 0xac
47#define SL_R12 0xb0 /* r12 to r31 */
48#define SL_SIZE (SL_R12 + 80)
49
50 .section .text
51 .align 5
52
53#if defined(CONFIG_PM) || defined(CONFIG_CPU_FREQ_PMAC) || \
54 (defined(CONFIG_HOTPLUG_CPU) && defined(CONFIG_PPC32))
55
56/* This gets called by via-pmu.c late during the sleep process.
57 * The PMU was already send the sleep command and will shut us down
58 * soon. We need to save all that is needed and setup the wakeup
59 * vector that will be called by the ROM on wakeup
60 */
61_GLOBAL(low_sleep_handler)
62#ifndef CONFIG_PPC_BOOK3S_32
63 blr
64#else
65 mflr r0
66 stw r0,4(r1)
67 stwu r1,-SL_SIZE(r1)
68 mfcr r0
69 stw r0,SL_CR(r1)
70 stw r2,SL_R2(r1)
71 stmw r12,SL_R12(r1)
72
73 /* Save MSR & SDR1 */
74 mfmsr r4
75 stw r4,SL_MSR(r1)
76 mfsdr1 r4
77 stw r4,SL_SDR1(r1)
78
79 /* Get a stable timebase and save it */
801: mftbu r4
81 stw r4,SL_TB(r1)
82 mftb r5
83 stw r5,SL_TB+4(r1)
84 mftbu r3
85 cmpw r3,r4
86 bne 1b
87
88 /* Save SPRGs */
89 mfsprg r4,0
90 stw r4,SL_SPRG0(r1)
91 mfsprg r4,1
92 stw r4,SL_SPRG0+4(r1)
93 mfsprg r4,2
94 stw r4,SL_SPRG0+8(r1)
95 mfsprg r4,3
96 stw r4,SL_SPRG0+12(r1)
97
98 /* Save BATs */
99 mfdbatu r4,0
100 stw r4,SL_DBAT0(r1)
101 mfdbatl r4,0
102 stw r4,SL_DBAT0+4(r1)
103 mfdbatu r4,1
104 stw r4,SL_DBAT1(r1)
105 mfdbatl r4,1
106 stw r4,SL_DBAT1+4(r1)
107 mfdbatu r4,2
108 stw r4,SL_DBAT2(r1)
109 mfdbatl r4,2
110 stw r4,SL_DBAT2+4(r1)
111 mfdbatu r4,3
112 stw r4,SL_DBAT3(r1)
113 mfdbatl r4,3
114 stw r4,SL_DBAT3+4(r1)
115 mfibatu r4,0
116 stw r4,SL_IBAT0(r1)
117 mfibatl r4,0
118 stw r4,SL_IBAT0+4(r1)
119 mfibatu r4,1
120 stw r4,SL_IBAT1(r1)
121 mfibatl r4,1
122 stw r4,SL_IBAT1+4(r1)
123 mfibatu r4,2
124 stw r4,SL_IBAT2(r1)
125 mfibatl r4,2
126 stw r4,SL_IBAT2+4(r1)
127 mfibatu r4,3
128 stw r4,SL_IBAT3(r1)
129 mfibatl r4,3
130 stw r4,SL_IBAT3+4(r1)
131
132BEGIN_MMU_FTR_SECTION
133 mfspr r4,SPRN_DBAT4U
134 stw r4,SL_DBAT4(r1)
135 mfspr r4,SPRN_DBAT4L
136 stw r4,SL_DBAT4+4(r1)
137 mfspr r4,SPRN_DBAT5U
138 stw r4,SL_DBAT5(r1)
139 mfspr r4,SPRN_DBAT5L
140 stw r4,SL_DBAT5+4(r1)
141 mfspr r4,SPRN_DBAT6U
142 stw r4,SL_DBAT6(r1)
143 mfspr r4,SPRN_DBAT6L
144 stw r4,SL_DBAT6+4(r1)
145 mfspr r4,SPRN_DBAT7U
146 stw r4,SL_DBAT7(r1)
147 mfspr r4,SPRN_DBAT7L
148 stw r4,SL_DBAT7+4(r1)
149 mfspr r4,SPRN_IBAT4U
150 stw r4,SL_IBAT4(r1)
151 mfspr r4,SPRN_IBAT4L
152 stw r4,SL_IBAT4+4(r1)
153 mfspr r4,SPRN_IBAT5U
154 stw r4,SL_IBAT5(r1)
155 mfspr r4,SPRN_IBAT5L
156 stw r4,SL_IBAT5+4(r1)
157 mfspr r4,SPRN_IBAT6U
158 stw r4,SL_IBAT6(r1)
159 mfspr r4,SPRN_IBAT6L
160 stw r4,SL_IBAT6+4(r1)
161 mfspr r4,SPRN_IBAT7U
162 stw r4,SL_IBAT7(r1)
163 mfspr r4,SPRN_IBAT7L
164 stw r4,SL_IBAT7+4(r1)
165END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
166
167 /* Backup various CPU config stuffs */
168 bl __save_cpu_setup
169
170 /* The ROM can wake us up via 2 different vectors:
171 * - On wallstreet & lombard, we must write a magic
172 * value 'Lars' at address 4 and a pointer to a
173 * memory location containing the PC to resume from
174 * at address 0.
175 * - On Core99, we must store the wakeup vector at
176 * address 0x80 and eventually it's parameters
177 * at address 0x84. I've have some trouble with those
178 * parameters however and I no longer use them.
179 */
180 lis r5,grackle_wake_up@ha
181 addi r5,r5,grackle_wake_up@l
182 tophys(r5,r5)
183 stw r5,SL_PC(r1)
184 lis r4,KERNELBASE@h
185 tophys(r5,r1)
186 addi r5,r5,SL_PC
187 lis r6,MAGIC@ha
188 addi r6,r6,MAGIC@l
189 stw r5,0(r4)
190 stw r6,4(r4)
191 /* Setup stuffs at 0x80-0x84 for Core99 */
192 lis r3,core99_wake_up@ha
193 addi r3,r3,core99_wake_up@l
194 tophys(r3,r3)
195 stw r3,0x80(r4)
196 stw r5,0x84(r4)
197 /* Store a pointer to our backup storage into
198 * a kernel global
199 */
200 lis r3,sleep_storage@ha
201 addi r3,r3,sleep_storage@l
202 stw r5,0(r3)
203
204 .globl low_cpu_die
205low_cpu_die:
206 /* Flush & disable all caches */
207 bl flush_disable_caches
208
209 /* Turn off data relocation. */
210 mfmsr r3 /* Save MSR in r7 */
211 rlwinm r3,r3,0,28,26 /* Turn off DR bit */
212 sync
213 mtmsr r3
214 isync
215
216BEGIN_FTR_SECTION
217 /* Flush any pending L2 data prefetches to work around HW bug */
218 sync
219 lis r3,0xfff0
220 lwz r0,0(r3) /* perform cache-inhibited load to ROM */
221 sync /* (caches are disabled at this point) */
222END_FTR_SECTION_IFSET(CPU_FTR_SPEC7450)
223
224/*
225 * Set the HID0 and MSR for sleep.
226 */
227 mfspr r2,SPRN_HID0
228 rlwinm r2,r2,0,10,7 /* clear doze, nap */
229 oris r2,r2,HID0_SLEEP@h
230 sync
231 isync
232 mtspr SPRN_HID0,r2
233 sync
234
235/* This loop puts us back to sleep in case we have a spurrious
236 * wakeup so that the host bridge properly stays asleep. The
237 * CPU will be turned off, either after a known time (about 1
238 * second) on wallstreet & lombard, or as soon as the CPU enters
239 * SLEEP mode on core99
240 */
241 mfmsr r2
242 oris r2,r2,MSR_POW@h
2431: sync
244 mtmsr r2
245 isync
246 b 1b
247
248/*
249 * Here is the resume code.
250 */
251
252
253/*
254 * Core99 machines resume here
255 * r4 has the physical address of SL_PC(sp) (unused)
256 */
257_GLOBAL(core99_wake_up)
258 /* Make sure HID0 no longer contains any sleep bit and that data cache
259 * is disabled
260 */
261 mfspr r3,SPRN_HID0
262 rlwinm r3,r3,0,11,7 /* clear SLEEP, NAP, DOZE bits */
263 rlwinm 3,r3,0,18,15 /* clear DCE, ICE */
264 mtspr SPRN_HID0,r3
265 sync
266 isync
267
268 /* sanitize MSR */
269 mfmsr r3
270 ori r3,r3,MSR_EE|MSR_IP
271 xori r3,r3,MSR_EE|MSR_IP
272 sync
273 isync
274 mtmsr r3
275 sync
276 isync
277
278 /* Recover sleep storage */
279 lis r3,sleep_storage@ha
280 addi r3,r3,sleep_storage@l
281 tophys(r3,r3)
282 lwz r1,0(r3)
283
284 /* Pass thru to older resume code ... */
285/*
286 * Here is the resume code for older machines.
287 * r1 has the physical address of SL_PC(sp).
288 */
289
290grackle_wake_up:
291
292 /* Restore the kernel's segment registers before
293 * we do any r1 memory access as we are not sure they
294 * are in a sane state above the first 256Mb region
295 */
296 bl load_segment_registers
297 sync
298 isync
299
300 subi r1,r1,SL_PC
301
302 /* Restore various CPU config stuffs */
303 bl __restore_cpu_setup
304
305 /* Make sure all FPRs have been initialized */
306 bl reloc_offset
307 bl __init_fpu_registers
308
309 /* Invalidate & enable L1 cache, we don't care about
310 * whatever the ROM may have tried to write to memory
311 */
312 bl __inval_enable_L1
313
314 /* Restore the BATs, and SDR1. Then we can turn on the MMU. */
315 lwz r4,SL_SDR1(r1)
316 mtsdr1 r4
317 lwz r4,SL_SPRG0(r1)
318 mtsprg 0,r4
319 lwz r4,SL_SPRG0+4(r1)
320 mtsprg 1,r4
321 lwz r4,SL_SPRG0+8(r1)
322 mtsprg 2,r4
323 lwz r4,SL_SPRG0+12(r1)
324 mtsprg 3,r4
325
326 lwz r4,SL_DBAT0(r1)
327 mtdbatu 0,r4
328 lwz r4,SL_DBAT0+4(r1)
329 mtdbatl 0,r4
330 lwz r4,SL_DBAT1(r1)
331 mtdbatu 1,r4
332 lwz r4,SL_DBAT1+4(r1)
333 mtdbatl 1,r4
334 lwz r4,SL_DBAT2(r1)
335 mtdbatu 2,r4
336 lwz r4,SL_DBAT2+4(r1)
337 mtdbatl 2,r4
338 lwz r4,SL_DBAT3(r1)
339 mtdbatu 3,r4
340 lwz r4,SL_DBAT3+4(r1)
341 mtdbatl 3,r4
342 lwz r4,SL_IBAT0(r1)
343 mtibatu 0,r4
344 lwz r4,SL_IBAT0+4(r1)
345 mtibatl 0,r4
346 lwz r4,SL_IBAT1(r1)
347 mtibatu 1,r4
348 lwz r4,SL_IBAT1+4(r1)
349 mtibatl 1,r4
350 lwz r4,SL_IBAT2(r1)
351 mtibatu 2,r4
352 lwz r4,SL_IBAT2+4(r1)
353 mtibatl 2,r4
354 lwz r4,SL_IBAT3(r1)
355 mtibatu 3,r4
356 lwz r4,SL_IBAT3+4(r1)
357 mtibatl 3,r4
358
359BEGIN_MMU_FTR_SECTION
360 lwz r4,SL_DBAT4(r1)
361 mtspr SPRN_DBAT4U,r4
362 lwz r4,SL_DBAT4+4(r1)
363 mtspr SPRN_DBAT4L,r4
364 lwz r4,SL_DBAT5(r1)
365 mtspr SPRN_DBAT5U,r4
366 lwz r4,SL_DBAT5+4(r1)
367 mtspr SPRN_DBAT5L,r4
368 lwz r4,SL_DBAT6(r1)
369 mtspr SPRN_DBAT6U,r4
370 lwz r4,SL_DBAT6+4(r1)
371 mtspr SPRN_DBAT6L,r4
372 lwz r4,SL_DBAT7(r1)
373 mtspr SPRN_DBAT7U,r4
374 lwz r4,SL_DBAT7+4(r1)
375 mtspr SPRN_DBAT7L,r4
376 lwz r4,SL_IBAT4(r1)
377 mtspr SPRN_IBAT4U,r4
378 lwz r4,SL_IBAT4+4(r1)
379 mtspr SPRN_IBAT4L,r4
380 lwz r4,SL_IBAT5(r1)
381 mtspr SPRN_IBAT5U,r4
382 lwz r4,SL_IBAT5+4(r1)
383 mtspr SPRN_IBAT5L,r4
384 lwz r4,SL_IBAT6(r1)
385 mtspr SPRN_IBAT6U,r4
386 lwz r4,SL_IBAT6+4(r1)
387 mtspr SPRN_IBAT6L,r4
388 lwz r4,SL_IBAT7(r1)
389 mtspr SPRN_IBAT7U,r4
390 lwz r4,SL_IBAT7+4(r1)
391 mtspr SPRN_IBAT7L,r4
392END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
393
394 /* Flush all TLBs */
395 lis r4,0x1000
3961: addic. r4,r4,-0x1000
397 tlbie r4
398 blt 1b
399 sync
400
401 /* restore the MSR and turn on the MMU */
402 lwz r3,SL_MSR(r1)
403 bl turn_on_mmu
404
405 /* get back the stack pointer */
406 tovirt(r1,r1)
407
408 /* Restore TB */
409 li r3,0
410 mttbl r3
411 lwz r3,SL_TB(r1)
412 lwz r4,SL_TB+4(r1)
413 mttbu r3
414 mttbl r4
415
416 /* Restore the callee-saved registers and return */
417 lwz r0,SL_CR(r1)
418 mtcr r0
419 lwz r2,SL_R2(r1)
420 lmw r12,SL_R12(r1)
421 addi r1,r1,SL_SIZE
422 lwz r0,4(r1)
423 mtlr r0
424 blr
425
426turn_on_mmu:
427 mflr r4
428 tovirt(r4,r4)
429 mtsrr0 r4
430 mtsrr1 r3
431 sync
432 isync
433 rfi
434
435#endif /* defined(CONFIG_PM) || defined(CONFIG_CPU_FREQ) */
436
437 .section .data
438 .balign L1_CACHE_BYTES
439sleep_storage:
440 .long 0
441 .balign L1_CACHE_BYTES, 0
442
443#endif /* CONFIG_PPC_BOOK3S_32 */
444 .section .text