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192.168.1.100 / T108 / c2023d5d03be91dbb983606f0ec5e9e4ea36c8c2 / . / marvell / linux / drivers / mfd / es8311.c
blob: d28a65538f414014d5c44013e40112c422afacaa [file] [log] [blame]
b.liub17525e2025-05-14 17:22:29 +0800[diff] [blame]1/*
2 * Base driver for ASR es8311
3 *
4 * Copyright (C) 2019 ASR.
5 *
6 * This file is subject to the terms and conditions of the GNU General
7 * Public License. See the file "COPYING" in the main directory of this
8 * archive for more details.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#include <linux/kernel.h>
21#include <linux/module.h>
22#include <linux/i2c.h>
23#include <linux/irq.h>
24#include <linux/mfd/core.h>
25#include <linux/mfd/88pm80x.h>
26#include <linux/slab.h>
27#include <linux/delay.h>
28#include <linux/of_device.h>
29#include <linux/uaccess.h>
30#include <linux/proc_fs.h>
31#include <linux/fs.h>
32#include <linux/debugfs.h>
33#include <sound/pcm.h>
34#include <sound/soc.h>
35#include <linux/gpio.h>
36//#include <plat/mfp.h>
37#include <linux/regulator/consumer.h>
38#include <linux/pinctrl/consumer.h>
39#include <linux/platform_device.h>
40#include <linux/mutex.h>
41#include <linux/of.h>
42#include <linux/of_gpio.h>
43#include <asm/io.h>
44#include <linux/interrupt.h>
45#include <linux/cputype.h>
46#include <soc/asr/addr-map.h>
47#include "es8311.h"
48#include <linux/clk.h>
49
50#ifndef APB_VIRT_BASE
51#define APB_VIRT_BASE IOMEM(0xfe000000)
52#endif
53
54#define SSP1_I2S_CLOCK_REG_ADDR (0xD4050044)
55
56#ifdef Kestrel_Z2
57//Kestrel Z2
58static void __iomem *VCXO_OUT_MFPR_reg = APB_VIRT_BASE + 0x1E000 + 0x208;/* 0xD401E000+0x208 */
59static void __iomem *PM_MN_CLK_reg = APB_VIRT_BASE + 0x51000 + 0xA4;/* 0xD4051000+0xA4 */
60static void __iomem *GPCR_reg = APB_VIRT_BASE + 0x50000 + 0x30;/* 0xD4050030 */
61#else
62//Kestrel A0
63static void __iomem *MCLK_CLK_CTRL_reg = NULL;/* 0xD6800000+0x4C */
64static void __iomem *MCLK_MN_DIV_reg = NULL;/* 0xD6800000+0x50 */
65#endif
66
67//NezhaC/Falcon
68static void __iomem *SSP1_I2S_CLOCK_reg = APB_VIRT_BASE + 0x50000 + 0x44;/* 0xD4050000+0x44 */
69
70#if defined(CONFIG_CODEC_PCM_NB)
71/* Narrowband */
72char Audio_Codec_Fsync_Rate = 0;
73#elif defined(CONFIG_CODEC_PCM_WB)
74/* Wideband */
75char Audio_Codec_Fsync_Rate = 1;
76#elif defined(CONFIG_CODEC_PCM_32KHz)
77/* 32KHz */
78char Audio_Codec_Fsync_Rate = 2;
79#elif defined(CONFIG_CODEC_PCM_48KHz)
80/* 48KHz */
81char Audio_Codec_Fsync_Rate = 3;
82#else
83/* Narrowband */
84char Audio_Codec_Fsync_Rate = 0;
85#endif
86
87#ifdef CONFIG_CODEC_PCM_MASTER
88/* CODEC is master, GSSP is slave. */
89
90char G_AudioModemMaster = 0;
91#else
92/* CODEC PCM config is slave in config/defconfig_asr1802sp201
93 CODEC is slave, GSSP is master. */
94
95char G_AudioModemMaster = 1;
96#endif
97
98static const struct i2c_device_id es8311_id_table[] = {
99 {"es8311", 0},
100 {} /* NULL terminated */
101};
102MODULE_DEVICE_TABLE(i2c, es8311_id_table);
103
104static const struct of_device_id es8311_dt_ids[] = {
105 { .compatible = "asrmicro,es8311", },
106 {},
107};
108MODULE_DEVICE_TABLE(of, es8311_dt_ids);
109
110static struct i2c_client *g_es8311_client = NULL;
111static struct pinctrl *g_es8311_pinctrl = NULL;
112static struct device_node *g_es8311_node = NULL;
113static void __iomem *i2s_clk_reg = NULL;
114
115static int gpio_tds_dio10 = 0; /* GPIO[78] */
116static int gpio_vcxo_out = 0; /* GPIO[126] */
117static int gpio_31_CODEC_1V8_EN = 0; /* GPIO[31] */
118static int gpio_32_CODEC_3V3_EN = 0; /* GPIO[32] */
119static struct regulator *es8311_regulator_vdd_1v8 = NULL;
120static struct regulator *es8311_regulator_vdd_3v3 = NULL;
121
122#ifdef HEADSET_DETECTION
123static int gpio_CODEC_IRQ = 0; /* GPIO[1] */
124static int irq_codec;
125#endif
126
127//#define HEADSET_DETECTION
128//#define ES8311_DEBUG
129//#define ES8311_DEBUG_CLOSE
130
yu.dongb3e49372025-06-23 23:57:56 -0700[diff] [blame]131#define CONFIG_CODEC_VDDD_EN 1
132static int gpio_codec_vddd_en = -1;
133
b.liub17525e2025-05-14 17:22:29 +0800[diff] [blame]134#define es8311_reg_NUM 0xFF
135/* base functions */
136
137static unsigned short es8311_readable_register(unsigned int reg)
138{
139 switch (reg) {
140 case ES8311_RESET_REG00:
141 case ES8311_CLK_MANAGER_REG01:
142 case ES8311_CLK_MANAGER_REG02:
143 case ES8311_CLK_MANAGER_REG03:
144 case ES8311_CLK_MANAGER_REG04:
145 case ES8311_CLK_MANAGER_REG05:
146 case ES8311_CLK_MANAGER_REG06:
147 case ES8311_CLK_MANAGER_REG07:
148 case ES8311_CLK_MANAGER_REG08:
149 case ES8311_SDPIN_REG09:
150 case ES8311_SDPOUT_REG0A:
151 case ES8311_SYSTEM_REG0B:
152 case ES8311_SYSTEM_REG0C:
153 case ES8311_SYSTEM_REG0D:
154 case ES8311_SYSTEM_REG0E:
155 case ES8311_SYSTEM_REG0F:
156 case ES8311_SYSTEM_REG10:
157 case ES8311_SYSTEM_REG11:
158 case ES8311_SYSTEM_REG12:
159 case ES8311_SYSTEM_REG13:
160 case ES8311_SYSTEM_REG14:
161 case ES8311_ADC_REG15:
162 case ES8311_ADC_REG16:
163 case ES8311_ADC_REG17:
164 case ES8311_ADC_REG18:
165 case ES8311_ADC_REG19:
166 case ES8311_ADC_REG1A:
167 case ES8311_ADC_REG1B:
168 case ES8311_ADC_REG1C:
169 case ES8311_ADC_REG1E:
170 case ES8311_DAC_REG31:
171 case ES8311_DAC_REG32:
172 case ES8311_DAC_REG33:
173 case ES8311_PRIV_INDEX:
174 case ES8311_PRIV_DATA:
175 case ES8311_DAC_REG34:
176 case ES8311_DAC_REG35:
177 case ES8311_DAC_REG37:
178 case ES8311_GPIO_REG44:
179 case ES8311_GP_REG45:
180 case ES8311_CHD1_REGFD:
181 case ES8311_CHD2_REGFE:
182 case ES8311_CHVER_REGFF:
183 return 1;
184 default:
185 return 0;
186 }
187}
188
189/******************************************************************************
190 * Function : es8311_reg_read
191 *******************************************************************************
192 *
193 * Description :
194 *
195 * Parameters : char RegAddr
196 * Parameters : unsigned short *value
197 *
198 * Output Param : None.
199 *
200 * Return value :
201 *
202 * Notes :
203 *******************************************************************************/
204static int es8311_reg_read(struct i2c_client *client, char reg)
205{
206 char data[1] = {0};
207 int value = 0x0;
208
209 data[0] = reg & 0xFF;
210
211 if(i2c_master_send(client, data, 1) == 1) {
212 i2c_master_recv(client, data, 1);
213 value = data[0];
214#ifdef ES8311_DEBUG
215 printk(KERN_INFO"%s: es8311 read reg:[0x%02x]=0x%02x\n", __FUNCTION__, reg, value);
216#endif
217 return value;
218 } else {
219 printk(KERN_INFO"%s: es8311 read failed.\n", __FUNCTION__);
220 return -EIO;
221 }
222}
223
224
225static int es8311_read(char reg, unsigned short *oValue)
226{
227 int value;
228
229 value = es8311_reg_read(g_es8311_client, reg);
230
231 if (value < 0)
232 {
233 printk(KERN_INFO"%s: es8311_reg read failed.\n", __FUNCTION__);
234
235 *oValue = 0x00;
236 return -EIO;
237 }
238
239 *oValue = value & 0xFF;
240
241 return 0;
242}
243/******************************************************************************
244 * Function : es8311_write
245 *******************************************************************************
246 *
247 * Description :
248 *
249 * Parameters : char RegAddr
250 * Parameters : unsigned short RegData
251 *
252 * Output Param : None.
253 *
254 * Return value :
255 *
256 * Notes :
257 *******************************************************************************/
258static int es8311_reg_write(struct i2c_client *client, char reg, unsigned short value)
259{
260 char data[3] = {0};
261
262 data[0] = reg & 0xFF;
263 // data[1] = (char)((value >> 8) & 0xFF);
264 data[1] = (char)(value & 0xFF);
265
266 if (i2c_master_send(client, data, 2) == 2) {
267#ifdef ES8311_DEBUG
268 printk(KERN_INFO"%s=> reg:0x%02x,value:0x%02x success\n", __FUNCTION__, reg, value);
269#endif
270 return 0;
271 } else {
272 printk(KERN_INFO"%s=> reg:0x%02x,value:0x%02x error\n", __FUNCTION__, reg, value);
273 return -1;
274 }
275}
276
277static int es8311_write(char reg, unsigned short value)
278{
279 int ret;
280
281#ifdef ES8311_DEBUG_CLOSE
282 unsigned short read_value;
283#endif
284
285 ret = es8311_reg_write(g_es8311_client, reg, value);
286 if (ret < 0)
287 {
288 printk(KERN_INFO"%s:L%d: es8311_write() error.\n", __FUNCTION__, __LINE__);
289 }
290
291#ifdef ES8311_DEBUG_CLOSE
292 //for check whether write is OK or not.
293 ret = es8311_read(reg, &read_value);
294 if (ret < 0)
295 {
296 printk(KERN_INFO"%s:L%d: es8311_read() error.\n", __FUNCTION__, __LINE__);
297 }
298
299 printk(KERN_INFO"%s:L%d: reg=0x%02x, value=0x%04x, read_value=0x%04x. Please check it:%s.\n",
300 __FUNCTION__, __LINE__, reg, value, read_value, (value == read_value)?"OK":"FAIL");
301#endif
302 return ret;
303}
304
305static int es8311_update_bit(char reg, unsigned short mask, unsigned short value)
306{
307 int status = 0;
308 unsigned short orig = 0;
309 unsigned short tmp = 0;
310
311 status = es8311_read(reg, &orig);
312 if (status < 0)
313 {
314 printk(KERN_INFO"%s:L%d: es8311_read() error.\n", __FUNCTION__, __LINE__);
315 return status;
316 }
317 else
318 {
319 tmp = orig & (~mask);
320 tmp |= (value & mask);
321
322 if (tmp != orig)
323 {
324 status = es8311_write(reg, tmp);
325 if (status < 0)
326 {
327 printk(KERN_INFO"%s:L%d: es8311_write() error.\n", __FUNCTION__, __LINE__);
328 return status;
329 }
330 }
331 }
332
333#ifdef ES8311_DEBUG_CLOSE
334 printk(KERN_INFO"%s:L%d: reg=0x%02x, mask=0x%02x, value=0x%04x, orig=0x%04x, last_value=0x%04x, please check it:%s.\n",
335 __FUNCTION__, __LINE__, reg, mask, value, orig, tmp, (orig == tmp)?"EQUAL":"UNEQUAL");
336#endif
337
338 return status;
339}
340
341static int es8311_index_read(char RegAddr, unsigned short *value)
342{
343 int status = -1;
344
345 status = es8311_write(ES8311_PRIV_INDEX, RegAddr);
346 if (status != 0)
347 {
348 printk(KERN_INFO"status: %d, RegAddr: 0x%04x\n", status, RegAddr);
349 return status;
350 }
351
352 status = es8311_read(ES8311_PRIV_DATA, value);
353 if (status != 0)
354 {
355 printk(KERN_INFO"status: %d, RegAddr: 0x%04x\n", status, RegAddr);
356 return status;
357 }
358
359 return status;
360}
361
362static int es8311_index_write(char RegAddr, unsigned short value)
363{
364 int status = -1;
365
366 status = es8311_write(ES8311_PRIV_INDEX, RegAddr);
367 if (status != 0)
368 {
369 printk(KERN_INFO"status: %d, RegAddr: 0x%04x\n", status, RegAddr);
370 return status;
371 }
372
373 status = es8311_write(ES8311_PRIV_DATA, value);
374 if (status != 0)
375 {
376 printk(KERN_INFO"status: %d, RegAddr: 0x%04x\n", status, RegAddr);
377 return status;
378 }
379
380 return status;
381}
382
383static int es8311_index_update_bits(char RegAddr, unsigned short mask, unsigned short value)
384{
385 int status = -1;
386 unsigned short orig;
387 unsigned short tmp;
388
389 status = es8311_index_read(RegAddr, &orig);
390 if (status != 0)
391 {
392 printk(KERN_INFO"status: %d, RegAddr: 0x%04x\n", status, RegAddr);
393 }
394 else
395 {
396 tmp = orig & (~mask);
397 tmp |= (value & mask);;
398
399 if (tmp != orig)
400 {
401 status = es8311_index_write(RegAddr, tmp);
402 if (status != 0)
403 {
404 printk(KERN_INFO"status: %d, RegAddr: 0x%04x\n", status, RegAddr);
405 }
406 }
407 }
408
409 return status;
410}
411
412
413#define ES8311_STATE_OFF 0x00
414
415static char es8311_init_ok = 0;
416static char connect_ES8311 = 0;
417static char ES8311_work_state = ES8311_STATE_OFF;
418
419static char l_connect_es8311 = 0;
420
421int es8311_is_connect(void)
422{
423 return l_connect_es8311;
424}
425
426int codec_es8311_init(void)
427{
428 static char es8311_init_ok = 0;
429 short value = 0;
430
431 if(0 == es8311_init_ok){
432 //codec_es8311_enable_mfpr();
433 /* check if has codec es8311*/
434 es8311_read(0xFE, &value);
435
436 if (0x10EC == value) {
437 es8311_write(0x00, 0x00);
438 es8311_init_ok = 1;
439 l_connect_es8311 = 1;
440
441 es8311_init_ok = 1;
442 connect_ES8311 = 1;
443 }
444 }
445
446 printk(KERN_INFO"%s:L%d: es8311_init_ok=%d, l_connect_es8311 =%d.\n",
447 __FUNCTION__, __LINE__, es8311_init_ok, l_connect_es8311);
448
449 return !es8311_init_ok;
450}
451
452static int g_8311_mclk_type = 1; /* 0: use bitclk, 1: use i2s_mclk, 2, use bitclk and turn on i2s_mclk */
453static int g_8311_mainmic_type = 0; /* 0: differential mode, 1: single mode */
454
455/***********************************************************************
456 INTCBind() could only use one lisr for ***all*** GPIOs,
457 So, headset detection is disabled by default on ASR1802S EVB.
458
459 So, we need to set g_8311_headset_plugged=1 by default;
460 thus user just need to plugin headset and no other operation/command is needed.
461 ************************************************************************/
462static int g_8311_headset_plugged = 1; /* 0: headset plug out, 1: headset plug in */
463static int g_8311_headset_mic = 0; /* 0: without HS_MIC, 1: with HS_MIC */
464
465/***********************************************************************
466 When we enable headset detection, could not power off codec
467 i.e could not call codec_ES8311_power_on/codec_es8311_power_off
468 ************************************************************************/
469int g_8311_headset_detection_enabled = 0; /* 0: disable, 1: enable */
470
471#define is_speaker_on() (ES8311_work_state & 0x01)
472#define is_headphone_on() (ES8311_work_state & 0x02)
473#define is_main_mic_on() (ES8311_work_state & 0x04)
474#define is_headset_mic_on() (ES8311_work_state & 0x08)
475
476struct reg_value_group {
477 char reg;
478 unsigned short mask;
479 unsigned short value;
480};
481
482void disable_8311_MClock(void);
483void enable_8311_MClock(void);
484
485static int disableES8311 = 0;
486static int disableES8311HsMic = 0;
487void disableCodecES8311(void)
488{
489 disableES8311 = 1;
490}
491
492static int disableES8311DefaultPower = 0;
493void disableCodecES8311Power(void)
494{
495 disableES8311DefaultPower = 1;
496}
497
498void disableCodecES8311HsMic(void)
499{
500 disableES8311HsMic = 1;
501}
502
503int codec_es8311_is_connect(void)
504{
505 return connect_ES8311;
506}
507
508static void ES8311_set_work_state(char device, char onoff)
509{
510 if (device == ES8311_OUTPUT_DEVICE_SPEAKER)
511 {
512 if (onoff == ES8311_DEVICE_OFF)
513 {
514 ES8311_work_state &= 0xFE;
515 }
516 else if (onoff == ES8311_DEVICE_ON)
517 {
518 ES8311_work_state |= 0x01;
519 }
520 }
521 else if (device == ES8311_OUTPUT_DEVICE_HEADPHONE)
522 {
523 if (onoff == ES8311_DEVICE_OFF)
524 {
525 ES8311_work_state &= 0xFD;
526 }
527 else if (onoff == ES8311_DEVICE_ON)
528 {
529 ES8311_work_state |= 0x02;
530 }
531 }
532 else if (device == ES8311_INPUT_DEVICE_MAIN_MIC)
533 {
534 if (onoff == ES8311_DEVICE_OFF)
535 {
536 ES8311_work_state &= 0xFB;
537 }
538 else if (onoff == ES8311_DEVICE_ON)
539 {
540 ES8311_work_state |= 0x04;
541 }
542 }
543 else if (device == ES8311_INPUT_DEVICE_HEADSET_MIC)
544 {
545 if (onoff == ES8311_DEVICE_OFF)
546 {
547 ES8311_work_state &= 0xF7;
548 }
549 else if (onoff == ES8311_DEVICE_ON)
550 {
551 ES8311_work_state |= 0x08;
552 }
553 }
554}
555
556/* audio control functions */
557static void es8311_speaker_on(void)
558{
559#if 1
560 es8311_index_write(0x3D, 0x3600); /*DAC Clock1 Generator Enable*/
561 es8311_write(0x63, 0xf8de); /*LOUTMIX Power On*/
562 es8311_write(0x61, 0x9804); /*DACL1 Power On*/
563 es8311_write(0x62, 0x8800); /*Stereo1 DAC Digital Filter Power On*/
564 es8311_write(0x65, 0xc800); /*OUTMIXL Power On*/
565 es8311_write(0x66, 0x3000); /*OUTVOLL Power On*/
566 es8311_write(0x8F, 0x3100); /*HP Deop Mode mode 2*/
567 es8311_write(0x2A, 0x1250); /*DACL1 to Stereo DAC left Mixer*/
568 es8311_write(0x4F, 0x0278); /*DACL1 to OUTMIXL*/
569 es8311_write(0x52, 0x0278); /*DACR1 to OUTMIXR*/
570 es8311_write(0x53, 0xc000); /*OUTVOLL to LOUTMIX Unmute*/
571 es8311_write(0x03, 0x0808); /*LOUTL Unmute*/
572 es8311_write(0x73, 0x0102); /*Stereo DAC sample Rate 128 FS*/
573 es8311_write(0x05, 0x8000); /*enable Differential Line Output*/
574#else
575 es8311_index_update_bits(0x3D, 1 << 10, 1 << 10); /*DAC Clock1 Generator Enable*/
576 es8311_index_update_bits(0x3D, 1 << 9, 1 << 9); /*DAC Clock2 Generator Enable*/
577 es8311_update_bit(0x63, 1 << 12, 1 << 12); /*LOUTMIX Power On*/
578 es8311_update_bit(0x61, 1 << 12, 1 << 12); /*DACL1 Power On*/
579 es8311_update_bit(0x61, 1 << 11, 1 << 11); /*DACR1 Power On*/
580 es8311_update_bit(0x62, 1 << 11, 1 << 11); /*Stereo1 DAC Digital Filter Power On*/
581 es8311_update_bit(0x65, 1 << 15, 1 << 15); /*OUTMIXL Power On*/
582 es8311_update_bit(0x65, 1 << 14, 1 << 14); /*OUTMIXR Power On*/
583 es8311_update_bit(0x66, 1 << 13, 1 << 13); /*OUTVOLL Power On*/
584 es8311_update_bit(0x66, 1 << 12, 1 << 12); /*OUTVOLR Power On*/
585 es8311_update_bit(0x8F, 1 << 13, 1 << 13); /*HP Deop Mode mode 2*/
586 es8311_update_bit(0x2A, 1 << 14, 0); /*DACL1 to Stereo DAC left Mixer*/
587 es8311_update_bit(0x2A, 1 << 1, 0); /*DACL1 to Stereo DAC Right Mixer*/
588 es8311_update_bit(0x4F, 1, 0); /*DACL1 to OUTMIXL*/
589 es8311_update_bit(0x52, 1, 0); /*DACR1 to OUTMIXR*/
590 es8311_update_bit(0x53, 1 << 13, 0); /*OUTVOLL to LOUTMIX Unmute*/
591 es8311_update_bit(0x53, 1 << 12, 0); /*OUTVOLR to LOUTMIX Unmute*/
592 es8311_update_bit(0x03, 1 << 15, 0); /*LOUTL Unmute*/
593 es8311_update_bit(0x03, 1 << 14, 0); /*OUTVOLL Unmute*/
594 es8311_update_bit(0x03, 1 << 7, 0); /*LOUTR Unmute*/
595 es8311_update_bit(0x03, 1 << 6, 0); /*OUTVOLR Unmute*/
596 es8311_update_bit(0x73, 3 << 2, 0 << 2); /*Stereo DAC sample Rate 128 FS*/
597 es8311_update_bit(0x05, 1 << 15, 1 << 15); /*enable Differential Line Output*/
598#endif
599}
600
601static void es8311_speaker_off(void)
602{
603#if 1
604 es8311_index_write(0x3D, 0x2000); /*DAC Clock1 Generator Enable*/
605 es8311_write(0x63, 0xe8de); /*LOUTMIX Power Off*/
606 es8311_write(0x61, 0x8000); /*DACL1 Power On*/
607 es8311_write(0x62, 0x0000); /*Stereo1 DAC Digital Filter Power On*/
608 es8311_write(0x65, 0x0000); /*OUTMIXL Power On*/
609 es8311_write(0x66, 0x0000); /*OUTVOLL Power On*/
610 es8311_write(0x8F, 0x1100); /*HP Deop Mode mode 2*/
611 es8311_write(0x2A, 0x5250); /*DACL1 to Stereo DAC left Mixer*/
612 es8311_write(0x4F, 0x0279); /*DACL1 to OUTMIXL*/
613 es8311_write(0x52, 0x0279); /*DACR1 to OUTMIXR*/
614 es8311_write(0x53, 0xf000); /*OUTVOLL to LOUTMIX Unmute*/
615 es8311_write(0x03, 0xc8c8); /*LOUTL Unmute*/
616 es8311_write(0x73, 0x0102); /*Stereo DAC sample Rate 128 FS*/
617 es8311_write(0x05, 0x0000); /*disable Differential Line Output*/
618#else
619 es8311_index_update_bits(0x3D, 1 << 10, 0); /*DAC Clock1 Generator Enable*/
620 es8311_index_update_bits(0x3D, 1 << 9, 0); /*DAC Clock2 Generator Enable*/
621 es8311_update_bit(0x63, 1 << 12, 0); /*LOUTMIX Power Off*/
622 es8311_update_bit(0x61, 1 << 12, 0); /*DACL1 Power On*/
623 es8311_update_bit(0x61, 1 << 11, 0); /*DACR1 Power On*/
624 es8311_update_bit(0x62, 1 << 11, 0); /*Stereo1 DAC Digital Filter Power On*/
625 es8311_update_bit(0x65, 1 << 15, 0); /*OUTMIXL Power On*/
626 es8311_update_bit(0x65, 1 << 14, 0); /*OUTMIXR Power On*/
627 es8311_update_bit(0x66, 1 << 13, 0); /*OUTVOLL Power On*/
628 es8311_update_bit(0x66, 1 << 12, 0); /*OUTVOLR Power On*/
629 es8311_update_bit(0x8F, 1 << 13, 0); /*HP Deop Mode mode 2*/
630 es8311_update_bit(0x2A, 1 << 14, 1 << 14); /*DACL1 to Stereo DAC left Mixer*/
631 es8311_update_bit(0x2A, 1 << 6, 1 << 6); /*DACR1 to Stereo DAC Right Mixer*/
632 es8311_update_bit(0x4F, 1, 1); /*DACL1 to OUTMIXL*/
633 es8311_update_bit(0x52, 1, 1); /*DACR1 to OUTMIXR*/
634 es8311_update_bit(0x53, 1 << 13, 1 << 13); /*OUTVOLL to LOUTMIX Unmute*/
635 es8311_update_bit(0x53, 1 << 12, 1 << 12); /*OUTVOLR to LOUTMIX Unmute*/
636 es8311_update_bit(0x03, 1 << 15, 1 << 15); /*LOUTL Unmute*/
637 es8311_update_bit(0x03, 1 << 14, 1 << 14); /*OUTVOLL Unmute*/
638 es8311_update_bit(0x03, 1 << 7, 1 << 7); /*LOUTR Unmute*/
639 es8311_update_bit(0x03, 1 << 6, 1 << 6); /*OUTVOLR Unmute*/
640 es8311_update_bit(0x73, 3 << 2, 0 << 2); /*Stereo DAC sample Rate 128 FS*/
641 es8311_update_bit(0x05, 1 << 15, 0 << 15); /*disable Differential Line Output*/
642#endif
643}
644
645static void es8311_headphone_on(void)
646{
647#if 1
648 es8311_index_write(0x3D, 0x3600); /*DAC Clock1 Generator Enable*/
649 es8311_write(0x61, 0x9804); /*DACL1 Power On*/
650 es8311_write(0x62, 0x8800); /*Stereo1 DAC Digital Filter Power On*/
651 es8311_write(0x65, 0xcc00); /*OUTMIXL Power On*/
652 es8311_write(0x66, 0x0c00); /*HPOVOLL Power On*/
653 es8311_write(0x8E, 0x001d); /*Enable Headphone Output*/
654 es8311_write(0x8F, 0x3100); /*HP Deop Mode mode 2*/
655 es8311_write(0x2A, 0x1250); /*DACL1 to Stereo DAC left Mixer*/
656 es8311_write(0x4F, 0x0278); /*DACL1 to OUTMIXL*/
657 es8311_write(0x52, 0x0278); /*DACR1 to OUTMIXR*/
658 es8311_write(0x45, 0x5000); /*HPOVOL to HPOMIX Unmute*/
659 es8311_write(0x02, 0x0808); /*HPOL UnMute*/
660 es8311_write(0x73, 0x0102); /*Stereo DAC sample Rate 128 FS*/
661
662#else
663 es8311_index_update_bits(0x3D, 1 << 10, 1 << 10); /*DAC Clock1 Generator Enable*/
664 es8311_index_update_bits(0x3D, 1 << 9, 1 << 9); /*DAC Clock2 Generator Enable*/
665 es8311_update_bit(0x61, 1 << 12, 1 << 12); /*DACL1 Power On*/
666 es8311_update_bit(0x61, 1 << 11, 1 << 11); /*DACR1 Power On*/
667 es8311_update_bit(0x62, 1 << 11, 1 << 11); /*Stereo1 DAC Digital Filter Power On*/
668 es8311_update_bit(0x65, 1 << 15, 1 << 15); /*OUTMIXL Power On*/
669 es8311_update_bit(0x65, 1 << 14, 1 << 14); /*OUTMIXR Power On*/
670 es8311_update_bit(0x66, 1 << 11, 1 << 11); /*HPOVOLL Power On*/
671 es8311_update_bit(0x66, 1 << 10, 1 << 10); /*HPOVOLR Power On*/
672 es8311_update_bit(0x8E, 1 << 4, 1 << 4); /*Enable Headphone Output*/
673 es8311_update_bit(0x8E, 1, 1); /*HP Amp All Power On*/
674 es8311_update_bit(0x8F, 1 << 13, 1 << 13); /*HP Deop Mode mode 2*/
675 es8311_update_bit(0x2A, 1 << 14, 0); /*DACL1 to Stereo DAC left Mixer*/
676 es8311_update_bit(0x2A, 1 << 1, 0); /*DACL1 to Stereo DAC Right Mixer*/
677 es8311_update_bit(0x4F, 1, 0); /*DACL1 to OUTMIXL*/
678 es8311_update_bit(0x52, 1, 0); /*DACR1 to OUTMIXR*/
679 es8311_update_bit(0x45, 1 << 13, 0); /*HPOVOL to HPOMIX Unmute*/
680 es8311_update_bit(0x02, 1 << 15, 0); /*HPOL UnMute*/
681 es8311_update_bit(0x02, 1 << 14, 0); /*HPOVOLL Unmute*/
682 es8311_update_bit(0x02, 1 << 7, 0); /*HPOR UnMute*/
683 es8311_update_bit(0x02, 1 << 6, 0); /*HPOVOLR Unmute*/
684 es8311_update_bit(0x73, 3 << 2, 0 << 2); /*Stereo DAC sample Rate 128 FS*/
685
686#endif
687}
688
689static void es8311_headphone_off(void)
690{
691#if 1
692 es8311_index_write(0x3D, 0x2000); /*DAC Clock1 Generator Enable*/
693 es8311_write(0x61, 0x8000); /*DACL1 Power On*/
694 es8311_write(0x62, 0x0000); /*Stereo1 DAC Digital Filter Power On*/
695 es8311_write(0x65, 0x0000); /*OUTMIXL Power On*/
696 es8311_write(0x66, 0x0000); /*HPOVOLL Power On*/
697 es8311_write(0x8E, 0x000c); /*Enable Headphone Output*/
698 es8311_write(0x8F, 0x1100); /*HP Deop Mode mode 2*/
699 es8311_write(0x2A, 0x5252); /*DACR1 to Stereo DAC left Mixer*/
700 es8311_write(0x4F, 0x0279); /*DACL1 to OUTMIXL*/
701 es8311_write(0x52, 0x0279); /*DACR1 to OUTMIXR*/
702 es8311_write(0x45, 0x7000); /*HPOVOL to HPOMIX Unmute*/
703 es8311_write(0x02, 0xc8c8); /*HPOL UnMute*/
704 es8311_write(0x73, 0x0102); /*Stereo DAC sample Rate 128 FS*/
705#else
706 es8311_index_update_bits(0x3D, 1 << 10, 0); /*DAC Clock1 Generator Enable*/
707 es8311_index_update_bits(0x3D, 1 << 9, 0); /*DAC Clock2 Generator Enable*/
708 es8311_update_bit(0x61, 1 << 12, 0); /*DACL1 Power On*/
709 es8311_update_bit(0x61, 1 << 11, 0); /*DACR1 Power On*/
710 es8311_update_bit(0x62, 1 << 11, 0); /*Stereo1 DAC Digital Filter Power On*/
711 es8311_update_bit(0x65, 1 << 15, 0); /*OUTMIXL Power On*/
712 es8311_update_bit(0x65, 1 << 14, 0); /*OUTMIXR Power On*/
713 es8311_update_bit(0x66, 1 << 11, 0); /*HPOVOLL Power On*/
714 es8311_update_bit(0x66, 1 << 10, 0); /*HPOVOLR Power On*/
715 es8311_update_bit(0x8E, 1 << 4, 0); /*Enable Headphone Output*/
716 es8311_update_bit(0x8E, 1, 0); /*HP Amp All Power On*/
717 es8311_update_bit(0x8F, 1 << 13, 0); /*HP Deop Mode mode 2*/
718 es8311_update_bit(0x2A, 1 << 14, 1 << 14); /*DACR1 to Stereo DAC left Mixer*/
719 es8311_update_bit(0x2A, 1 << 1, 1 << 1); /*DACL1 to Stereo DAC Right Mixer*/
720 es8311_update_bit(0x4F, 1, 1); /*DACL1 to OUTMIXL*/
721 es8311_update_bit(0x52, 1, 1); /*DACR1 to OUTMIXR*/
722 es8311_update_bit(0x45, 1 << 13, 1 << 13); /*HPOVOL to HPOMIX Unmute*/
723 es8311_update_bit(0x02, 1 << 15, 1 << 15); /*HPOL UnMute*/
724 es8311_update_bit(0x02, 1 << 14, 1 << 14); /*HPOVOLL Unmute*/
725 es8311_update_bit(0x02, 1 << 7, 1 << 7); /*HPOR UnMute*/
726 es8311_update_bit(0x02, 1 << 6, 1 << 6); /*HPOVOLR Unmute*/
727 es8311_update_bit(0x73, 3 << 2, 0 << 2); /*Stereo DAC sample Rate 128 FS*/
728#endif
729}
730
731static void es8311_main_mic_on(void)
732{
733#if 1
734 es8311_index_write(0x3D, 0x3600); /*ADC Clock Genaral Enable*/
735 es8311_write(0x65, 0xc800); /*RECMIXL Power On*/
736 es8311_write(0x61, 0x9804); /*ADCL Power On*/
737 es8311_write(0x62, 0x8800); /*Stereo ADC Digital Filter Power On*/
738 es8311_write(0x64, 0x4a00); /*BST2 Power On*/
739 es8311_write(0x0D, 0x0540); /*IN2 Boost Control +40dB*/
740 es8311_write(0x73, 0x0102); /*Stereo ADC Over Sample Rate 32 Fs*/
741 es8311_write(0x3C, 0x006b); /*BST2 to RECMIXL Unmute*/
742 es8311_write(0x3E, 0x006b); /*BST1 to RECMIXR Unmute*/
743 es8311_write(0x27, 0x3860); /*Stereo ADC1 Left Channel Unmute*/
744#else
745 es8311_index_update_bits(0x3D, 1 << 12, 1 << 12); /*ADC Clock Genaral Enable*/
746 es8311_update_bit(0x65, 1 << 11, 1 << 11); /*RECMIXL Power On*/
747 es8311_update_bit(0x61, 1 << 2, 1 << 2); /*ADCL Power On*/
748 es8311_update_bit(0x62, 1 << 15, 1 << 15); /*Stereo ADC Digital Filter Power On*/
749 es8311_update_bit(0x64, 1 << 14, 1 << 14); /*BST2 Power On*/
750 es8311_update_bit(0x0D, 0xF << 8, 5 << 8); /*IN2 Boost Control +40dB*/
751 es8311_update_bit(0x0D, 1 << 6, 1 << 6); /*IN2 Differential Mode*/
752 es8311_update_bit(0x73, 3, 2); /*Stereo ADC Over Sample Rate 32 Fs*/
753 es8311_update_bit(0x3C, 1 << 2, 0); /*BST2 to RECMIXL Unmute*/
754 es8311_update_bit(0x3E, 1 << 2, 0); /*BST1 to RECMIXR Unmute*/
755 es8311_update_bit(0x27, 1 << 14, 0); /*Stereo ADC1 Left Channel Unmute*/
756#endif
757}
758
759static void es8311_main_mic_off(void)
760{
761#if 1
762 es8311_index_write(0x3D, 0x2000); /*ADC Clock Genaral Enable*/
763 es8311_write(0x65, 0x0000); /*RECMIXL Power On*/
764 es8311_write(0x61, 0x8000); /*ADCL Power On*/
765 es8311_write(0x62, 0x0000); /*Stereo ADC Digital Filter Power On*/
766 es8311_write(0x64, 0x0a00); /*BST2 Power On*/
767 es8311_write(0x0D, 0x0000); /*IN2 Boost Control +40dB*/
768 es8311_write(0x73, 0x0102); /*Stereo ADC Over Sample Rate 128 Fs*/
769 es8311_write(0x3C, 0x006f); /*BST2 to RECMIXL Unmute*/
770 es8311_write(0x3E, 0x006f); /*BST2 to RECMIXL Unmute*/
771 es8311_write(0x27, 0x7860); /*Stereo ADC1 Left Channel Unmute*/
772#else
773 es8311_index_update_bits(0x3D, 1 << 12, 0); /*ADC Clock Genaral Enable*/
774 es8311_update_bit(0x65, 1 << 11, 0); /*RECMIXL Power On*/
775 es8311_update_bit(0x61, 1 << 2, 0); /*ADCL Power On*/
776 es8311_update_bit(0x62, 1 << 15, 0); /*Stereo ADC Digital Filter Power On*/
777 es8311_update_bit(0x64, 1 << 14, 0); /*BST2 Power On*/
778 es8311_update_bit(0x0D, 0xF << 8, 0); /*IN2 Boost Control +40dB*/
779 es8311_update_bit(0x0D, 1 << 6, 0); /*IN2 Differential Mode*/
780 es8311_update_bit(0x73, 3, 2); /*Stereo ADC Over Sample Rate 128 Fs*/
781 es8311_update_bit(0x3C, 1 << 2, 1 << 2); /*BST2 to RECMIXL Unmute*/
782 es8311_update_bit(0x3E, 1 << 2, 1 << 2); /*BST2 to RECMIXL Unmute*/
783 es8311_update_bit(0x27, 1 << 14, 1 << 14); /*Stereo ADC1 Left Channel Unmute*/
784#endif
785}
786
787static void es8311_headset_mic_on(void)
788{
789#if 1
790 es8311_index_write(0x3D, 0x3600); /*ADC Clock Genaral Enable*/
791 es8311_write(0x65, 0xcc00); /*RECMIXL Power On*/
792 es8311_write(0x61, 0x9804); /*ADCL Power On*/
793 es8311_write(0x62, 0x8800); /*Stereo ADC Digital Filter Power On*/
794 es8311_write(0x0D, 0x5000); /*IN1 Boost Control +40dB*/
795 es8311_write(0x64, 0x4a04); /*BST1 Power On*/
796 es8311_write(0x73, 0x0102); /*Stereo ADC Over Sample Rate 128 Fs*/
797 es8311_write(0x3C, 0x006D); /*BST1 to RECMIXL Unmute*/
798 es8311_write(0x3E, 0x006D); /*BST1 to RECMIXR Unmute*/
799 es8311_write(0x27, 0x3820); /*Stereo ADC1 Left Channel Unmute*/
800#else
801 es8311_index_update_bits(0x3D, 1 << 12, 1 << 12); /*ADC Clock Genaral Enable*/
802 es8311_update_bit(0x65, 1 << 11, 1 << 11); /*RECMIXL Power On*/
803 es8311_update_bit(0x65, 1 << 10, 1 << 10); /*RECMIXR Power On*/
804 es8311_update_bit(0x61, 1 << 2, 1 << 2); /*ADCL Power On*/
805 es8311_update_bit(0x61, 1 << 1, 1 << 1); /*ADCR Power On*/
806 es8311_update_bit(0x62, 1 << 15, 1 << 15); /*Stereo ADC Digital Filter Power On*/
807 es8311_update_bit(0x0D, 0xF << 12, 5 << 12); /*IN1 Boost Control +40dB*/
808 es8311_update_bit(0x64, 1 << 15, 0 << 15); /*BST1 Power On*/
809 es8311_update_bit(0x64, 1 << 4, 1 << 4); /*MIC2 SE Mode single-end mode*/
810 es8311_update_bit(0x73, 3, 2); /*Stereo ADC Over Sample Rate 128 Fs*/
811 es8311_update_bit(0x3C, 1 << 1, 0); /*BST1 to RECMIXL Unmute*/
812 es8311_update_bit(0x3E, 1 << 1, 0); /*BST1 to RECMIXR Unmute*/
813 es8311_update_bit(0x27, 1 << 14, 0); /*Stereo ADC1 Left Channel Unmute*/
814 es8311_update_bit(0x27, 1 << 6, 0); /*Stereo ADC1 Right Channel Unmute*/
815#endif
816}
817
818static void es8311_headset_mic_off(void)
819{
820#if 1
821 es8311_index_write(0x3D, 0x2000); /*ADC Clock Genaral Enable*/
822 es8311_write(0x65, 0x0000); /*recmixl power on*/
823 es8311_write(0x61, 0x8000); /*adcl power on*/
824 es8311_write(0x62, 0x0000); /*stereo adc digital filter power on*/
825 es8311_write(0x0d, 0x0540); /*in1 boost control +40db*/
826 es8311_write(0x64, 0x4a00); /*bst1 power on*/
827 es8311_write(0x73, 0x0102); /*stereo adc over sample rate 128 fs*/
828 es8311_write(0x3c, 0x006b); /*bst1 to recmixl unmute*/
829 es8311_write(0x3e, 0x006b); /*bst1 to recmixr unmute*/
830 es8311_write(0x27, 0x7860); /*stereo adc1 left channel unmute*/
831#else
832 es8311_index_update_bits(0x3D, 1 << 12, 0); /*ADC Clock Genaral Enable*/
833 es8311_update_bit(0x65, 1 << 11, 0); /*RECMIXL Power On*/
834 es8311_update_bit(0x65, 1 << 10, 0); /*RECMIXR Power On*/
835 es8311_update_bit(0x61, 1 << 2, 0); /*ADCL Power On*/
836 es8311_update_bit(0x61, 1 << 1, 0); /*ADCR Power On*/
837 es8311_update_bit(0x62, 1 << 15, 0); /*Stereo ADC Digital Filter Power On*/
838 es8311_update_bit(0x0D, 0xF << 12, 0); /*IN1 Boost Control +40dB*/
839 es8311_update_bit(0x64, 1 << 15, 0); /*BST1 Power On*/
840 es8311_update_bit(0x64, 1 << 4, 0); /*MIC2 SE Mode single-end mode*/
841 es8311_update_bit(0x73, 3, 2); /*Stereo ADC Over Sample Rate 128 Fs*/
842 es8311_update_bit(0x3C, 1 << 1, 1 << 1); /*BST1 to RECMIXL Unmute*/
843 es8311_update_bit(0x3E, 1 << 1, 1 << 1); /*BST1 to RECMIXR Unmute*/
844 es8311_update_bit(0x27, 1 << 14, 1 << 14); /*Stereo ADC1 Left Channel Unmute*/
845 es8311_update_bit(0x27, 1 << 6, 1 << 6); /*Stereo ADC1 Right Channel Unmute*/
846#endif
847}
848
849void es8311_mute_mic(int mute)
850{
851#if 1
852 if (mute) {
853 es8311_write(0x1c, 0xafaf);
854 } else {
855 es8311_write(0x1c, 0x2f2f);
856 }
857#else
858 if (mute) {
859 es8311_update_bit(0x1c, (1 << 15), (1 << 15));
860 es8311_update_bit(0x1c, (1 << 7), (1 << 7));
861 } else {
862 es8311_update_bit(0x1c, (1 << 15), (0 << 15));
863 es8311_update_bit(0x1c, (1 << 7), (0 << 7));
864 }
865#endif
866 return;
867}
868 /*volume level: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 */
869int gain_output_ctrl[11] = { 0x0A, 0x09, 0x08, 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00};
870int gain_digital_vol[11] = { 0xAFAF, 0xB7B7, 0xBFBF, 0xC7C7, 0xCFCF, 0xD7D7, 0xDDDD, 0xE5E5, 0xEDED, 0xF5F5, 0xFFFF};
871
872void es8311_adjust_gain(int gain)
873{
874 /* gain is within 0~10 */
875#if 1
876 es8311_update_bit(0x02, (0x3F << 8), (gain_output_ctrl[gain] << 8));/* Headphone output control */
877 es8311_update_bit(0x02, (0x3F << 0), (gain_output_ctrl[gain] << 0));
878
879 es8311_update_bit(0x03, (0x3F << 8), (gain_output_ctrl[gain] << 8));/* Line Output Control 1 */
880 es8311_update_bit(0x03, (0x3F << 0), (gain_output_ctrl[gain] << 0));
881
882 es8311_write(0x19, gain_digital_vol[gain]); /* DACL1/R1 Digital Volume */
883#else
884 es8311_update_bit(0x02, (0x3F << 8), (gain_output_ctrl[gain] << 8));/* Headphone output control */
885 es8311_update_bit(0x02, (0x3F << 0), (gain_output_ctrl[gain] << 0));
886
887 es8311_update_bit(0x03, (0x3F << 8), (gain_output_ctrl[gain] << 8));/* Line Output Control 1 */
888 es8311_update_bit(0x03, (0x3F << 0), (gain_output_ctrl[gain] << 0));
889
890 es8311_write(0x19, gain_digital_vol[gain]); /* DACL1/R1 Digital Volume */
891#endif
892 return;
893}
894
895void es8311_check_HS_mic(void)
896{
897 /* Enable MICBIAS1 Short Current Detector, Threshold:1500uA */
898 es8311_update_bit(0x93, (7 << 9), (5 << 9));
899 return;
900}
901
902#define ES8311_SPEAKER_ON_REG_GROUP_NUM 23
903static struct reg_value_group ES8311_speaker_on_reg_group[] = {
904 {0x3D, 1 << 10, 1 << 10}, /*DAC Clock1 Generator Enable*/
905 {0x3D, 1 << 9, 1 << 9}, /*DAC Clock2 Generator Enable*/
906 {0x63, 1 << 12, 1 << 12}, /*LOUTMIX Power On*/
907 {0x61, 1 << 12, 1 << 12}, /*DACL1 Power On*/
908 {0x61, 1 << 11, 1 << 11}, /*DACR1 Power On*/
909 {0x62, 1 << 11, 1 << 11}, /*Stereo1 DAC Digital Filter Power On*/
910 {0x65, 1 << 15, 1 << 15}, /*OUTMIXL Power On*/
911 {0x65, 1 << 14, 1 << 14}, /*OUTMIXR Power On*/
912 {0x66, 1 << 13, 1 << 13}, /*OUTVOLL Power On*/
913 {0x66, 1 << 12, 1 << 12}, /*OUTVOLR Power On*/
914 {0x8F, 1 << 13, 1 << 13}, /*HP Deop Mode mode 2*/
915 {0x2A, 1 << 14, 0}, /*DACL1 to Stereo DAC left Mixer*/
916 {0x2A, 1 << 1, 0}, /*DACL1 to Stereo DAC Right Mixer*/
917 {0x4F, 1, 0}, /*DACL1 to OUTMIXL*/
918 {0x52, 1, 0}, /*DACR1 to OUTMIXR*/
919 {0x53, 1 << 13, 0}, /*OUTVOLL to LOUTMIX Unmute*/
920 {0x53, 1 << 12, 0}, /*OUTVOLR to LOUTMIX Unmute*/
921 {0x03, 1 << 15, 0}, /*LOUTL Unmute*/
922 {0x03, 1 << 14, 0}, /*OUTVOLL Unmute*/
923 {0x03, 1 << 7, 0}, /*LOUTR Unmute*/
924 {0x03, 1 << 6, 0}, /*OUTVOLR Unmute*/
925 {0x73, 3 << 2, 0 << 2}, /*Stereo DAC sample Rate 128 FS*/
926 {0x05, 1 << 15, 1 << 15}, /*enable Differential Line Output*/
927};
928
929#define ES8311_SPEAKER_OFF_REG_GROUP_NUM 23
930static struct reg_value_group ES8311_speaker_off_reg_group[] = {
931 {0x3D, 1 << 10, 0}, /*DAC Clock1 Generator Enable*/
932 {0x3D, 1 << 9, 0}, /*DAC Clock2 Generator Enable*/
933 {0x63, 1 << 12, 0}, /*LOUTMIX Power Off*/
934 {0x61, 1 << 12, 0}, /*DACL1 Power On*/
935 {0x61, 1 << 11, 0}, /*DACR1 Power On*/
936 {0x62, 1 << 11, 0}, /*Stereo1 DAC Digital Filter Power On*/
937 {0x65, 1 << 15, 0}, /*OUTMIXL Power On*/
938 {0x65, 1 << 14, 0}, /*OUTMIXR Power On*/
939 {0x66, 1 << 13, 0}, /*OUTVOLL Power On*/
940 {0x66, 1 << 12, 0}, /*OUTVOLR Power On*/
941 {0x8F, 1 << 13, 0}, /*HP Deop Mode mode 2*/
942 {0x2A, 1 << 14, 1 << 14}, /*DACL1 to Stereo DAC left Mixer*/
943 {0x2A, 1 << 6, 1 << 6}, /*DACR1 to Stereo DAC Right Mixer*/
944 {0x4F, 1, 1}, /*DACL1 to OUTMIXL*/
945 {0x52, 1, 1}, /*DACR1 to OUTMIXR*/
946 {0x53, 1 << 13, 1 << 13}, /*OUTVOLL to LOUTMIX Unmute*/
947 {0x53, 1 << 12, 1 << 12}, /*OUTVOLR to LOUTMIX Unmute*/
948 {0x03, 1 << 15, 1 << 15}, /*LOUTL Unmute*/
949 {0x03, 1 << 14, 1 << 14}, /*OUTVOLL Unmute*/
950 {0x03, 1 << 7, 1 << 7}, /*LOUTR Unmute*/
951 {0x03, 1 << 6, 1 << 6}, /*OUTVOLR Unmute*/
952 {0x73, 3 << 2, 0 << 2}, /*Stereo DAC sample Rate 128 FS*/
953 {0x05, 1 << 15, 0 << 15}, /*disable Differential Line Output*/
954};
955
956#define ES8311_HEADPHONE_ON_REG_GROUP_NUM 22
957static struct reg_value_group ES8311_headphone_on_reg_group[] = {
958 {0x3D, 1 << 10, 1 << 10}, /*DAC Clock1 Generator Enable*/
959 {0x3D, 1 << 9, 1 << 9}, /*DAC Clock2 Generator Enable*/
960 {0x61, 1 << 12, 1 << 12}, /*DACL1 Power On*/
961 {0x61, 1 << 11, 1 << 11}, /*DACR1 Power On*/
962 {0x62, 1 << 11, 1 << 11}, /*Stereo1 DAC Digital Filter Power On*/
963 {0x65, 1 << 15, 1 << 15}, /*OUTMIXL Power On*/
964 {0x65, 1 << 14, 1 << 14}, /*OUTMIXR Power On*/
965 {0x66, 1 << 11, 1 << 11}, /*HPOVOLL Power On*/
966 {0x66, 1 << 10, 1 << 10}, /*HPOVOLR Power On*/
967 {0x8E, 1 << 4, 1 << 4}, /*Enable Headphone Output*/
968 {0x8E, 1, 1}, /*HP Amp All Power On*/
969 {0x8F, 1 << 13, 1 << 13}, /*HP Deop Mode mode 2*/
970 {0x2A, 1 << 14, 0}, /*DACL1 to Stereo DAC left Mixer*/
971 {0x2A, 1 << 1, 0}, /*DACL1 to Stereo DAC Right Mixer*/
972 {0x4F, 1, 0}, /*DACL1 to OUTMIXL*/
973 {0x52, 1, 0}, /*DACR1 to OUTMIXR*/
974 {0x45, 1 << 13, 0}, /*HPOVOL to HPOMIX Unmute*/
975 {0x02, 1 << 15, 0}, /*HPOL UnMute*/
976 {0x02, 1 << 14, 0}, /*HPOVOLL Unmute*/
977 {0x02, 1 << 7, 0}, /*HPOR UnMute*/
978 {0x02, 1 << 6, 0}, /*HPOVOLR Unmute*/
979 {0x73, 3 << 2, 0 << 2}, /*Stereo DAC sample Rate 128 FS*/
980};
981
982#define ES8311_HEADPHONE_OFF_REG_GROUP_NUM 22
983static struct reg_value_group ES8311_headphone_off_reg_group[] = {
984 {0x3D, 1 << 10, 0}, /*DAC Clock1 Generator Enable*/
985 {0x3D, 1 << 9, 0}, /*DAC Clock2 Generator Enable*/
986 {0x61, 1 << 12, 0}, /*DACL1 Power On*/
987 {0x61, 1 << 11, 0}, /*DACR1 Power On*/
988 {0x62, 1 << 11, 0}, /*Stereo1 DAC Digital Filter Power On*/
989 {0x65, 1 << 15, 0}, /*OUTMIXL Power On*/
990 {0x65, 1 << 14, 0}, /*OUTMIXR Power On*/
991 {0x66, 1 << 11, 0}, /*HPOVOLL Power On*/
992 {0x66, 1 << 10, 0}, /*HPOVOLR Power On*/
993 {0x8E, 1 << 4, 0}, /*Enable Headphone Output*/
994 {0x8E, 1, 0}, /*HP Amp All Power On*/
995 {0x8F, 1 << 13, 0}, /*HP Deop Mode mode 2*/
996 {0x2A, 1 << 14, 1 << 14}, /*DACR1 to Stereo DAC left Mixer*/
997 {0x2A, 1 << 1, 1 << 1}, /*DACL1 to Stereo DAC Right Mixer*/
998 {0x4F, 1, 1}, /*DACL1 to OUTMIXL*/
999 {0x52, 1, 1}, /*DACR1 to OUTMIXR*/
1000 {0x45, 1 << 13, 1 << 13}, /*HPOVOL to HPOMIX Unmute*/
1001 {0x02, 1 << 15, 1 << 15}, /*HPOL UnMute*/
1002 {0x02, 1 << 14, 1 << 14}, /*HPOVOLL Unmute*/
1003 {0x02, 1 << 7, 1 << 7}, /*HPOR UnMute*/
1004 {0x02, 1 << 6, 1 << 6}, /*HPOVOLR Unmute*/
1005 {0x73, 3 << 2, 0 << 2}, /*Stereo DAC sample Rate 128 FS*/
1006};
1007
1008#define ES8311_MAIN_MIC_ON_REG_GROUP_NUM 11
1009static struct reg_value_group ES8311_main_mic_on_reg_group[] = {
1010 {0x3D, 1 << 12, 1 << 12}, /*ADC Clock Genaral Enable*/
1011 {0x65, 1 << 11, 1 << 11}, /*RECMIXL Power On*/
1012 {0x61, 1 << 2, 1 << 2}, /*ADCL Power On*/
1013 {0x62, 1 << 15, 1 << 15}, /*Stereo ADC Digital Filter Power On*/
1014 {0x64, 1 << 14, 1 << 14}, /*BST2 Power On*/
1015 {0x0D, 0xF << 8, 5 << 8}, /*IN2 Boost Control +40dB*/
1016 {0x0D, 1 << 6, 1 << 6}, /*IN2 Differential Mode*/
1017 {0x73, 3, 2}, /*Stereo ADC Over Sample Rate 32 Fs*/
1018 {0x3C, 1 << 2, 0}, /*BST2 to RECMIXL Unmute*/
1019 {0x3E, 1 << 2, 0}, /*BST1 to RECMIXR Unmute*/
1020 {0x27, 1 << 14, 0}, /*Stereo ADC1 Left Channel Unmute*/
1021};
1022static struct reg_value_group ES8311_main_mic_on_reg_group_singlemode[] = {
1023 {0x3D, 1 << 12, 1 << 12}, /*ADC Clock Genaral Enable*/
1024 {0x65, 1 << 11, 1 << 11}, /*RECMIXL Power On*/
1025 {0x61, 1 << 2, 1 << 2}, /*ADCL Power On*/
1026 {0x62, 1 << 15, 1 << 15}, /*Stereo ADC Digital Filter Power On*/
1027 {0x64, 1 << 14, 1 << 14}, /*BST2 Power On*/
1028 {0x0D, 0xF << 8, 5 << 8}, /*IN2 Boost Control +40dB*/
1029 {0x0D, 1 << 6, 0}, /*IN2 Single Mode*/
1030 {0x73, 3, 2}, /*Stereo ADC Over Sample Rate 32 Fs*/
1031 {0x3C, 1 << 2, 0}, /*BST2 to RECMIXL Unmute*/
1032 {0x3E, 1 << 2, 0}, /*BST1 to RECMIXR Unmute*/
1033 {0x27, 1 << 14, 0}, /*Stereo ADC1 Left Channel Unmute*/
1034};
1035
1036
1037
1038#define ES8311_MAIN_MIC_OFF_REG_GROUP_NUM 11
1039static struct reg_value_group ES8311_main_mic_off_reg_group[] = {
1040 {0x3D, 1 << 12, 0}, /*ADC Clock Genaral Enable*/
1041 {0x65, 1 << 11, 0}, /*RECMIXL Power On*/
1042 {0x61, 1 << 2, 0}, /*ADCL Power On*/
1043 {0x62, 1 << 15, 0}, /*Stereo ADC Digital Filter Power On*/
1044 {0x64, 1 << 14, 0}, /*BST2 Power On*/
1045 {0x0D, 0xF << 8, 0}, /*IN2 Boost Control +40dB*/
1046 {0x0D, 1 << 6, 0}, /*IN2 Differential Mode*/
1047 {0x73, 3, 2}, /*Stereo ADC Over Sample Rate 128 Fs*/
1048 {0x3C, 1 << 2, 1 << 2}, /*BST2 to RECMIXL Unmute*/
1049 {0x3E, 1 << 2, 1 << 2}, /*BST2 to RECMIXL Unmute*/
1050 {0x27, 1 << 14, 1 << 14}, /*Stereo ADC1 Left Channel Unmute*/
1051};
1052
1053#define ES8311_HEADSET_MIC_ON_REG_GROUP_NUM 14
1054static struct reg_value_group ES8311_headset_mic_on_reg_group[] = {
1055 {0x3D, 1 << 12, 1 << 12}, /*ADC Clock Genaral Enable*/
1056 {0x65, 1 << 11, 1 << 11}, /*RECMIXL Power On*/
1057 {0x65, 1 << 10, 1 << 10}, /*RECMIXR Power On*/
1058 {0x61, 1 << 2, 1 << 2}, /*ADCL Power On*/
1059 {0x61, 1 << 1, 1 << 1}, /*ADCR Power On*/
1060 {0x62, 1 << 15, 1 << 15}, /*Stereo ADC Digital Filter Power On*/
1061 {0x0D, 0xF << 12, 5 << 12}, /*IN1 Boost Control +40dB*/
1062 {0x64, 1 << 15, 0 << 15}, /*BST1 Power On*/
1063 {0x64, 1 << 4, 1 << 4}, /*MIC2 SE Mode single-end mode*/
1064 {0x73, 3, 2}, /*Stereo ADC Over Sample Rate 128 Fs*/
1065 {0x3C, 1 << 1, 0}, /*BST1 to RECMIXL Unmute*/
1066 {0x3E, 1 << 1, 0}, /*BST1 to RECMIXR Unmute*/
1067 {0x27, 1 << 14, 0}, /*Stereo ADC1 Left Channel Unmute*/
1068 {0x27, 1 << 6, 0}, /*Stereo ADC1 Right Channel Unmute*/
1069};
1070
1071#define ES8311_HEADSET_MIC_OFF_REG_GROUP_NUM 14
1072static struct reg_value_group ES8311_headset_mic_off_reg_group[] = {
1073 {0x3D, 1 << 12, 0}, /*ADC Clock Genaral Enable*/
1074 {0x65, 1 << 11, 0}, /*RECMIXL Power On*/
1075 {0x65, 1 << 10, 0}, /*RECMIXR Power On*/
1076 {0x61, 1 << 2, 0}, /*ADCL Power On*/
1077 {0x61, 1 << 1, 0}, /*ADCR Power On*/
1078 {0x62, 1 << 15, 0}, /*Stereo ADC Digital Filter Power On*/
1079 {0x0D, 0xF << 12, 0}, /*IN1 Boost Control +40dB*/
1080 {0x64, 1 << 15, 0}, /*BST1 Power On*/
1081 {0x64, 1 << 4, 0}, /*MIC2 SE Mode single-end mode*/
1082 {0x73, 3, 2}, /*Stereo ADC Over Sample Rate 128 Fs*/
1083 {0x3C, 1 << 1, 1 << 1}, /*BST1 to RECMIXL Unmute*/
1084 {0x3E, 1 << 1, 1 << 1}, /*BST1 to RECMIXR Unmute*/
1085 {0x27, 1 << 14, 1 << 14}, /*Stereo ADC1 Left Channel Unmute*/
1086 {0x27, 1 << 6, 1 << 6}, /*Stereo ADC1 Right Channel Unmute*/
1087};
1088/////////////////////////////////////////////////////////////////////////////////
1089
1090#define ES8311_HEADSET_DETECT_ON_REG_GROUP_NUM 3
1091static struct reg_value_group ES8311_headset_detect_on_reg_group[] = {
1092 {0x64, 1 << 2, 1 << 2}, /*JD1 Multilevel Power on*/
1093 {0xC0, 1 << 15, 1 << 15}, /*GPIO1 Pin as IRQ output*/
1094 {0xBD, 7 << 7, 4 << 7}, /*jd1_1, jd1_1_stricky disable, Polarity Normal*/
1095};
1096
1097#define ES8311_HEADSET_DETECT_OFF_REG_GROUP_NUM 3
1098static struct reg_value_group ES8311_headset_detect_off_reg_group[] = {
1099 {0x64, 1 << 2, 0 << 2}, /*JD1 Multilevel Power off*/
1100 {0xC0, 1 << 15, 0 << 15}, /*GPIO1 Pin as IRQ output*/
1101 {0xBD, 7 << 7, 0 << 7}, /*jd1_1, jd1_1_stricky disable, Polarity Normal*/
1102};
1103
1104
1105int es8311_reg_dump(void)
1106{
1107 char index;
1108 unsigned short value;
1109 int status = -1;
1110
1111 printk(KERN_INFO"es8311_reg_dump_enter\n");
1112 for (index = 0; index < 0xFF; index++)
1113 {
1114 // if (es8311_readable_register(index))
1115 // {
1116 status = es8311_read(index, &value);
1117 if (status != 0)
1118 {
1119 printk(KERN_INFO"status: 0x%x\n", status);
1120 return -1;
1121 }
1122 printk(KERN_INFO"index: 0x%x, value: 0x%x\n", index, value);
1123 // }
1124 }
1125
1126 return 0;
1127}
1128
1129/*
1130 I2S1 BCLK Polarity Invert
1131 I2S1 PCM Mode A
1132 */
1133static void ES8311_set_dai_fmt(char enable)
1134{
1135#if 0
1136 if (ES8311_DEVICE_ON == enable)
1137 {
1138 if(0 == G_AudioModemMaster){
1139 /* GSSP is slave, es8311 is master */
1140 es8311_write(0x70, 0x0082);
1141 } else {
1142 /* GSSP is master, es8311 is slave */
1143 es8311_write(0x70, 0x8082);
1144 }
1145 }
1146 else if (ES8311_DEVICE_OFF == enable)
1147 {
1148 if(0 == G_AudioModemMaster){
1149 /* GSSP is slave, es8311 is master */
1150 es8311_write(0x70, 0x0000);
1151 } else {
1152 /* GSSP is master, es8311 is slave */
1153 es8311_write(0x70, 0x8000);
1154 }
1155 }
1156#else
1157 if (ES8311_DEVICE_ON == enable)
1158 {
1159 es8311_update_bit(0x70, (1 << 7) | 3, (1 << 7) | 2);
1160 if(0 == G_AudioModemMaster){// gssp slave, 8311 master
1161 es8311_update_bit(0x70, (1 << 15) , (0 << 15) );// set 8311 master
1162 }
1163 }
1164 else if (ES8311_DEVICE_OFF == enable)
1165 {
1166 es8311_update_bit(0x70, (1 << 7) | 3, 0);
1167 }
1168#endif
1169}
1170
1171/*FS = bitrate = 8K
1172 BCLK = 512K = 64FS , 0x73
1173 FOUT = (sysclk * (N + 2)) / ((M + 2) / (K + 2))
1174 SYSCLK = PLL = 26M
1175 FOUT = (26 * 34) / (9 * 4) = 24.555
1176 CLK = FOUT / 12 = 2048K = 256 * FS
1177 */
1178static void es8311_set_sysclk(char enable)
1179{
1180#if 1
1181 if (ES8311_DEVICE_ON == enable)
1182 {
1183 es8311_write(0xFA, 0x0001); /*Enable MCLK Input*/
1184 es8311_write(0x73, 0x0002); /*DAC Over Sample Rate: 128Fs, ADC Over Sample Rate: 32Fs*/
1185 if (3 == Audio_Codec_Fsync_Rate)
1186 {
1187 printk(KERN_INFO"%s, sys clock comes from PLL when Fsync = 48K.\n", __FUNCTION__);
1188 es8311_update_bit(0x64, 1 << 9, 1 << 9); /*PLL Power On*/
1189 es8311_update_bit(0x73, 7 << 12, 1 << 12); /*sel_i2s_pre_div1 = 1/2*/
1190 }
1191 }
1192 else if (ES8311_DEVICE_OFF == enable)
1193 {
1194 es8311_write(0xFA, 0x0000); /*Disable MCLK Input*/
1195 if (3 == Audio_Codec_Fsync_Rate)
1196 {
1197 printk(KERN_INFO"%s, sys clock comes from PLL when Fsync = 48K.\n", __FUNCTION__);
1198 es8311_update_bit(0x64, 1 << 9, 0); /*PLL Power Off*/
1199 }
1200 }
1201#else
1202 int bclk_type = BCLK_256_FS;
1203
1204 if (ES8311_DEVICE_ON == enable)
1205 {
1206 es8311_update_bit(0xFA, 1, 1); /*Enable MCLK Input*/
1207 es8311_update_bit(0x64, 1 << 9, 1 << 9); /*PLL Power On*/
1208
1209 es8311_update_bit(0x73, 3 << 2, 0 << 2); /*128Fs*/
1210 es8311_update_bit(0x73, 3, 2); /*32Fs*/
1211
1212 if(1 == g_8311_mclk_type){/*use I2S_SYSCLK as MCLK , 2.048M/4.096M*/
1213 es8311_update_bit(0x73, 7 << 12, 0 << 12); /*I2S Clock Pre-Divider = 0 for divide 1*/
1214 }
1215 else if(0 == g_8311_mclk_type){//using bitclk as 8311 mclk
1216 es8311_update_bit(0x73, 7 << 12, 0 << 12); /*I2S Clock Pre-Divider = 0 for divide 1*/
1217 es8311_update_bit(0x80, 3 << 14, 1 << 14); /*System Clock from PLL*/
1218 es8311_update_bit(0x80, 3 << 12, 1 << 12); /*PLL from bclk*/
1219 es8311_update_bit(0x82, 1 << 11, 1 << 11); /*PLL M bypass */
1220
1221 if(BCLK_64_FS == bclk_type){ // 64fs
1222 es8311_update_bit(0x81, 0x1FF << 7 , 6 << 7);/*PLL K = 0,PLL N = 6*/
1223 }
1224 else if(BCLK_128_FS == bclk_type){// 128fs
1225 es8311_update_bit(0x81, 0x1FF << 7 , 2 << 7);/*PLL K = 0,PLL N = 2*/
1226 }
1227 else if(BCLK_256_FS == bclk_type){// 256fs
1228 es8311_update_bit(0x81, 0x1FF << 7 , 0 << 7);/*PLL K = 0,PLL N = 0*/
1229 }
1230 else if(BCLK_32_FS == bclk_type){// 32fs
1231 es8311_update_bit(0x81, 0x1FF << 7 , 14 << 7);/*PLL K = 0,PLL N = 14*/
1232 }
1233
1234 }
1235 }
1236 else if (ES8311_DEVICE_OFF == enable)
1237 {
1238 es8311_update_bit(0xFA, 1, 0); /*disable MCLK Input*/
1239 es8311_update_bit(0x64, 1 << 9, 0); /*PLL Power off*/
1240 }
1241#endif
1242}
1243
1244static void ES8311_set_sys_power(char enable)
1245{
1246 if (ES8311_DEVICE_ON == enable)
1247 {
1248 es8311_update_bit(0x63, 1 << 11, 1 << 11); /*MICBIAS Bandgap Power On*/
1249 es8311_update_bit(0x63, 1 << 15, 1 << 15); /*VREF1 Power On*/
1250 es8311_update_bit(0x63, 1 << 14, 1 << 14); /*VREF Slow*/
1251 es8311_update_bit(0x63, 1 << 4, 1 << 4); /*VREF2 Power On*/
1252 es8311_update_bit(0x63, 1 << 3, 1 << 3); /*VREF2 Slow*/
1253 es8311_update_bit(0x63, 1 << 13, 1 << 13); /*MBIAS Power On*/
1254 es8311_update_bit(0x61, 1 << 15, 1 << 15); /*I2S Power On*/
1255 es8311_update_bit(0x8E, 1 << 3, 1 << 3); /*Charge Pump Power On*/
1256 es8311_update_bit(0x64, 1 << 11, 1 << 11); /*MICBIAS1 Power On*/
1257 }
1258 else if (ES8311_DEVICE_OFF == enable)
1259 {
1260 es8311_update_bit(0x63, 1 << 11, 0); /*MICBIAS Bandgap Power Off*/
1261 es8311_update_bit(0x63, 1 << 15, 0); /*VREF1 Power Off*/
1262 es8311_update_bit(0x63, 1 << 14, 0); /*VREF Slow*/
1263 es8311_update_bit(0x63, 1 << 4, 0); /*VREF2 Power Off*/
1264 es8311_update_bit(0x63, 1 << 3, 0); /*VREF2 Slow*/
1265 es8311_update_bit(0x63, 1 << 13, 0); /*MBIAS Power Off*/
1266 es8311_update_bit(0x61, 1 << 15, 0); /*I2S Power Off*/
1267 es8311_update_bit(0x8E, 1 << 3, 0); /*Charge Pump Power Off*/
1268 es8311_update_bit(0x64, 1 << 11, 0); /*MICBIAS1 Power Off*/
1269 }
1270}
1271
1272static void ES8311_device_enable(char device, char enable)
1273{
1274 int length;
1275 int index;
1276 struct reg_value_group *reg_group = NULL;
1277
1278 if ((device == ES8311_OUTPUT_DEVICE_SPEAKER) && (enable == ES8311_DEVICE_ON))
1279 {
1280 reg_group = ES8311_speaker_on_reg_group;
1281 length = ES8311_SPEAKER_ON_REG_GROUP_NUM;
1282 }
1283 else if ((device == ES8311_OUTPUT_DEVICE_SPEAKER) && (enable == ES8311_DEVICE_OFF))
1284 {
1285 reg_group = ES8311_speaker_off_reg_group;
1286 length = ES8311_SPEAKER_OFF_REG_GROUP_NUM;
1287 }
1288 else if ((device == ES8311_OUTPUT_DEVICE_HEADPHONE) && (enable == ES8311_DEVICE_ON))
1289 {
1290 reg_group = ES8311_headphone_on_reg_group;
1291 length = ES8311_HEADPHONE_ON_REG_GROUP_NUM;
1292 }
1293 else if ((device == ES8311_OUTPUT_DEVICE_HEADPHONE) && (enable == ES8311_DEVICE_OFF))
1294 {
1295 reg_group = ES8311_headphone_off_reg_group;
1296 length = ES8311_HEADPHONE_OFF_REG_GROUP_NUM;
1297 }
1298 else if ((device == ES8311_INPUT_DEVICE_MAIN_MIC) && (enable == ES8311_DEVICE_ON))
1299 {
1300 if(g_8311_mainmic_type == 0)
1301 reg_group = ES8311_main_mic_on_reg_group;
1302 else
1303 reg_group = ES8311_main_mic_on_reg_group_singlemode;
1304 length = ES8311_MAIN_MIC_ON_REG_GROUP_NUM;
1305 }
1306 else if ((device == ES8311_INPUT_DEVICE_MAIN_MIC) && (enable == ES8311_DEVICE_OFF))
1307 {
1308 reg_group = ES8311_main_mic_off_reg_group;
1309 length = ES8311_MAIN_MIC_OFF_REG_GROUP_NUM;
1310 }
1311 else if ((device == ES8311_INPUT_DEVICE_HEADSET_MIC) && (enable == ES8311_DEVICE_ON))
1312 {
1313 reg_group = ES8311_headset_mic_on_reg_group;
1314 length = ES8311_HEADSET_MIC_ON_REG_GROUP_NUM;
1315 }
1316 else if ((device == ES8311_INPUT_DEVICE_HEADSET_MIC) && (enable == ES8311_DEVICE_OFF))
1317 {
1318 reg_group = ES8311_headset_mic_off_reg_group;
1319 length = ES8311_HEADSET_MIC_OFF_REG_GROUP_NUM;
1320 }
1321 else if ((device == ES8311_INPUT_DEVICE_HEADSET_DETECT) && (enable == ES8311_DEVICE_ON))
1322 {
1323 reg_group = ES8311_headset_detect_on_reg_group;
1324 length = ES8311_HEADSET_DETECT_ON_REG_GROUP_NUM;
1325 }
1326 else if ((device == ES8311_INPUT_DEVICE_HEADSET_DETECT) && (enable == ES8311_DEVICE_OFF))
1327 {
1328 reg_group = ES8311_headset_detect_off_reg_group;
1329 length = ES8311_HEADSET_DETECT_OFF_REG_GROUP_NUM;
1330 }
1331
1332 if (reg_group == NULL)
1333 return;
1334
1335 if (enable == ES8311_DEVICE_ON)
1336 {
1337 for (index = 0; index < length; index++)
1338 {
1339 if (reg_group[index].reg != 0x3D)
1340 es8311_update_bit(reg_group[index].reg, reg_group[index].mask, reg_group[index].value);
1341 else
1342 es8311_index_update_bits(reg_group[index].reg, reg_group[index].mask, reg_group[index].value);
1343 }
1344 ES8311_set_work_state(device, enable);
1345 //printk(KERN_INFO"device enabled:%e{ES8311_DEVICE}", device);
1346 }
1347 else if (enable == ES8311_DEVICE_OFF)
1348 {
1349 for (index = 0; index < length; index++)
1350 {
1351 if (reg_group[index].reg != 0x3D)
1352 es8311_update_bit(reg_group[index].reg, reg_group[index].mask, reg_group[index].value);
1353 else
1354 es8311_index_update_bits(reg_group[index].reg, reg_group[index].mask, reg_group[index].value);
1355 }
1356 ES8311_set_work_state(device, enable);
1357 //printk(KERN_INFO"device disabled:%e{ES8311_DEVICE}", device);
1358 }
1359}
1360
1361static void ES8311_speaker_enable(char enable)
1362{
1363#ifdef RECONFIGURE_POWER_INCALL
1364 ES8311_set_dai_fmt(enable);
1365 es8311_set_sysclk(enable);
1366 ES8311_set_sys_power(enable);
1367#endif
1368 ES8311_device_enable(ES8311_OUTPUT_DEVICE_SPEAKER, enable);
1369 return;
1370}
1371
1372static void ES8311_headphone_enable(char enable)
1373{
1374#ifdef RECONFIGURE_POWER_INCALL
1375 ES8311_set_dai_fmt(enable);
1376 es8311_set_sysclk(enable);
1377 ES8311_set_sys_power(enable);
1378#endif
1379
1380 ES8311_device_enable(ES8311_OUTPUT_DEVICE_HEADPHONE, enable);
1381 return;
1382}
1383
1384static void ES8311_main_mic_enable(char enable)
1385{
1386#ifdef RECONFIGURE_POWER_INCALL
1387 ES8311_set_dai_fmt(enable);
1388 es8311_set_sysclk(enable);
1389 ES8311_set_sys_power(enable);
1390#endif
1391
1392 ES8311_device_enable(ES8311_INPUT_DEVICE_MAIN_MIC, enable);
1393 return;
1394}
1395
1396static void ES8311_headset_mic_enable(char enable)
1397{
1398#ifdef RECONFIGURE_POWER_INCALL
1399 ES8311_set_dai_fmt(enable);
1400 es8311_set_sysclk(enable);
1401 ES8311_set_sys_power(enable);
1402#endif
1403
1404 ES8311_device_enable(ES8311_INPUT_DEVICE_HEADSET_MIC, enable);
1405 return;
1406}
1407
1408static void ES8311_device_select(char device, char onoff)
1409{
1410 if (es8311_init_ok == 0)
1411 {
1412 printk(KERN_INFO"ES8311 not init\n");
1413 return;
1414 }
1415 switch (onoff)
1416 {
1417 case ES8311_DEVICE_ON:
1418 if (device == ES8311_OUTPUT_DEVICE_SPEAKER)
1419 {
1420 if (is_speaker_on())
1421 {
1422 printk(KERN_INFO"already enabled\n");
1423 return;
1424 }
1425 else
1426 {
1427 if (is_headphone_on())
1428 {
1429 ES8311_headphone_enable(ES8311_DEVICE_OFF);
1430 }
1431 ES8311_speaker_enable(ES8311_DEVICE_ON);
1432 }
1433 }
1434 else if (device == ES8311_OUTPUT_DEVICE_HEADPHONE)
1435 {
1436 if (is_headphone_on())
1437 {
1438 printk(KERN_INFO"already enabled\n");
1439 return;
1440 }
1441 else
1442 {
1443 if (is_speaker_on())
1444 {
1445 ES8311_speaker_enable(ES8311_DEVICE_OFF);
1446 }
1447 ES8311_headphone_enable(ES8311_DEVICE_ON);
1448 }
1449 }
1450 else if (device == ES8311_INPUT_DEVICE_MAIN_MIC)
1451 {
1452 if (is_main_mic_on())
1453 {
1454 printk(KERN_INFO"already enabled\n");
1455 return;
1456 }
1457 else
1458 {
1459 if (is_headset_mic_on())
1460 {
1461 ES8311_headset_mic_enable(ES8311_DEVICE_OFF);
1462 }
1463 ES8311_main_mic_enable(ES8311_DEVICE_ON);
1464 }
1465 }
1466 else if (device == ES8311_INPUT_DEVICE_HEADSET_MIC)
1467 {
1468 if (is_headset_mic_on())
1469 {
1470 printk(KERN_INFO"already enabled\n");
1471 return;
1472 }
1473 else
1474 {
1475 if (is_main_mic_on())
1476 {
1477 ES8311_main_mic_enable(ES8311_DEVICE_OFF);
1478 }
1479 ES8311_headset_mic_enable(ES8311_DEVICE_ON);
1480 }
1481 }
1482 break;
1483
1484 case ES8311_DEVICE_OFF:
1485 if (device == ES8311_OUTPUT_DEVICE_SPEAKER)
1486 {
1487 if (!is_speaker_on())
1488 {
1489 printk(KERN_INFO"already disabled\n");
1490 return;
1491 }
1492 else
1493 {
1494 ES8311_speaker_enable(ES8311_DEVICE_OFF);
1495 }
1496 }
1497 else if (device == ES8311_OUTPUT_DEVICE_HEADPHONE)
1498 {
1499 if (!is_headphone_on())
1500 {
1501 printk(KERN_INFO"already disabled\n");
1502 return;
1503 }
1504 else
1505 {
1506 ES8311_headphone_enable(ES8311_DEVICE_OFF);
1507 }
1508 }
1509 else if (device == ES8311_INPUT_DEVICE_MAIN_MIC)
1510 {
1511 if (!is_main_mic_on())
1512 {
1513 printk(KERN_INFO"already disabled\n");
1514 return;
1515 }
1516 else
1517 {
1518 ES8311_main_mic_enable(ES8311_DEVICE_OFF);
1519 }
1520 }
1521 else if (device == ES8311_INPUT_DEVICE_HEADSET_MIC)
1522 {
1523 if (!is_headset_mic_on())
1524 {
1525 printk(KERN_INFO"already disabled\n");
1526 return;
1527 }
1528 else
1529 {
1530 ES8311_headset_mic_enable(ES8311_DEVICE_OFF);
1531 }
1532 }
1533
1534 if (is_speaker_on())
1535 ES8311_speaker_enable(ES8311_DEVICE_ON);
1536 if (is_headphone_on())
1537 ES8311_headphone_enable(ES8311_DEVICE_ON);
1538 if (is_main_mic_on())
1539 ES8311_main_mic_enable(ES8311_DEVICE_ON);
1540 if (is_headset_mic_on())
1541 ES8311_headset_mic_enable(ES8311_DEVICE_ON);
1542 break;
1543
1544 default:
1545 break;
1546 }
1547}
1548
1549
1550void codec_ES8311_set_headphone_gain(void)
1551{
1552#if 0
1553 // -6db
1554 es8311_update_bit(0x45, (1 << 12), (1 << 12));
1555
1556#else
1557
1558 es8311_write(0x45, 0x5000);
1559#endif
1560
1561 return;
1562}
1563
1564void codec_ES8311_set_headphone_mic_gain(void)
1565{
1566#if 0
1567 // +24db
1568 es8311_update_bit(0x1c, (0x7F << 8), (0x6F << 8));
1569 es8311_update_bit(0x1c, (0x7F << 0), (0x6F << 0));
1570
1571 // +24db: Boost will cause something like white noise in background, so just remove it.
1572 //es8311_update_bit(0x1E, (3 << 14), (2 << 14));
1573 //es8311_update_bit(0x1E, (3 << 12), (2 << 12));
1574#else
1575 es8311_write(0x1c, 0x6f6f);
1576#endif
1577 return;
1578}
1579
1580void codec_ES8311_mute_headphone(int mute)
1581{
1582 if(mute){
1583 es8311_update_bit(0x02, (1 << 15), (1 << 15));
1584 es8311_update_bit(0x02, (1 << 7), (1 << 7));
1585 }
1586 else{
1587 es8311_update_bit(0x02, (1 << 15), (0 << 15));
1588 es8311_update_bit(0x02, (1 << 7), (0 << 7));
1589 }
1590 return;
1591}
1592
1593void codec_ES8311_mute_speaker(int mute)
1594{
1595 if(mute){
1596 es8311_update_bit(0x03, (1 << 15), (1 << 15));
1597 es8311_update_bit(0x03, (1 << 7), (1 << 7));
1598 }
1599 else{
1600 es8311_update_bit(0x03, (1 << 15), (0 << 15));
1601 es8311_update_bit(0x03, (1 << 7), (0 << 7));
1602 }
1603 return;
1604}
1605
1606void codec_ES8311_set_speaker_mic_gain(void)
1607{
1608 // +0db
1609 es8311_update_bit(0x1c, (0x7F << 8), (0x2F << 8));
1610 es8311_update_bit(0x1c, (0x7F << 0), (0x2F << 0));
1611
1612 return;
1613}
1614
1615
1616void codec_es8311_enable_headphone_main_mic(void)
1617{
1618 if(!codec_es8311_is_connect()) {return;}
1619
1620 printk(KERN_INFO"codec_es8311_enable_headphone_main_mic\n");
1621
1622#ifdef RECONFIGURE_POWER_INCALL
1623 enable_8311_MClock();
1624#endif
1625 ES8311_device_select(ES8311_OUTPUT_DEVICE_HEADPHONE, ES8311_DEVICE_ON);
1626 ES8311_device_select(ES8311_INPUT_DEVICE_MAIN_MIC, ES8311_DEVICE_ON);
1627 codec_ES8311_set_headphone_gain();
1628 return;
1629}
1630
1631void codec_ES8311_enable_headphone(void)
1632{
1633 if(disableES8311HsMic){
1634 return codec_es8311_enable_headphone_main_mic();
1635 }
1636
1637 if(!codec_es8311_is_connect()) {return;}
1638
1639 printk(KERN_INFO"codec_ES8311_enable_headphone\n");
1640#ifdef RECONFIGURE_POWER_INCALL
1641 enable_8311_MClock();
1642#endif
1643 ES8311_device_select(ES8311_OUTPUT_DEVICE_HEADPHONE, ES8311_DEVICE_ON);
1644 ES8311_device_select(ES8311_INPUT_DEVICE_HEADSET_MIC, ES8311_DEVICE_ON);
1645
1646 codec_ES8311_set_headphone_gain();
1647 codec_ES8311_set_headphone_mic_gain();
1648 return;
1649}
1650
1651void codec_ES8311_enable_headphone_only(void)
1652{
1653 if(!codec_es8311_is_connect()) {return;}
1654
1655 printk(KERN_INFO"codec_ES8311_enable_headphone_only\n");
1656#ifdef RECONFIGURE_POWER_INCALL
1657 enable_8311_MClock();
1658#endif
1659 ES8311_device_select(ES8311_OUTPUT_DEVICE_HEADPHONE, ES8311_DEVICE_ON);
1660 return;
1661}
1662
1663void codec_ES8311_enable_main_mic_only(void)
1664{
1665 if(!codec_es8311_is_connect()) {return;}
1666
1667 printk(KERN_INFO"codec_ES8311_enable_main_mic_only\n");
1668#ifdef RECONFIGURE_POWER_INCALL
1669 enable_8311_MClock();
1670#endif
1671 ES8311_device_select(ES8311_INPUT_DEVICE_HEADSET_MIC, ES8311_DEVICE_ON);
1672 return;
1673}
1674
1675void codec_ES8311_enable_speaker(void)
1676{
1677 if(!codec_es8311_is_connect()) {return;}
1678
1679 printk(KERN_INFO"codec_ES8311_enable_speaker\n");
1680#ifdef RECONFIGURE_POWER_INCALL
1681 enable_8311_MClock();
1682#endif
1683 ES8311_device_select(ES8311_OUTPUT_DEVICE_SPEAKER, ES8311_DEVICE_ON);
1684 ES8311_device_select(ES8311_INPUT_DEVICE_MAIN_MIC, ES8311_DEVICE_ON);
1685
1686 codec_ES8311_set_speaker_mic_gain();
1687 return;
1688}
1689
1690void codec_ES8311_enable_speaker_only(void)
1691{
1692 if(!codec_es8311_is_connect()) {return;}
1693
1694 printk(KERN_INFO"codec_ES8311_enable_speaker_only\n");
1695 ES8311_device_select(ES8311_OUTPUT_DEVICE_SPEAKER, ES8311_DEVICE_ON);
1696 return;
1697}
1698
1699void codec_ES8311_disable_path(void)
1700{
1701 if(!codec_es8311_is_connect()) {return;}
1702
1703 printk(KERN_INFO"codec_ES8311_disable_path\n");
1704
1705 if(is_speaker_on()){
1706 ES8311_device_select(ES8311_OUTPUT_DEVICE_SPEAKER, ES8311_DEVICE_OFF);
1707 }
1708 if(is_headphone_on()){
1709 ES8311_device_select(ES8311_OUTPUT_DEVICE_HEADPHONE, ES8311_DEVICE_OFF);
1710 }
1711 if(is_main_mic_on()){
1712 ES8311_device_select(ES8311_INPUT_DEVICE_MAIN_MIC, ES8311_DEVICE_OFF);
1713 }
1714 if(is_headset_mic_on()){
1715 ES8311_device_select(ES8311_INPUT_DEVICE_HEADSET_MIC, ES8311_DEVICE_OFF);
1716 }
1717
1718#ifdef RECONFIGURE_POWER_INCALL
1719 disable_8311_MClock();
1720#endif
1721 return;
1722}
1723
1724//Kestrel/Falcon/NezhaC
1725void disable_8311_MClock(void)
1726{
1727 printk(KERN_INFO"disable_8311_MClock, g_8311_mclk_type=%d\n", g_8311_mclk_type);
1728
1729#if 0 //yjg
1730 if(g_8311_mclk_type){
1731 /*GPIO-20 function 0 (default), GPIO-20*/
1732 /* *(volatile unsigned long *)(SSP1_I2S_CLOCK_REG_ADDR) = 0x7820130B; *//*8k, sysclk_en = 0*/
1733 /* *(volatile unsigned long *)(MFPRX_GPIO_20) = 0xB0C0; */
1734 iounmap(i2s_clk_reg);
1735 release_mem_region(SSP1_I2S_CLOCK_REG_ADDR, 4);
1736 }
1737#endif
1738 return;
1739}
1740
1741extern char * get_MCLK_start_addr(void);
1742#ifdef CONFIG_CPU_ASR1901
1743extern int enable_pmu_audio_clk(void);
1744#endif
1745//Kestrel/Flacon/NezhaC
1746void enable_8311_MClock(void)
1747{
1748#ifdef ES8311_DEBUG_CLOSE
1749 int reg_value = 0;
1750
1751 printk(KERN_INFO"enable_8311_MClock, g_8311_mclk_type=%d, Audio_Codec_Fsync_Rate=%d\n", g_8311_mclk_type, Audio_Codec_Fsync_Rate);
1752 printk("enable_8311_MClock, g_8311_mclk_type=%d, Audio_Codec_Fsync_Rate=%d\n", g_8311_mclk_type, Audio_Codec_Fsync_Rate);
1753 if (cpu_is_asr1803()) {
1754 printk(KERN_INFO"%s, platform is Falcon.\n", __FUNCTION__);
1755 } else if (cpu_is_asr1806()) {
1756 printk(KERN_INFO"%s, platform is Falcon-T.\n", __FUNCTION__);
1757 } else if (cpu_is_asr1901() || cpu_is_asr1906()) {
1758 printk(KERN_INFO"%s, platform is Kestrel.\n", __FUNCTION__);
1759 } else if (cpu_is_asr1903()) {
1760 printk(KERN_INFO"%s, platform is Lapwing.\n", __FUNCTION__);
1761 } else {
1762 printk(KERN_INFO"%s, platform is Nezhac or Nezha3.\n", __FUNCTION__);
1763 }
1764#endif
1765
1766 if (cpu_is_asr1901() || cpu_is_asr1906()) {
1767 printk(KERN_INFO"%s, platform is kestrel.\n", __FUNCTION__);
1768#ifdef Kestrel_Z2
1769 __raw_writel(0x1043, VCXO_OUT_MFPR_reg);
1770 __raw_writel(0x3, PM_MN_CLK_reg);
1771
1772 if(0 == Audio_Codec_Fsync_Rate){
1773 /* config 2.048MHz MCLK for 8KHz Fsync of PCM */
1774 __raw_writel(0x00980001, GPCR_reg);
1775 } else {
1776 /* config 4.096MHz MCLK for 16KHz Fsync of PCM */
1777 __raw_writel(0x004c0001, GPCR_reg);
1778 }
1779
1780 printk(KERN_INFO"%s, VCXO_OUT_MFPR_reg is 0x%0x, PM_MN_CLK_reg is 0x%0x, GPCR_reg is 0x%0x.\n",
1781 __FUNCTION__, *(unsigned int *)VCXO_OUT_MFPR_reg, *(unsigned int *)PM_MN_CLK_reg, *(unsigned int *)GPCR_reg);
1782
1783#else
1784 MCLK_CLK_CTRL_reg = get_MCLK_start_addr();
1785 if (NULL == MCLK_CLK_CTRL_reg) {
1786 printk(KERN_INFO"%s, MCLK_CLK_CTRL_reg is NULL.\n", __FUNCTION__, MCLK_CLK_CTRL_reg);
1787 return;
1788 }
1789
1790 MCLK_MN_DIV_reg = (char *)MCLK_CLK_CTRL_reg + 4;
1791
1792 __raw_writel(0x3, MCLK_CLK_CTRL_reg);
1793
1794 if(0 == Audio_Codec_Fsync_Rate){
1795 /* config 2.048MHz MCLK for 8KHz Fsync of PCM */
1796 printk("--->%s%d\n", __FUNCTION__, __LINE__);
1797 __raw_writel(0x004b0004, MCLK_MN_DIV_reg);
1798 } else if (1 == Audio_Codec_Fsync_Rate){
1799 /* config 4.096MHz MCLK for 16KHz Fsync of PCM */
1800 __raw_writel(0x004b0008, MCLK_MN_DIV_reg);
1801 } else if (3 == Audio_Codec_Fsync_Rate) {
1802 /* config 12.288MHz MCLK for 48KHz Fsync of PCM */
1803 //__raw_writel(0x004b0018, MCLK_MN_DIV_reg);//1.MCLK 12.288MHz direct connection
1804
1805 __raw_writel(0x000a0001, MCLK_MN_DIV_reg);//MCLK 3.84MHz for PLL and for HP detection
1806
1807 es8311_write(0x73, 0x1002);
1808 es8311_write(0x80, 0x4000);//2.MCLK 3.84MHz for PLL
1809 //es8311_write(0x80, 0x5000);//3.BCLK 3.84MHz for PLL
1810 es8311_write(0x81, 0x3F02);
1811 es8311_write(0x82, 0x3000);
1812 } else {
1813 printk(KERN_INFO"%s, please check Audio_Codec_Fsync_Rate = %d.\n",__FUNCTION__, Audio_Codec_Fsync_Rate);
1814 }
1815
1816 printk(KERN_INFO"%s, Audio_Codec_Fsync_Rate = %d.\n",__FUNCTION__, Audio_Codec_Fsync_Rate);
1817 printk(KERN_INFO"%s, MCLK_CLK_CTRL_reg is 0x%0x, MCLK_MN_DIV_reg is 0x%0x.\n",
1818 __FUNCTION__, *(unsigned int *)MCLK_CLK_CTRL_reg, *(unsigned int *)MCLK_MN_DIV_reg);
1819#endif
1820 } else {
1821 printk(KERN_INFO"%s, platform is NezhaC, Falcon, .etc.\n", __FUNCTION__);
1822 printk("--->%s%d\n", __FUNCTION__, __LINE__);
1823 struct clk * mclk = devm_clk_get(&g_es8311_client->dev, "i2s_sys_clk");
1824 if(IS_ERR(mclk)){
1825 printk(KERN_INFO"mclk get failed\n");
1826 return;
1827 }
1828
1829 int ret = clk_prepare_enable(mclk);
1830 if(ret){
1831 printk(KERN_INFO"mclk prepare enable failed");
1832 return;
1833 }
1834
1835 if(g_8311_mclk_type){
1836printk("--->%s%d\n", __FUNCTION__, __LINE__);
1837 if(0 == Audio_Codec_Fsync_Rate){
1838 /*i2s_sysclk = 2M for 8k*/
1839
1840#ifdef ES8311_DEBUG_CLOSE
1841 reg_value = ioread32(SSP1_I2S_CLOCK_reg);
1842 //reg_value = *(volatile int*)(i2s_clk_reg);
1843 printk(KERN_INFO"read: reg_value=0x%x\n", reg_value);
1844 //printk(KERN_INFO"read: *register_address = 0x%x, reg_value=0x%x\n",
1845 //*(unsigned int *)i2s_clk_reg, reg_value);
1846#endif
1847 printk("--->%s%d\n", __FUNCTION__, __LINE__);
1848 clk_set_rate(mclk, 2048000);
1849 // clk_set_rate(mclk, 10000000);
1850 int rate = clk_get_rate(mclk);
1851 printk(KERN_INFO"mclk rate is %d", rate);
1852 printk("--->%s%d mclk rate is %d\n", __FUNCTION__, __LINE__, rate);
1853 /* write value to register */
1854 //*(volatile unsigned int *)i2s_clk_reg = 0xF820130B;
1855
1856#ifdef ES8311_DEBUG_CLOSE
1857 /* read value from register */
1858 printk(KERN_INFO"NB, write:0xF820130B(Nezhac, Nezha3),0xE0C472D8(Falcon),*register_address = 0x%x\n", *(unsigned int *)SSP1_I2S_CLOCK_reg);
1859#endif
1860 }
1861 else{
1862 /*i2s_sysclk = 4M for 16k*/
1863
1864#ifdef ES8311_DEBUG_CLOSE
1865 reg_value = ioread32(SSP1_I2S_CLOCK_reg);
1866 printk(KERN_INFO"read: reg_value=0x%x\n", reg_value);
1867 //printk(KERN_INFO"read: *register_address = %x\n", *(unsigned int *)i2s_clk_reg);
1868
1869 //reg_value = *(volatile int*)(i2s_clk_reg);
1870 //printk(KERN_INFO"read: *register_address = 0x%x, reg_value=0x%x\n",
1871 //*(unsigned int *)i2s_clk_reg, reg_value);
1872#endif
1873 clk_set_rate(mclk, 4096000);
1874 int rate = clk_get_rate(mclk);
1875 printk(KERN_INFO"mclk rate is %d", rate);
1876#ifdef ES8311_DEBUG_CLOSE
1877 /* write value to register */
1878 //*(volatile unsigned int *)i2s_clk_reg = 0xF840130B;
1879
1880 /* read value from register */
1881 printk(KERN_INFO"WB, write: 0xF840130B(Nezhac, Nezha3),0xE18872D8(Falcon), *register_address = %x\n", *(unsigned int *)SSP1_I2S_CLOCK_reg);
1882#endif
1883 }
1884 }
1885 }
1886 return;
1887}
1888EXPORT_SYMBOL_GPL(enable_8311_MClock);
1889
1890void codec_ES8311_power_on(void)
1891{
1892 printk(KERN_INFO"codec_ES8311_power_on\n");
1893
1894 enable_8311_MClock();
1895 ES8311_set_dai_fmt(1);
1896 es8311_set_sysclk(1);
1897 ES8311_set_sys_power(1);
1898}
1899
1900void codec_es8311_power_off(void)
1901{
1902 printk(KERN_INFO"codec_es8311_power_off\n");
1903
1904 ES8311_set_dai_fmt(0);
1905 es8311_set_sysclk(0);
1906 ES8311_set_sys_power(0);
1907 disable_8311_MClock();
1908}
1909
1910void codec_es8311_enable_headset_detect(void)
1911{
1912 if(!codec_es8311_is_connect()) {return;}
1913
1914 printk(KERN_INFO"codec_es8311_enable_headset_detect\n");
1915
1916 g_8311_headset_detection_enabled = 1;
1917 g_8311_headset_plugged = 0;
1918
1919 ES8311_device_enable(ES8311_INPUT_DEVICE_HEADSET_DETECT, 1);
1920
1921 return;
1922}
1923
1924void codec_es8311_disable_headset_detect(void)
1925{
1926 if(!codec_es8311_is_connect()) {return;}
1927
1928 printk(KERN_INFO"codec_es8311_disable_headset_detect\n");
1929
1930 ES8311_device_enable(ES8311_INPUT_DEVICE_HEADSET_DETECT, 0);
1931
1932 g_8311_headset_detection_enabled = 0;
1933 return;
1934}
1935
1936/* HS Detection */
1937static struct mfd_cell headset_devs_es8311[] = {
1938 {
1939 .name = "es8311-headset",
1940 .id = -1,
1941 },
1942};
1943
1944static void es8311_headset_detection_init(struct i2c_client *client)
1945{
1946 int ret = 0;
1947
1948 headset_devs_es8311[0].platform_data = client;
1949 headset_devs_es8311[0].pdata_size = sizeof(struct i2c_client);
1950
1951 ret = mfd_add_devices(&client->dev, 0, &headset_devs_es8311[0],
1952 ARRAY_SIZE(headset_devs_es8311), NULL,
1953 0,
1954 NULL);
1955 if (ret) {
1956 printk(KERN_INFO"Failed to add headset subdev\n");
1957 return;
1958 }
1959
1960 return;
1961}
1962
1963
1964void codec_es8311_switch_headset(char on)
1965{
1966 if(on == 1)
1967 {
1968 //codec_ES8311_disable_path();
1969 //msleep(10);
1970 //ACMSetMSAVoicePath(ATC_HEADSET);
1971
1972 codec_ES8311_enable_headphone();
1973 }
1974 else
1975 {
1976 //codec_ES8311_disable_path();
1977 //msleep(10);
1978
1979 //ACMSetMSAVoicePath(ATC_HANDSET);
1980 codec_ES8311_enable_speaker();
1981 }
1982
1983 return;
1984}
1985
1986/* Headset function and report to userspace for ACM */
1987
1988void es8311_get_headset_status(void)
1989{
1990 unsigned short value = 0;
1991 int status = -1;
1992
1993 if(!codec_es8311_is_connect()) {return;}
1994
1995 status = es8311_read(0xBF, &value);
1996 if(0 != status)
1997 {
1998 printk(KERN_INFO"%s: Read register [0xBF] error = 0x%x\n", __FUNCTION__, status);
1999 return;
2000 }
2001
2002 if((value & 0x3000) == 0)
2003 {/* headset plug in: bit 12 & 13 is 1 */
2004 g_8311_headset_plugged = 1;
2005
2006 /* Enable MICBIAS1 Short Current Detector, Threshold:1500uA */
2007 es8311_update_bit(0x93, (7 << 9), (5 << 9));
2008
2009 /* wait mic bias stable*/
2010 mdelay(100);
2011
2012 value = 0;
2013 status = es8311_read(0xBE, &value);
2014 if(0 != status)
2015 {
2016 printk(KERN_INFO"%s: Read register [0xBE] error = 0x%x\n", __FUNCTION__, status);
2017 return;
2018 }
2019
2020 /* MICBIAS1 Over Current status */
2021 if((1 == g_8311_headset_plugged) && ((value & (1 << 3)) == 0))
2022 {
2023 /* Headset with mic */
2024 g_8311_headset_mic = 1;
2025 printk(KERN_INFO"Headset(with mic) plugin!\n");
2026 }
2027 else if((1 == g_8311_headset_plugged) && ((value & (1 << 3)) != 0))
2028 {
2029 /* Headset without mic */
2030 g_8311_headset_mic = 0;
2031 printk(KERN_INFO"Headset(without mic) plugin!\n");
2032 }
2033 }
2034 else if((value & 0x3000) == 0x3000)
2035 {/* headset plug out: bit 12 & 13 is 0 */
2036 g_8311_headset_plugged = 0;
2037 g_8311_headset_mic = 0;
2038
2039 /* Disable MICBIAS1 Short Current Detector */
2040 es8311_update_bit(0x93, (7 << 9), (0 << 9));
2041
2042 printk(KERN_INFO"Headset plugout!\n");
2043 }
2044
2045 return;
2046}
2047
2048
2049int es8311_get_headset_mic_status(void)
2050{
2051 return g_8311_headset_mic;
2052}
2053EXPORT_SYMBOL_GPL(es8311_get_headset_mic_status);
2054
2055int es8311_get_headset_plugged_status(void)
2056{
2057 return g_8311_headset_plugged;
2058}
2059EXPORT_SYMBOL_GPL(es8311_get_headset_plugged_status);
2060
2061void codec_es8311_clear_headset_status(void)
2062{
2063 if(!codec_es8311_is_connect()) {return;}
2064
2065 printk(KERN_INFO"codec_es8311_clear_headset_status\n");
2066
2067 es8311_write(0xBF, 0);
2068 return;
2069}
2070
2071void codec_es8311_use_bitclk(void)
2072{
2073 printk(KERN_INFO"codec_es8311_use_bitclk\n");
2074 g_8311_mclk_type = 0;
2075 return;
2076}
2077
2078void codec_es8311_use_bitclk_with_mclk_on(void)
2079{
2080 printk(KERN_INFO"codec_es8311_use_bitclk_with_mclk_on\n");
2081 g_8311_mclk_type = 2;
2082 return;
2083}
2084
2085void codec_es8311_set_mainmic_singlemode(void)
2086{
2087 printk(KERN_INFO"codec_es8311_set_mainmic_singlemode\n");
2088 g_8311_mainmic_type = 1;
2089 return;
2090}
2091
2092void es8311_Enable_Headsetdetection(void)
2093{
2094 /* Init headset detection for es8311 */
2095 if(codec_es8311_is_connect() && (g_8311_headset_detection_enabled == 0))
2096 {
2097 codec_es8311_enable_headset_detect();
2098 }
2099}
2100EXPORT_SYMBOL_GPL(es8311_Enable_Headsetdetection);
2101
2102void es8311_Disable_Headsetdetection(void)
2103{
2104 /* Init headset detection for es8311 */
2105 if(codec_es8311_is_connect() && (g_8311_headset_detection_enabled == 1))
2106 {
2107 codec_es8311_disable_headset_detect();
2108 }
2109}
2110EXPORT_SYMBOL_GPL(es8311_Disable_Headsetdetection);
2111
2112void codec_es8311_dump(void)
2113{
2114 es8311_reg_dump();
2115}
2116
2117/* debug fs for es8311 register interface of read and write. */
2118static int reg_es8311 = 0xffff;
2119struct dentry *es8311_dump_reg = NULL;
2120
2121static ssize_t es8311_dump_read(struct file *file, char __user *user_buf,
2122 size_t count, loff_t *ppos)
2123{
2124 unsigned short reg_val = 0;
2125 unsigned short out_val = 0;
2126 int i;
2127 int len = 0;
2128 char str[100] = {0};
2129
2130 if (reg_es8311 == 0xffff) {
2131 len = snprintf(str, sizeof(str) - 1, "%s\n",
2132 "es8311: register dump:");
2133 for (i = 0; i < es8311_reg_NUM; i++) {
2134 if (es8311_readable_register(i)) {
2135
2136 if (0x3D == i)
2137 {
2138 reg_val = es8311_index_read(i, &out_val);
2139 }
2140 else
2141 {
2142 reg_val = es8311_read(i, &out_val);
2143 }
2144 pr_info("%s: [0x%02x]=0x%02x\n", __FUNCTION__, i, out_val);
2145 }
2146 }
2147 } else {
2148
2149 /*
21500xFF:get MIC Gain and Speaker Gain
2151echo 0xFF 4 > /sys/kernel/debug/es8311_reg
2152cat /sys/kernel/debug/es8311_reg
2153 */
2154 if (0xFF == reg_es8311)
2155 {
2156 /* adjust the gain. */
2157 }
2158 else if (0x3D == reg_es8311)
2159 {
2160 reg_val = es8311_index_read(reg_es8311, &out_val);
2161 len = snprintf(str, sizeof(str), "reg_es8311=0x%02x, val=0x%04x\n",
2162 reg_es8311, out_val);
2163 printk(KERN_INFO"%s:%s\n", __FUNCTION__, str);
2164 }
2165 else
2166 {
2167 reg_val = es8311_read(reg_es8311, &out_val);
2168 len = snprintf(str, sizeof(str), "reg_es8311=0x%02x, val=0x%04x\n",
2169 reg_es8311, out_val);
2170 printk(KERN_INFO"%s:%s\n", __FUNCTION__, str);
2171
2172 }
2173 }
2174
2175 return 0;
2176}
2177
2178/*
2179 read example:
2180 echo 0x90 > /sys/kernel/debug/es8311_reg
2181 cat /sys/kernel/debug/es8311_reg
2182 read all register:
2183 echo + > /sys/kernel/debug/es8311_reg
2184 cat /sys/kernel/debug/es8311_reg
2185 write example: echo 0x90 0x10 > /sys/kernel/debug/es8311_reg
2186
2187 read register example:
2188 echo 0x3F > /sys/kernel/debug/es8311_reg
2189 cat /sys/kernel/debug/es8311_reg
2190
2191 read all registers example:
2192 echo + > /sys/kernel/debug/es8311_reg
2193 cat /sys/kernel/debug/es8311_reg
2194
2195 config Gain example:
2196 echo 0xFF 0x00 > /sys/kernel/debug/es8311_reg
2197 echo 0xFF 0x01 > /sys/kernel/debug/es8311_reg
2198 echo 0xFF 0x02 > /sys/kernel/debug/es8311_reg
2199 echo 0xFF 0x03 > /sys/kernel/debug/es8311_reg
2200 echo 0xFF 0x04 > /sys/kernel/debug/es8311_reg
2201 echo 0xFF 0x05 > /sys/kernel/debug/es8311_reg
2202 echo 0xFF 0x06 > /sys/kernel/debug/es8311_reg
2203 echo 0xFF 0x07 > /sys/kernel/debug/es8311_reg
2204 cat /sys/kernel/debug/es8311_reg
2205
2206 write the register example:
2207 echo 0x2C 0x01 > /sys/kernel/debug/es8311_reg
2208 cat /sys/kernel/debug/es8311_reg
2209 */
2210static ssize_t es8311_dump_write(struct file *file,
2211 const char __user *user_buf,
2212 size_t count, loff_t *ppos)
2213{
2214 int reg_val;
2215 //struct pm80x_chip *chip = file->private_data;
2216 int i = 0;
2217 int ret;
2218
2219 char messages[20];
2220 memset(messages, '\0', 20);
2221
2222 if (copy_from_user(messages, user_buf, count))
2223 return -EFAULT;
2224
2225 if ('+' == messages[0]) {
2226 /* enable to get all the reg value */
2227 reg_es8311 = 0xffff;
2228 pr_info("%s: read all reg enabled!\n", __FUNCTION__);
2229 } else {
2230 if (messages[1] != 'x') {
2231 pr_err("Right format: 0x[addr]\n");
2232 return -EINVAL;
2233 }
2234
2235 if (strlen(messages) > 5) {
2236 while (messages[i] != ' ')
2237 i++;
2238 messages[i] = '\0';
2239 if (kstrtouint(messages, 16, &reg_es8311) < 0)
2240 return -EINVAL;
2241 i++;
2242 if (kstrtouint(messages + i, 16, &reg_val) < 0)
2243 return -EINVAL;
2244
2245 /*
2246 0xFF:set MIC Gain and Speaker Gain
2247 value(0x00~0x07)
2248 echo 0xFF value > /sys/kernel/debug/es8311_reg
2249 cat /sys/kernel/debug/es8311_reg
2250 */
2251 if (0xFF == reg_es8311)
2252 {
2253 /* adjust the gain within 0~10 */
2254 extern void es8311_adjust_gain(int gain);
2255 es8311_adjust_gain(reg_val);
2256 }
2257 else if (0x3D == reg_es8311)
2258 {
2259 /* config the registers */
2260 ret = es8311_index_write(reg_es8311, reg_val & 0xffff);
2261 if (ret < 0) {
2262 pr_err("write reg error!\n");
2263 return -EINVAL;
2264 }
2265
2266 printk(KERN_INFO"%s/L%d: addr=0x%02x, val=0x%04x.\n", __FUNCTION__, __LINE__, reg_es8311, reg_val);
2267 }
2268 else
2269 {
2270 /* config the registers */
2271 ret = es8311_write(reg_es8311, reg_val & 0xffff);
2272 if (ret < 0) {
2273 pr_err("write reg error!\n");
2274 return -EINVAL;
2275 }
2276
2277 printk(KERN_INFO"%s/L%d: addr=0x%02x, val=0x%04x.\n", __FUNCTION__, __LINE__, reg_es8311, reg_val);
2278
2279 }
2280
2281 } else {
2282 /* point out the register address for read. */
2283 if (kstrtouint(messages, 16, &reg_es8311) < 0)
2284 return -EINVAL;
2285 }
2286 }
2287
2288 return count;
2289}
2290
2291static const struct file_operations es8311_dump_ops = {
2292 .open = simple_open,
2293 .read = es8311_dump_read,
2294 .write = es8311_dump_write,
2295};
2296
2297static inline int es8311_dump_debugfs_init(struct pm80x_chip *chip)
2298{
2299
2300 es8311_dump_reg = debugfs_create_file("es8311_reg", S_IRUGO | S_IFREG,
2301 NULL, NULL, &es8311_dump_ops);
2302
2303 if (es8311_dump_reg == NULL) {
2304 pr_err("create es8311 debugfs error!\n");
2305 return -ENOENT;
2306 } else if (es8311_dump_reg == ERR_PTR(-ENODEV)) {
2307 pr_err("CONFIG_DEBUG_FS is not enabled!\n");
2308 return -ENOENT;
2309 }
2310
2311 return 0;
2312}
2313
2314static void es8311_dump_debugfs_remove(struct pm80x_chip *chip)
2315{
2316 if (NULL != es8311_dump_reg){
2317 debugfs_remove_recursive(es8311_dump_reg);
2318 }
2319
2320 return;
2321}
2322
2323
2324
2325/* debug fs for es8311 audio control of Earphone, speaker or HS... */
2326
2327struct dentry *es8311_audio_control = NULL;
2328
2329static ssize_t es8311_audio_read(struct file *file, char __user *user_buf,
2330 size_t count, loff_t *ppos)
2331{
2332
2333#ifdef ES8311_DEBUG
2334 printk(KERN_INFO"%s/L%d.\n", __FUNCTION__, __LINE__);
2335#endif
2336 return 0;
2337
2338}
2339
2340/*
23411:enable earphone, enable MIC1
23422:disable earphone, enable MIC1
2343
23443:enable speaker, enable MIC1
23454:disable speaker, enable MIC1
2346
23475:enable Headphone, enable HSMIC
23486:disable Headphone, enable HSMIC
2349control command:
2350enable earphone and MIC1: echo 1 > /sys/kernel/debug/es8311_audio
2351disable earphone and MIC1: echo 2 > /sys/kernel/debug/es8311_audio
2352
2353enable speaker and MIC1: echo 3 > /sys/kernel/debug/es8311_audio
2354disable speaker and MIC1: echo 4 > /sys/kernel/debug/es8311_audio
2355
2356enable Headphone and HSMIC echo 5 > /sys/kernel/debug/es8311_audio
2357disable Headphone and HSMIC echo 6 > /sys/kernel/debug/es8311_audio
2358 */
2359static char msg[10];
2360
2361static ssize_t es8311_audio_write(struct file *file,
2362 const char __user *user_buf,
2363 size_t count, loff_t *ppos)
2364{
2365 int ret = 0;
2366 size_t tmp_count = 0;
2367
2368 printk(KERN_INFO"%s/L%d.\n", __FUNCTION__, __LINE__);
2369
2370 memset(msg, 0x00, sizeof(msg));
2371 tmp_count = count;
2372
2373 if (tmp_count >= sizeof(msg)){
2374 tmp_count = sizeof(msg) - 1;
2375 }
2376
2377 /* copy the content from user space to kernel space */
2378 ret = copy_from_user(msg, user_buf, tmp_count);
2379 if (ret){
2380 printk(KERN_ALERT"copy from user fail \n");
2381 return -EFAULT;
2382 }
2383
2384 switch (msg[0]){
2385 case '1':/* input command# echo 1 > /sys/kernel/debug/es8311_audio */
2386 printk(KERN_INFO "input %c. \n", msg[0]);
2387 es8311_check_HS_mic();
2388 break;
2389
2390 case '2':/* input command# echo 2 > /sys/kernel/debug/es8311_audio */
2391 printk(KERN_INFO "input %c. \n", msg[0]);
2392 enable_8311_MClock();
2393 es8311_speaker_off();
2394 es8311_main_mic_off();
2395 break;
2396
2397 case '3':/* input command# echo 3 > /sys/kernel/debug/es8311_audio */
2398 printk(KERN_INFO "input %c. \n", msg[0]);
2399 enable_8311_MClock();
2400 es8311_headphone_on();
2401 es8311_headset_mic_on();
2402 break;
2403
2404 case '4':/* input command# echo 4 > /sys/kernel/debug/es8311_audio */
2405 printk(KERN_INFO "input %c. \n", msg[0]);
2406 codec_es8311_enable_headset_detect();
2407 break;
2408
2409 case '5':/* input command# echo 5 > /sys/kernel/debug/es8311_audio */
2410 printk(KERN_INFO "input %c. \n", msg[0]);
2411 enable_8311_MClock();
2412 es8311_headphone_off();
2413 es8311_headset_mic_off();
2414 break;
2415
2416 case '6':/* input command# echo 6 > /sys/kernel/debug/es8311_audio */
2417 printk(KERN_INFO "input %c. \n", msg[0]);
2418 es8311_mute_mic(1);
2419 break;
2420
2421 case '7':/* input command# echo 7 > /sys/kernel/debug/es8311_audio */
2422 enable_8311_MClock();
2423 es8311_speaker_on();
2424 es8311_main_mic_on();
2425 break;
2426
2427 case '8':/* input command# echo 8 > /sys/kernel/debug/es8311_audio */
2428 enable_8311_MClock();
2429 es8311_speaker_off();
2430 es8311_main_mic_off();
2431 break;
2432
2433 case '9':/* input command# echo 9 > /sys/kernel/debug/es8311_audio */
2434 enable_8311_MClock();
2435 codec_es8311_enable_headphone_main_mic();
2436 break;
2437
2438 default:/* input command# */
2439 printk(KERN_INFO "input invalid. \n");
2440 break;
2441 }
2442
2443 return tmp_count;
2444}
2445
2446static const struct file_operations es8311_audio_ops = {
2447 .open = simple_open,
2448 .read = es8311_audio_read,
2449 .write = es8311_audio_write,
2450};
2451
2452static inline int es8311_audio_debugfs_init(struct pm80x_chip *chip)
2453{
2454
2455 es8311_audio_control = debugfs_create_file("es8311_audio", S_IRUGO | S_IFREG,
2456 NULL, NULL, &es8311_audio_ops);
2457
2458 if (es8311_audio_control == NULL) {
2459 pr_err("create es8311 debugfs error!\n");
2460 return -ENOENT;
2461 } else if (es8311_audio_control == ERR_PTR(-ENODEV)) {
2462 pr_err("CONFIG_DEBUG_FS is not enabled!\n");
2463 return -ENOENT;
2464 }
2465
2466 return 0;
2467}
2468
2469static void es8311_audio_debugfs_remove(struct pm80x_chip *chip)
2470{
2471 if (NULL != es8311_audio_control){
2472 debugfs_remove_recursive(es8311_audio_control);
2473 }
2474
2475 return;
2476};
2477
2478/* register codec to ALSA. */
2479static const struct snd_kcontrol_new es8311_snd_controls[] = {
2480
2481 SOC_SINGLE("Reset Register", ES8311_RESET_REG00, 0, 0xff, 0), //0x00
2482
2483 SOC_SINGLE("Clock Manager 1", ES8311_CLK_MANAGER_REG01, 0, 0xff, 0), //0x01
2484 SOC_SINGLE("Clock Manager 2", ES8311_CLK_MANAGER_REG02, 0, 0xff, 0), //0x02
2485 SOC_SINGLE("Clock Manager 3", ES8311_CLK_MANAGER_REG03, 0, 0xff, 0), //0x03
2486 SOC_SINGLE("Clock Manager 4", ES8311_CLK_MANAGER_REG04, 0, 0xff, 0), //0x04
2487 SOC_SINGLE("Clock Manager 5", ES8311_CLK_MANAGER_REG05, 0, 0xff, 0), //0x05
2488 SOC_SINGLE("Clock Manager 6", ES8311_CLK_MANAGER_REG06, 0, 0xff, 0), //0x06
2489 SOC_SINGLE("Clock Manager 7", ES8311_CLK_MANAGER_REG07, 0, 0xff, 0), //0x07
2490 SOC_SINGLE("Clock Manager 8", ES8311_CLK_MANAGER_REG08, 0, 0xff, 0), //0x08
2491
2492 SOC_SINGLE("ADC SDP Register", ES8311_SDPIN_REG09, 0, 0xff, 0), //0x09
2493 SOC_SINGLE("DAC SDP Register", ES8311_SDPOUT_REG0A, 0, 0xff, 0), //0x0A
2494
2495 SOC_SINGLE("System Manager 1", ES8311_SYSTEM_REG0B, 0, 0xff, 0), //0x0B
2496 SOC_SINGLE("System Manager 2", ES8311_SYSTEM_REG0C, 0, 0xff, 0), //0x0C
2497 SOC_SINGLE("System Manager 3", ES8311_SYSTEM_REG0D, 0, 0xff, 0), //0x0D
2498 SOC_SINGLE("System Manager 4", ES8311_SYSTEM_REG0E, 0, 0xff, 0), //0x0E
2499 SOC_SINGLE("System Manager 5", ES8311_SYSTEM_REG0F, 0, 0xff, 0), //0x0F
2500 SOC_SINGLE("System Manager 6", ES8311_SYSTEM_REG10, 0, 0xff, 0), //0x10
2501 SOC_SINGLE("System Manager 7", ES8311_SYSTEM_REG11, 0, 0xff, 0), //0x11
2502 SOC_SINGLE("System Manager 8", ES8311_SYSTEM_REG12, 0, 0xff, 0), //0x12
2503 SOC_SINGLE("System Manager 9", ES8311_SYSTEM_REG13, 0, 0xff, 0), //0x13
2504 SOC_SINGLE("System Manager 10", ES8311_SYSTEM_REG14, 0, 0xff, 0), //0x14
2505
2506 SOC_SINGLE("ADC RAMP Register", ES8311_ADC_REG15, 0, 0xff, 0), //0x15
2507 SOC_SINGLE("ADC Register", ES8311_ADC_REG16, 0, 0xff, 0), //0x16
2508 SOC_SINGLE("ADC Volume Register", ES8311_ADC_REG17, 0, 0xff, 0), //0x17
2509 SOC_SINGLE("ADC ALC Register1", ES8311_ADC_REG18, 0, 0xff, 0), //0x18
2510 SOC_SINGLE("ADC ALC Register2", ES8311_ADC_REG19, 0, 0xff, 0), //0x19
2511 SOC_SINGLE("ADC Mute Register1", ES8311_ADC_REG1A, 0, 0xff, 0), //0x1A
2512 SOC_SINGLE("ADC Mute Register2", ES8311_ADC_REG1B, 0, 0xff, 0), //0x1B
2513 SOC_SINGLE("ADC EQ Register1", ES8311_ADC_REG1C, 0, 0xff, 0), //0x1C
2514 SOC_SINGLE("ADC EQ Register2", ES8311_ADC_REG1E, 0, 0xff, 0), //0x1E
2515
2516 SOC_SINGLE("DAC Mute Register", ES8311_DAC_REG31, 0, 0xff, 0), //0x31
2517 SOC_SINGLE("DAC Volume Register", ES8311_DAC_REG32, 0, 0xff, 0), //0x32
2518 SOC_SINGLE("DAC Offset Register", ES8311_DAC_REG33, 0, 0xff, 0), //0x33
2519 SOC_SINGLE("DAC DRC Register1", ES8311_DAC_REG34, 0, 0xff, 0), //0x34
2520 SOC_SINGLE("DAC DRC Register2", ES8311_DAC_REG35, 0, 0xff, 0), //0x35
2521 SOC_SINGLE("DAC RAMP Register", ES8311_DAC_REG37, 0, 0xff, 0), //0x37
2522
2523 SOC_SINGLE("GPIO AFSEL Register", ES8311_GPIO_REG44, 0, 0xff, 0), //0x44
2524 SOC_SINGLE("GPIO CTL Register", ES8311_GP_REG45, 0, 0xff, 0), //0x45
2525
2526};
2527
2528
2529static int es8311_codec_probe(struct snd_soc_component *component)
2530{
2531#ifdef ES8311_DEBUG
2532 printk(KERN_INFO"%s/L%d.\n", __FUNCTION__, __LINE__);
2533#endif
2534
2535 es8311_write(ES8311_RESET_REG00, 0x1f);
2536 es8311_write(ES8311_RESET_REG00, 0x80);
2537
2538 printk("%s, wait for codec internal init\n", __func__);
2539 msleep(5);
2540
2541 es8311_write(ES8311_SYSTEM_REG0D, 0x01);
2542 es8311_write(ES8311_RESET_REG00, 0x1f);
2543 enable_8311_MClock();
2544 snd_soc_add_component_controls(component, es8311_snd_controls, ARRAY_SIZE(es8311_snd_controls));
2545
2546 return 0;
2547}
2548
2549static unsigned int es8311_codec_read(struct snd_soc_component *component, unsigned int reg)
2550{
2551 unsigned short out_val = 0;
2552 int ret;
2553
2554 ret = es8311_read(reg, &out_val);
2555
2556 if(ret)
2557 {
2558 printk("%s, read reg[0x%02x] fail\n", __func__, reg);
2559 return -EIO;
2560 }
2561
2562 out_val = out_val & 0xff;
2563
2564#ifdef ES8311_DEBUG
2565 printk(KERN_INFO"%s/L%d.[0x%02x]=[0x%04x]\n", __FUNCTION__, __LINE__, reg, out_val);
2566#endif
2567
2568 return out_val;
2569}
2570
2571static int es8311_codec_write(struct snd_soc_component *component,
2572 unsigned int reg, unsigned int value)
2573{
2574 int ret = 0;
2575
2576#ifdef ES8311_DEBUG
2577 printk(KERN_INFO"%s/L%d.[0x%02x]=[0x%04x]\n", __FUNCTION__, __LINE__, reg, value);
2578#endif
2579
2580 ret = es8311_write(reg, value & 0xFFFF);
2581
2582 return ret;
2583}
2584
2585/* es8311_dai_ops */
2586
2587static int es8311_digital_mute(struct snd_soc_dai *codec_dai, int mute)
2588{
2589#ifdef ES8311_DEBUG
2590 printk(KERN_INFO"%s/L%d.\n", __FUNCTION__, __LINE__);
2591#endif
2592
2593 return 0;
2594}
2595
2596static int es8311_hw_params(struct snd_pcm_substream *substream,
2597 struct snd_pcm_hw_params *params,
2598 struct snd_soc_dai *dai)
2599{
2600#ifdef ES8311_DEBUG
2601 printk(KERN_INFO"%s/L%d.\n", __FUNCTION__, __LINE__);
2602#endif
2603
2604 return 0;
2605}
2606
2607static int es8311_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
2608{
2609#ifdef ES8311_DEBUG
2610 printk(KERN_INFO"%s/L%d.\n", __FUNCTION__, __LINE__);
2611#endif
2612
2613 return 0;
2614}
2615
2616static int es8311_set_dai_sysclk(struct snd_soc_dai *dai,
2617 int clk_id, unsigned int freq, int dir)
2618{
2619#ifdef ES8311_DEBUG
2620 printk(KERN_INFO"%s/L%d.\n", __FUNCTION__, __LINE__);
2621#endif
2622
2623 return 0;
2624}
2625
2626static const struct snd_soc_component_driver soc_component_dev_es8311 = {
2627 .probe = es8311_codec_probe,
2628 .read = es8311_codec_read,
2629 .write = es8311_codec_write,
2630#if 0
2631 .suspend_bias_off = 1,
2632 .idle_bias_on = 1,
2633 .use_pmdown_time = 1,
2634 .endianness = 1,
2635 .non_legacy_dai_naming = 1,
2636#endif
2637};
2638
2639static struct snd_soc_dai_ops es8311_dai_ops = {
2640 .digital_mute = es8311_digital_mute,
2641 .hw_params = es8311_hw_params,
2642 .set_fmt = es8311_set_dai_fmt,
2643 .set_sysclk = es8311_set_dai_sysclk,
2644};
2645
2646static struct snd_soc_dai_driver es8311_dai[] ={
2647 {
2648 /* DAI I2S(SAI1) */
2649 .name = "es8311-i2s",
2650 .id = 1,
2651 .playback = {
2652 .stream_name = "I2S Playback",
2653 .channels_min = 2,
2654 .channels_max = 2,
2655 .rates = SNDRV_PCM_RATE_8000_48000,
2656 .formats = SNDRV_PCM_FORMAT_S16_LE | \
2657 SNDRV_PCM_FORMAT_S18_3LE,
2658 },
2659 .capture = {
2660 .stream_name = "I2S Capture",
2661 .channels_min = 2,
2662 .channels_max = 2,
2663 .rates = SNDRV_PCM_RATE_8000_48000,
2664 .formats = SNDRV_PCM_FORMAT_S16_LE | \
2665 SNDRV_PCM_FORMAT_S18_3LE,
2666 },
2667 .ops = &es8311_dai_ops,
2668 }, {
2669 /* DAI PCM(SAI2) */
2670 .name = "es8311-pcm",
2671 .id = 2,
2672 .playback = {
2673 .stream_name = "PCM Playback",
2674 .channels_min = 1,
2675 .channels_max = 2,
2676 .rates = SNDRV_PCM_RATE_8000_48000,
2677 .formats = SNDRV_PCM_FORMAT_S8| \
2678 SNDRV_PCM_FORMAT_S16_LE | \
2679 SNDRV_PCM_FORMAT_S20_3LE | \
2680 SNDRV_PCM_FORMAT_S24,
2681 },
2682 .capture = {
2683 .stream_name = "PCM Capture",
2684 .channels_min = 1,
2685 .channels_max = 2,
2686 .rates = SNDRV_PCM_RATE_8000_48000,
2687 .formats = SNDRV_PCM_FORMAT_S8| \
2688 SNDRV_PCM_FORMAT_S16_LE | \
2689 SNDRV_PCM_FORMAT_S20_3LE | \
2690 SNDRV_PCM_FORMAT_S24,
2691 },
2692 .ops = &es8311_dai_ops,
2693 },
2694};
2695
2696#ifdef HEADSET_DETECTION
2697irqreturn_t codec_irq_handler(int irq, void *dev_id)
2698{
2699 printk(KERN_INFO"%s/L%d.\n", __FUNCTION__, __LINE__);
2700
2701 /* check the headset plug in/out */
2702 es8311_get_headset_status();
2703
2704 return IRQ_HANDLED;
2705}
2706#endif
2707
2708//Kestrel
2709void audio_set_codec_vdd(int on_off)
2710{
2711 struct regulator *vdd_1v8 = NULL;
2712 struct regulator *vdd_3v3 = NULL;
2713 static int codec_on_off = 0;
2714
2715 printk(KERN_INFO"%s: codec now:%d, to be:%d\n", __FUNCTION__, codec_on_off, on_off);
2716
2717 if (!(cpu_is_asr1901() || cpu_is_asr1906()) || codec_on_off == on_off)
2718 {
2719 return;
2720 }
2721
2722 if(on_off) {
2723 /* 1V8 */
2724 vdd_1v8 = regulator_get(&g_es8311_client->dev, "vdd18");
2725 if (IS_ERR_OR_NULL(vdd_1v8)) {
2726 if (PTR_ERR(vdd_1v8) < 0) {
2727 printk(KERN_INFO"%s: the regulator for vdd_1v8 not found.\n", __FUNCTION__);
2728 }
2729 } else {
2730 es8311_regulator_vdd_1v8 = vdd_1v8;
2731 printk(KERN_INFO"%s: the regulator for vdd_1v8 is OK.\n", __FUNCTION__);
2732 }
2733
2734 if (es8311_regulator_vdd_1v8 > 0) {
2735 if (regulator_set_voltage(es8311_regulator_vdd_1v8, 1800000, 1800000))
2736 printk(KERN_INFO"fail to set regulator with 1.8v.\n");
2737 if (regulator_enable(es8311_regulator_vdd_1v8))
2738 printk(KERN_INFO"fail to enable regulator vdd_1v8.\n");
2739 }
2740
2741 /* 3V3 */
2742 vdd_3v3 = regulator_get(&g_es8311_client->dev, "vdd33");
2743 if (IS_ERR_OR_NULL(vdd_3v3)) {
2744 if (PTR_ERR(vdd_3v3) < 0) {
2745 printk(KERN_INFO"%s: the regulator for vdd_3v3 not found.\n", __FUNCTION__);
2746 }
2747 } else {
2748 es8311_regulator_vdd_3v3 = vdd_3v3;
2749 printk(KERN_INFO"%s: the regulator for vdd_3v3 is OK.\n", __FUNCTION__);
2750 }
2751
2752 if (es8311_regulator_vdd_3v3 > 0) {
2753 if (regulator_set_voltage(es8311_regulator_vdd_3v3, 3300000, 3300000))
2754 printk(KERN_INFO"fail to set regulator with 3.3v.\n");
2755 if (regulator_enable(es8311_regulator_vdd_3v3))
2756 printk(KERN_INFO"fail to enable regulator vdd_3v3.\n");
2757 }
2758
2759 codec_on_off = 1;
2760 }
2761 else {
2762 if (es8311_regulator_vdd_1v8 > 0) {
2763 if (regulator_disable(es8311_regulator_vdd_1v8))
2764 printk(KERN_INFO"fail to disable regulator vdd_1v8\n");
2765 }
2766
2767 if (es8311_regulator_vdd_3v3 > 0) {
2768 if (regulator_disable(es8311_regulator_vdd_3v3))
2769 printk(KERN_INFO"fail to disable regulator vdd_3v3\n");
2770 }
2771
2772 codec_on_off = 0;
2773 }
2774}
2775EXPORT_SYMBOL_GPL(audio_set_codec_vdd);
2776
2777
2778//Kestrel/NezhaC/Falcon
2779static void es8311_config_init(void)
2780{
2781 struct pinctrl_state *pin_AUDIO = NULL;
2782 int gpio_1V8 = 0;
2783 int gpio_3V3 = 0;
2784#ifdef HEADSET_DETECTION
2785 int ret = -1;
2786#endif
2787
2788#ifdef ES8311_DEBUG
2789 printk(KERN_INFO"%s/L%d.\n", __FUNCTION__, __LINE__);
2790#endif
2791
2792 if (cpu_is_asr1803()) {
2793 printk(KERN_INFO"%s, platform is Falcon.\n", __FUNCTION__);
2794 } else if (cpu_is_asr1806()) {
2795 printk(KERN_INFO"%s, platform is Falcon-T.\n", __FUNCTION__);
2796 } else if (cpu_is_asr1901() || cpu_is_asr1906()) {
2797 printk(KERN_INFO"%s, platform is Kestrel.\n", __FUNCTION__);
2798 } else if (cpu_is_asr1903()) {
2799 printk(KERN_INFO"%s, platform is Lapwing.\n", __FUNCTION__);
2800 } else if (cpu_is_asr1802s()) {
2801 printk(KERN_INFO"%s, platform is Nezhac.\n", __FUNCTION__);
2802 } else {
2803 printk(KERN_INFO"%s, please check the platform.\n", __FUNCTION__);
2804 }
2805
2806 /*
2807 NezhaC AUDIO_PIN_CTRL = TDS_DIO10 = function 1 , GPIO-78
2808 Config MPFR in arch/arm/boot/dts/asr1802s-p201.dts
2809 */
2810 pin_AUDIO = pinctrl_lookup_state(g_es8311_pinctrl, "default");
2811
2812 pinctrl_select_state(g_es8311_pinctrl, pin_AUDIO);
2813
2814 /* config MPFR of device node "asrmicro,es8311" */
2815 if (cpu_is_asr1802s()) {
2816 gpio_tds_dio10 = of_get_named_gpio(g_es8311_node, "tds_dio10-gpio", 0);/* GPIO[78] */
2817 gpio_vcxo_out = of_get_named_gpio(g_es8311_node, "vcxo_out-gpio", 0);/* GPIO[126] */
2818 }
2819
2820 printk(KERN_INFO"%s/L%d, gpio_tds_dio10 = %d, gpio_vcxo_out = %d\n", __FUNCTION__, __LINE__, gpio_tds_dio10, gpio_vcxo_out);
2821
2822 /* TDS_DIO10 */
2823 //gpio_request(gpio_tds_dio10, "TDS_DIO10");
2824 //gpio_direction_output(gpio_tds_dio10, 0);
2825
2826 /* VCXO_OUT */
2827 if (cpu_is_asr1802s()) {
2828 gpio_request(gpio_vcxo_out, "VCXO_OUT");
2829 gpio_direction_input(gpio_vcxo_out);
2830 }
2831
2832 /* config VDD */
2833 if (cpu_is_asr1802s()) {
2834 gpio_1V8 = of_get_named_gpio(g_es8311_node, "1V8-gpio", 0);
2835 }
2836
2837 gpio_3V3 = of_get_named_gpio(g_es8311_node, "3V3-gpio", 0);
2838
2839 printk(KERN_INFO"%s/L%d, gpio_1V8=%d, gpio_3V3=%d.\n", __FUNCTION__, __LINE__, gpio_1V8, gpio_3V3);
2840
2841 /* GPIO_31 for CODEC_1V8_EN.
2842 GPIO_32 for CODEC_3V3_EN. */
2843 //gpio_31_CODEC_1V8_EN = mfp_to_gpio(MFP_PIN_GPIO31);
2844 //gpio_32_CODEC_3V3_EN = mfp_to_gpio(MFP_PIN_GPIO32);
2845
2846 if (cpu_is_asr1802s()) {
2847 gpio_31_CODEC_1V8_EN = gpio_1V8;
2848 }
2849
2850 gpio_32_CODEC_3V3_EN = gpio_3V3;
2851
2852 if (cpu_is_asr1802s()) {
2853 if (gpio_31_CODEC_1V8_EN) {
2854 if (gpio_request(gpio_31_CODEC_1V8_EN, "power on/off 1V8")) {
2855 gpio_31_CODEC_1V8_EN = 0;
2856 } else {
2857 gpio_direction_output(gpio_31_CODEC_1V8_EN, 0);
2858 }
2859 }
2860 }
2861
2862 if (gpio_32_CODEC_3V3_EN >= 0) {
2863 if (gpio_request(gpio_32_CODEC_3V3_EN, "power on/off 3V3")) {
2864 gpio_32_CODEC_3V3_EN = 0;
2865 } else {
2866 gpio_direction_output(gpio_32_CODEC_3V3_EN, 0);
2867 }
2868 }
2869
2870 if (cpu_is_asr1802s()) {
2871 gpio_direction_output(gpio_31_CODEC_1V8_EN, 1);
2872 }
2873
2874 if (gpio_32_CODEC_3V3_EN >= 0) {
2875 gpio_direction_output(gpio_32_CODEC_3V3_EN, 1);
2876 }
2877
2878 /* Power on for ASR1901 kestrel */
2879 audio_set_codec_vdd(1);
2880
2881#ifdef HEADSET_DETECTION
2882 /* CODEC_IRQ */
2883 gpio_CODEC_IRQ = of_get_named_gpio(g_es8311_node, "irq-gpio", 0); //GPIO[1]
2884 printk(KERN_INFO"%s/L%d, gpio_CODEC_IRQ=%d.\n", __FUNCTION__, __LINE__, gpio_CODEC_IRQ);
2885
2886 gpio_request(gpio_CODEC_IRQ, "CODEC_IRQ");
2887 gpio_direction_input(gpio_CODEC_IRQ);
2888
2889 irq_codec = gpio_to_irq(gpio_CODEC_IRQ);
2890 printk(KERN_INFO"%s/L%d, irq_codec=%d.\n", __FUNCTION__, __LINE__, irq_codec);
2891
2892 /* request irq */
2893 ret = request_threaded_irq(irq_codec, NULL, codec_irq_handler,
2894 IRQF_SHARED | IRQF_TRIGGER_RISING |
2895 IRQF_TRIGGER_FALLING | IRQF_ONESHOT, "es8311-headset_detection",
2896 g_es8311_client);
2897 if (ret < 0) {
2898 printk(KERN_INFO"%s: request irq failed!\n",__FUNCTION__);
2899 }
2900#endif
2901
2902#if 0 //The vdds should be supplied
2903 /* Power off for ASR1901 kestrel */
2904 audio_set_codec_vdd(0);
2905#endif
2906
2907 return;
2908}
2909
2910static int g_fsync_rate = 0;
2911static ssize_t es8311_switch_rate_show(struct device *dev, struct device_attribute *attr,
2912 char *buf)
2913{
2914 int s = 0;
2915
2916 s += sprintf(buf, "%d", g_fsync_rate);
2917 return s;
2918}
2919
2920static ssize_t es8311_switch_rate_set(struct device *dev,
2921 struct device_attribute *attr,
2922 const char *buf, size_t count)
2923{
2924 int ret;
2925
2926 ret = kstrtoint(buf, 10, &g_fsync_rate);
2927 if (ret)
2928 return ret;
2929
2930 Audio_Codec_Fsync_Rate = g_fsync_rate;
2931 enable_8311_MClock();
2932 printk(KERN_INFO"%s, Audio_Codec_Fsync_Rate=%d\n", __FUNCTION__, Audio_Codec_Fsync_Rate);
2933
2934 return count;
2935}
2936static DEVICE_ATTR(es8311_switch_rate, 0644, es8311_switch_rate_show, es8311_switch_rate_set);
2937
2938
2939
2940
2941
2942
2943static ssize_t es8311_reg_show(struct device *dev, struct device_attribute *attr, char *_buf)
2944{
2945 int reg = 0;
2946 unsigned short read_value;
2947
2948 for(reg = 0; reg <= es8311_reg_NUM; reg++)
2949 {
2950 switch(reg)
2951 {
2952 case 0x00 ... 0x1c:
2953 case 0x31 ... 0x37:
2954 case 0x44:
2955 case 0xfd ... 0xff:
2956 {
2957 es8311_read(reg, &read_value);
2958 sprintf(_buf + strlen(_buf), "%s, reg:0x%02x value:0x%02x\r\n", __func__, reg, read_value);
2959 break;
2960 }
2961
2962 default :
2963 {
2964 break;
2965 }
2966 }
2967
2968 }
2969
2970 return strlen(_buf);
2971}
2972
2973
2974
2975static ssize_t es8311_reg_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)
2976{
2977
2978 if(buf[0] == '1')
2979 {
2980
2981 es8311_write(0x45, 0x00);
2982 es8311_write(0x01, 0x30);
2983 es8311_write(0x02, 0x10);
2984
2985 es8311_write(0x02, 0x00);
2986 es8311_write(0x03, 0x10);
2987 es8311_write(0x16, 0x24);
2988 es8311_write(0x04, 0x20);
2989 es8311_write(0x05, 0x00);
2990
2991 es8311_write(0x06, 0x20);
2992 es8311_write(0x07, 0x00);
2993
2994 es8311_write(0x08, 0xff);
2995 es8311_write(0x09, 0x0f);
2996
2997 es8311_write(0x0a, 0x0f);
2998
2999 es8311_write(0x0b, 0x00);
3000 es8311_write(0x0c, 0x00);
3001
3002 es8311_write(0x10, 0x03);
3003
3004 es8311_write(0x11, 0x7f);
3005 es8311_write(0x01, 0x3f);
3006
3007 es8311_write(0x00, 0x80);
3008 mdelay(1);
3009 es8311_write(0x0d, 0x01);
3010 es8311_write(0x14, 0x1a);
3011 es8311_write(0x12, 0x28);
3012 es8311_write(0x13, 0x10);
3013
3014 es8311_write(0x0e, 0x02);
3015 es8311_write(0x0f, 0x44);
3016 es8311_write(0x15, 0x00);
3017 es8311_write(0x1b, 0x0a);
3018 es8311_write(0x1c, 0x6a);
3019 es8311_write(0x37, 0x08);
3020 es8311_write(0x44, 0x00); //value:0x80 »Ø»·²âÊÔ
3021 es8311_write(0x17, 0x8f);
3022 es8311_write(0x32, 0xbf);
3023
3024
3025
3026 //gpio_set_value(es8311_drv_data.audio_ctl_gpio[AUDIO_CTL_PA_MUTE], 1);
3027 // gpio_set_value(es8311_drv_data.audio_ctl_gpio[AUDIO_CTL_PA_STATE], 0);
3028 }
3029 else
3030 {
3031 es8311_write(0x0e, 0xff);
3032 es8311_write(0x12, 0x02);
3033 es8311_write(0x14, 0x00);
3034 es8311_write(0x0d, 0xf9);
3035 es8311_write(0x15, 0x00);
3036 es8311_write(0x0d, 0xf9);
3037 es8311_write(0x37, 0x08);
3038 es8311_write(0x02, 0x10);
3039 es8311_write(0x00, 0x00);
3040 es8311_write(0x00, 0x1f);
3041 es8311_write(0x01, 0x30);
3042 es8311_write(0x01, 0x00);
3043 es8311_write(0x45, 0x00);
3044 // gpio_set_value(es8311_drv_data.audio_ctl_gpio[AUDIO_CTL_PA_MUTE], 0);
3045 // gpio_set_value(es8311_drv_data.audio_ctl_gpio[AUDIO_CTL_PA_STATE], 1);
3046 }
3047
3048 return count;
3049}
3050
3051
3052static DEVICE_ATTR(es8311_reg_op, 0664, es8311_reg_show, es8311_reg_store);
3053
3054
3055
3056/* i2c driver */
3057static int es8311_probe(struct i2c_client *client,
3058 const struct i2c_device_id *id)
3059{
3060 int ret = 0;
3061
3062 printk(KERN_INFO"[8311 codec-dai probe: begin] %s/L%d.\n", __FUNCTION__, __LINE__);
3063 printk("--->%s/L%d\n", __FUNCTION__, __LINE__);
3064 if (NULL == client) {
3065 printk(KERN_INFO"Please check codec input parameter for client.\n");
3066 return 0;
3067 }
3068
3069 g_es8311_client = client;
3070
3071 g_es8311_pinctrl = devm_pinctrl_get(&client->dev);
3072 if (NULL == g_es8311_pinctrl){
3073 printk(KERN_INFO"Please check codec input parameter for g_es8311_pinctrl.\n");
3074 return 0;
3075 }
3076
3077 g_es8311_node = client->dev.of_node;
3078 if (NULL == g_es8311_node){
3079 printk(KERN_INFO"Please check codec input parameter for g_es8311_node.\n");
3080 return 0;
3081 }
3082
yu.dongb3e49372025-06-23 23:57:56 -0700[diff] [blame]3083#ifdef CONFIG_CODEC_VDDD_EN
3084 /* Get CODEC_VDDD_EN GPIO from device tree */
3085 gpio_codec_vddd_en = of_get_gpio(g_es8311_node, 0);
3086 printk(KERN_INFO"es8311_probe: gpio_codec_vddd_en=%d\n", gpio_codec_vddd_en);
3087
3088 /* CODEC_VDDD_EN GPIO control from device tree */
3089 if (gpio_codec_vddd_en >= 0) {
3090 if (gpio_request(gpio_codec_vddd_en, "codec_vddd_en") == 0) {
3091 gpio_direction_output(gpio_codec_vddd_en, 1);
3092 printk(KERN_EMERG "0624 GPIO%d CODEC_VDDD_EN set to high (from DTS)\n", gpio_codec_vddd_en);
3093 } else {
3094 printk(KERN_EMERG "GPIO%d request failed\n", gpio_codec_vddd_en);
3095 }
3096 } else {
3097 printk(KERN_EMERG "CODEC_VDDD_EN GPIO not configured in device tree\n");
3098 }
3099#endif
3100
b.liub17525e2025-05-14 17:22:29 +0800[diff] [blame]3101 es8311_dump_debugfs_init(NULL);
3102
3103 // es8311_audio_debugfs_init(NULL);
3104
3105 /* Power on the ES8311. */
3106 //es8311_config_init();
3107
3108 /* initiate the ES8311 codec. */
3109 // codec_es8311_init();
3110
3111 // if (!es8311_is_connect()) {
3112 // printk(KERN_INFO"Please check codec es8311 OK or not.\n");
3113 // return 0;
3114 // }
3115
3116#ifdef CONFIG_CPU_ASR1901
3117 if(!enable_pmu_audio_clk())
3118 {
3119#endif
3120 // enable_8311_MClock();
3121 // es8311_set_sysclk(1);
3122#ifdef CONFIG_CPU_ASR1901
3123 }
3124#endif
3125
3126#if 0
3127 /* if debug the codec in kernel, could open the procedure */
3128
3129 /* enable the path. */
3130 codec_ES8311_power_on();
3131
3132 //codec_es8311_enable_headphone_main_mic();
3133 //codec_es8311_switch_headset(1);
3134
3135 es8311_headphone_on();
3136 es8311_headset_mic_on();
3137
3138 codec_ES8311_set_headphone_gain();
3139 codec_ES8311_set_headphone_mic_gain();
3140#endif
3141
3142#if 0
3143 /* if debug the codec in kernel, could open the procedure for spk */
3144
3145 /* enable the path. */
3146 codec_ES8311_power_on();
3147
3148 es8311_speaker_on();
3149 es8311_main_mic_on();
3150 /* Enable the speaker path using the command:echo 7 > /sys/kernel/debug/es8311_audio */
3151 /* Enable PA from CP or Enable PA using the command:echo 0 > /sys/kernel/debug/es8311_audio */
3152#endif
3153 /*
3154 create the platform device, and platform driver will register codec to ALSA.
3155 which will be for device node, such as /dev/snd/timer, control0, ...
3156 snd_soc_register_codec(&client->dev, &soc_codec_dev_es8311,
3157 es8311_dai, ARRAY_SIZE(es8311_dai));
3158 int snd_soc_register_card(struct snd_soc_card *card)
3159 */
3160 ret = devm_snd_soc_register_component(&client->dev, &soc_component_dev_es8311,
3161 es8311_dai, ARRAY_SIZE(es8311_dai));
3162
3163 if (ret < 0) {
3164 printk(KERN_INFO"Failed to register codec es8311: %d.\n", ret);
3165 return ret;
3166 }
3167
3168 /* Headset detection platform device */
3169 //es8311_headset_detection_init(client);
3170
3171 /* create the interface for audio_if command "config_pcm" */
3172 ret = device_create_file(&client->dev, &dev_attr_es8311_switch_rate);
3173 if (ret < 0) {
3174 printk(KERN_INFO"attr es8311_switch_rate create fail: %d.\n", ret);
3175 return ret;
3176 }
3177
3178 ret = device_create_file(&client->dev, &dev_attr_es8311_reg_op);
3179 if (ret < 0) {
3180 printk(KERN_INFO"attr dev_attr_es8311_reg_op create fail: %d.\n", ret);
3181 return ret;
3182 }
3183
3184 printk(KERN_INFO"[8311 codec-dai probe: end] %s/L%d.\n", __FUNCTION__, __LINE__);
3185
3186
3187
3188 return 0;
3189}
3190
3191static int es8311_remove(struct i2c_client *client)
3192{
3193#ifdef ES8311_DEBUG
3194 printk(KERN_INFO"%s/L%d.\n", __FUNCTION__, __LINE__);
3195#endif
3196
3197 es8311_dump_debugfs_remove(NULL);
3198
3199 // es8311_audio_debugfs_remove(NULL);
3200
3201 /* free gpio resource. */
3202 //gpio_free(gpio_tds_dio10);
3203 if (cpu_is_asr1802s()) {
3204 gpio_free(gpio_vcxo_out);
3205 }
3206
3207 if (cpu_is_asr1802s()) {
3208 gpio_free(gpio_31_CODEC_1V8_EN);
3209 }
3210
3211 if (gpio_32_CODEC_3V3_EN >= 0) {
3212 gpio_free(gpio_32_CODEC_3V3_EN);
3213 }
3214
3215 /* Power off for ASR1901 kestrel */
3216 audio_set_codec_vdd(0);
3217
yu.dongb3e49372025-06-23 23:57:56 -0700[diff] [blame]3218#ifdef CONFIG_CODEC_VDDD_EN
3219 if (gpio_is_valid(gpio_codec_vddd_en)) {
3220 gpio_free(gpio_codec_vddd_en);
3221 printk(KERN_INFO "es8311: Released gpio_codec_vddd_en\n");
3222 }
3223#endif
3224
b.liub17525e2025-05-14 17:22:29 +0800[diff] [blame]3225#ifdef HEADSET_DETECTION
3226 gpio_free(gpio_CODEC_IRQ);
3227 free_irq(irq_codec, g_es8311_client);
3228#endif
3229 /* disable the path. */
3230 //codec_es8311_disable_path();
3231 //codec_es8311_disable_path_app();
3232
3233 codec_es8311_power_off();
3234
3235 g_es8311_client = NULL;
3236
3237 mfd_remove_devices(&client->dev);
3238 return 0;
3239}
3240
3241void es8311_shutdown(struct i2c_client *client)
3242{
3243#ifdef ES8311_DEBUG
3244 printk(KERN_INFO"%s/L%d.\n", __FUNCTION__, __LINE__);
3245#endif
3246
3247 return;
3248}
3249
yu.dongb3e49372025-06-23 23:57:56 -0700[diff] [blame]3250static int es8311_i2c_suspend(struct device *dev)
3251{
3252 printk(KERN_INFO "es8311: Entering suspend\n");
3253
3254#ifdef CONFIG_CODEC_VDDD_EN
3255 if (gpio_is_valid(gpio_codec_vddd_en)) {
3256 gpio_direction_output(gpio_codec_vddd_en, 0);
3257 printk(KERN_INFO "es8311: codec_vddd_en set to input (low) for suspend\n");
3258 }
3259#endif
3260
3261 audio_set_codec_vdd(0);
3262
3263 return 0;
3264}
3265
3266static int es8311_i2c_resume(struct device *dev)
3267{
3268 int ret = 0;
3269 struct i2c_client *client = to_i2c_client(dev);
3270
3271 printk(KERN_INFO "es8311: Exiting suspend\n");
3272
3273#ifdef CONFIG_CODEC_VDDD_EN
3274 if (gpio_is_valid(gpio_codec_vddd_en)) {
3275 ret = gpio_direction_output(gpio_codec_vddd_en, 1);
3276 if (ret) {
3277 printk(KERN_ERR "es8311: Failed to set gpio_codec_vddd_en to output high: %d\n", ret);
3278 } else {
3279 printk(KERN_INFO "es8311: codec_vddd_en set to output high for resume\n");
3280 }
3281 }
3282#endif
3283
3284 audio_set_codec_vdd(1);
3285
3286 return ret;
3287}
3288
3289static const struct dev_pm_ops es8311_dev_pm_ops = {
3290 SET_SYSTEM_SLEEP_PM_OPS(es8311_i2c_suspend, es8311_i2c_resume)
3291};
3292
b.liub17525e2025-05-14 17:22:29 +0800[diff] [blame]3293static struct i2c_driver es8311_driver = {
3294 .driver = {
3295 .name = "es8311",
3296 .of_match_table = of_match_ptr(es8311_dt_ids),
yu.dongb3e49372025-06-23 23:57:56 -0700[diff] [blame]3297 .pm = &es8311_dev_pm_ops,
b.liub17525e2025-05-14 17:22:29 +0800[diff] [blame]3298 },
3299 .probe = es8311_probe,
3300 .remove = es8311_remove,
3301 //.shutdown = es8311_shutdown,
3302 .id_table = es8311_id_table,
3303};
3304
3305static int ex8311_i2c_init(void)
3306{
3307 return i2c_add_driver(&es8311_driver);
3308}
3309module_init(ex8311_i2c_init);
3310
3311static void es8311_i2c_exit(void)
3312{
3313 i2c_del_driver(&es8311_driver);
3314}
3315module_exit(es8311_i2c_exit);
3316
3317MODULE_DESCRIPTION("Driver for es8311");
3318MODULE_AUTHOR("wenchen@asrmicro.com");
3319MODULE_LICENSE("GPL");