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192.168.1.100 / T108 / c2023d5d03be91dbb983606f0ec5e9e4ea36c8c2 / . / marvell / linux / drivers / mfd / tlv320aic3x.c
blob: 53789891a485098cb4385d93c7c8eb2a53b65dd8 [file] [log] [blame]
b.liub17525e2025-05-14 17:22:29 +0800[diff] [blame]1/*
2 * Base driver for ASR tlv320aic3x
3 *
4 * Copyright (C) 2019 ASR.
5 *
6 * This file is subject to the terms and conditions of the GNU General
7 * Public License. See the file "COPYING" in the main directory of this
8 * archive for more details.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#include <linux/kernel.h>
21#include <linux/module.h>
22#include <linux/i2c.h>
23#include <linux/irq.h>
24#include <linux/mfd/core.h>
25#include <linux/mfd/88pm80x.h>
26#include <linux/slab.h>
27#include <linux/delay.h>
28#include <linux/of_device.h>
29#include <linux/uaccess.h>
30#include <linux/proc_fs.h>
31#include <linux/fs.h>
32#include <linux/debugfs.h>
33#include <sound/pcm.h>
34#include <sound/soc.h>
35#include <linux/gpio.h>
36//#include <plat/mfp.h>
37#include <linux/regulator/consumer.h>
38#include <linux/pinctrl/consumer.h>
39#include <linux/platform_device.h>
40#include <linux/mutex.h>
41#include <linux/of.h>
42#include <linux/of_gpio.h>
43#include <asm/io.h>
44#include <linux/interrupt.h>
45#include <linux/cputype.h>
46#include <soc/asr/addr-map.h>
47#include "tlv320aic3x.h"
48#include <linux/clk.h>
49
50#ifndef APB_VIRT_BASE
51#define APB_VIRT_BASE IOMEM(0xfe000000)
52#endif
53
54#define SSP1_I2S_CLOCK_REG_ADDR (0xD4050044)
55
56#ifdef Kestrel_Z2
57//Kestrel Z2
58static void __iomem *VCXO_OUT_MFPR_reg = APB_VIRT_BASE + 0x1E000 + 0x208;/* 0xD401E000+0x208 */
59static void __iomem *PM_MN_CLK_reg = APB_VIRT_BASE + 0x51000 + 0xA4;/* 0xD4051000+0xA4 */
60static void __iomem *GPCR_reg = APB_VIRT_BASE + 0x50000 + 0x30;/* 0xD4050030 */
61#else
62//Kestrel A0
63static void __iomem *MCLK_CLK_CTRL_reg = NULL;/* 0xD6800000+0x4C */
64static void __iomem *MCLK_MN_DIV_reg = NULL;/* 0xD6800000+0x50 */
65#endif
66
67//NezhaC/Falcon
68static void __iomem *SSP1_I2S_CLOCK_reg = APB_VIRT_BASE + 0x50000 + 0x44;/* 0xD4050000+0x44 */
69
70#if defined(CONFIG_CODEC_PCM_NB)
71/* Narrowband */
72char Audio_Codec_Fsync_Rate = 0;
73#elif defined(CONFIG_CODEC_PCM_WB)
74/* Wideband */
75char Audio_Codec_Fsync_Rate = 1;
76#elif defined(CONFIG_CODEC_PCM_32KHz)
77/* 32KHz */
78char Audio_Codec_Fsync_Rate = 2;
79#elif defined(CONFIG_CODEC_PCM_48KHz)
80/* 48KHz */
81char Audio_Codec_Fsync_Rate = 3;
82#else
83/* Narrowband */
84char Audio_Codec_Fsync_Rate = 0;
85#endif
86
87#ifdef CONFIG_CODEC_PCM_MASTER
88/* CODEC is master, GSSP is slave. */
89
90char G_AudioModemMaster = 0;
91#else
92/* CODEC PCM config is slave in config/defconfig_asr1802sp201
93 CODEC is slave, GSSP is master. */
94
95char G_AudioModemMaster = 1;
96#endif
97
98static const struct i2c_device_id tlv320aic3x_dt_table[] = {
99 {"tlv320aic3x", 0},
100 {} /* NULL terminated */
101};
102MODULE_DEVICE_TABLE(i2c, tlv320aic3x_dt_table);
103
104static const struct of_device_id tlv320aic3x_dt_ids[] = {
105 { .compatible = "ti,tlv320aic3104", },
106 {},
107};
108MODULE_DEVICE_TABLE(of, tlv320aic3x_dt_ids);
109
110static struct i2c_client *g_tlv320aic3x_client = NULL;
111static struct pinctrl *g_tlv320aic3x_pinctrl = NULL;
112static struct device_node *g_tlv320aic3x_node = NULL;
113static void __iomem *i2s_clk_reg = NULL;
114
115static int gpio_tds_dio10 = 0; /* GPIO[78] */
116static int gpio_vcxo_out = 0; /* GPIO[126] */
117static int gpio_31_CODEC_1V8_EN = 0; /* GPIO[31] */
118static int gpio_32_CODEC_3V3_EN = 0; /* GPIO[32] */
119
120static int g_reset_gpio = -1;
121static struct regulator *tlv320aic3x_regulator_vdd_1v8 = NULL;
122static struct regulator *tlv320aic3x_regulator_vdd_3v3 = NULL;
123
124#ifdef HEADSET_DETECTION
125static int gpio_CODEC_IRQ = 0; /* GPIO[1] */
126static int irq_codec;
127#endif
128
129//#define HEADSET_DETECTION
130//#define TLV320AIC3X_DEBUG
131//#define TLV320AIC3X_DEBUG_CLOSE
132
133#define tlv320aic3x_reg_NUM 0xFF
134/* base functions */
135
136static unsigned short tlv320aic3x_readable_register(unsigned int reg)
137{
138 switch (reg) {
139 case TLV320AIC3X_RESET_REG00:
140 case TLV320AIC3X_CLK_MANAGER_REG01:
141 case TLV320AIC3X_CLK_MANAGER_REG02:
142 case TLV320AIC3X_CLK_MANAGER_REG03:
143 case TLV320AIC3X_CLK_MANAGER_REG04:
144 case TLV320AIC3X_CLK_MANAGER_REG05:
145 case TLV320AIC3X_CLK_MANAGER_REG06:
146 case TLV320AIC3X_CLK_MANAGER_REG07:
147 case TLV320AIC3X_CLK_MANAGER_REG08:
148 case TLV320AIC3X_SDPIN_REG09:
149 case TLV320AIC3X_SDPOUT_REG0A:
150 case TLV320AIC3X_SYSTEM_REG0B:
151 case TLV320AIC3X_SYSTEM_REG0C:
152 case TLV320AIC3X_SYSTEM_REG0D:
153 case TLV320AIC3X_SYSTEM_REG0E:
154 case TLV320AIC3X_SYSTEM_REG0F:
155 case TLV320AIC3X_SYSTEM_REG10:
156 case TLV320AIC3X_SYSTEM_REG11:
157 case TLV320AIC3X_SYSTEM_REG12:
158 case TLV320AIC3X_SYSTEM_REG13:
159 case TLV320AIC3X_SYSTEM_REG14:
160 case TLV320AIC3X_ADC_REG15:
161 case TLV320AIC3X_ADC_REG16:
162 case TLV320AIC3X_ADC_REG17:
163 case TLV320AIC3X_ADC_REG18:
164 case TLV320AIC3X_ADC_REG19:
165 case TLV320AIC3X_ADC_REG1A:
166 case TLV320AIC3X_ADC_REG1B:
167 case TLV320AIC3X_ADC_REG1C:
168 case TLV320AIC3X_ADC_REG1E:
169 case TLV320AIC3X_DAC_REG31:
170 case TLV320AIC3X_DAC_REG32:
171 case TLV320AIC3X_DAC_REG33:
172 case TLV320AIC3X_PRIV_INDEX:
173 case TLV320AIC3X_PRIV_DATA:
174 case TLV320AIC3X_DAC_REG34:
175 case TLV320AIC3X_DAC_REG35:
176 case TLV320AIC3X_DAC_REG37:
177 case TLV320AIC3X_GPIO_REG44:
178 case TLV320AIC3X_GP_REG45:
179 case TLV320AIC3X_CHD1_REGFD:
180 case TLV320AIC3X_CHD2_REGFE:
181 case TLV320AIC3X_CHVER_REGFF:
182 return 1;
183 default:
184 return 0;
185 }
186}
187
188/******************************************************************************
189 * Function : tlv320aic3x_reg_read
190 *******************************************************************************
191 *
192 * Description :
193 *
194 * Parameters : char RegAddr
195 * Parameters : unsigned short *value
196 *
197 * Output Param : None.
198 *
199 * Return value :
200 *
201 * Notes :
202 *******************************************************************************/
203static int tlv320aic3x_reg_read(struct i2c_client *client, unsigned char reg)
204{
205 unsigned char data[1] = {0};
206 int value = 0x0;
207
208 data[0] = reg & 0xFF;
209
210 if (data[0] > 0x00)
211 {
212 data[0] -= 1;
213 }
214
215 if(i2c_master_send(client, data, 1) == 1) {
216 i2c_master_recv(client, data, 1);
217 value = data[0];
218#ifdef TLV320AIC3X_DEBUG
219 printk(KERN_INFO"%s: tlv320aic3x read reg:[0x%02x]=0x%02x\n", __FUNCTION__, reg, value);
220#endif
221 return value;
222 } else {
223 printk(KERN_INFO"%s: tlv320aic3x read failed.\n", __FUNCTION__);
224 return -EIO;
225 }
226}
227
228
229static int tlv320aic3x_read(unsigned char reg, unsigned short *oValue)
230{
231 int value;
232
233 value = tlv320aic3x_reg_read(g_tlv320aic3x_client, reg);
234
235 if (value < 0)
236 {
237 printk(KERN_INFO"%s: tlv320aic3x_reg read failed.\n", __FUNCTION__);
238
239 *oValue = 0x00;
240 return -EIO;
241 }
242
243 *oValue = value & 0xFF;
244
245 return 0;
246}
247/******************************************************************************
248 * Function : tlv320aic3x_write
249 *******************************************************************************
250 *
251 * Description :
252 *
253 * Parameters : char RegAddr
254 * Parameters : unsigned short RegData
255 *
256 * Output Param : None.
257 *
258 * Return value :
259 *
260 * Notes :
261 *******************************************************************************/
262static int tlv320aic3x_reg_write(struct i2c_client *client, char reg, unsigned short value)
263{
264 char data[3] = {0};
265
266 data[0] = reg & 0xFF;
267 // data[1] = (char)((value >> 8) & 0xFF);
268 data[1] = (char)(value & 0xFF);
269
270 if (i2c_master_send(client, data, 2) == 2) {
271#ifdef TLV320AIC3X_DEBUG
272 printk(KERN_INFO"%s=> reg:0x%02x,value:0x%02x success\n", __FUNCTION__, reg, value);
273#endif
274 return 0;
275 } else {
276 printk(KERN_INFO"%s=> reg:0x%02x,value:0x%02x error\n", __FUNCTION__, reg, value);
277 return -1;
278 }
279}
280
281static int tlv320aic3x_write(unsigned char reg, unsigned short value)
282{
283 int ret;
284
285#ifdef TLV320AIC3X_DEBUG_CLOSE
286 unsigned short read_value;
287#endif
288
289 ret = tlv320aic3x_reg_write(g_tlv320aic3x_client, reg, value);
290 if (ret < 0)
291 {
292 printk(KERN_INFO"%s:L%d: tlv320aic3x_write() error.\n", __FUNCTION__, __LINE__);
293 }
294
295#ifdef TLV320AIC3X_DEBUG_CLOSE
296 //for check whether write is OK or not.
297 ret = tlv320aic3x_read(reg, &read_value);
298 if (ret < 0)
299 {
300 printk(KERN_INFO"%s:L%d: tlv320aic3x_read() error.\n", __FUNCTION__, __LINE__);
301 }
302
303 printk(KERN_INFO"%s:L%d: reg=0x%02x, value=0x%04x, read_value=0x%04x. Please check it:%s.\n",
304 __FUNCTION__, __LINE__, reg, value, read_value, (value == read_value)?"OK":"FAIL");
305#endif
306 return ret;
307}
308
309static int tlv320aic3x_update_bit(unsigned char reg, unsigned short mask, unsigned short value)
310{
311 int status = 0;
312 unsigned short orig = 0;
313 unsigned short tmp = 0;
314
315 status = tlv320aic3x_read(reg, &orig);
316 if (status < 0)
317 {
318 printk(KERN_INFO"%s:L%d: tlv320aic3x_read() error.\n", __FUNCTION__, __LINE__);
319 return status;
320 }
321 else
322 {
323 tmp = orig & (~mask);
324 tmp |= (value & mask);
325
326 if (tmp != orig)
327 {
328 status = tlv320aic3x_write(reg, tmp);
329 if (status < 0)
330 {
331 printk(KERN_INFO"%s:L%d: tlv320aic3x_write() error.\n", __FUNCTION__, __LINE__);
332 return status;
333 }
334 }
335 }
336
337#ifdef TLV320AIC3X_DEBUG_CLOSE
338 printk(KERN_INFO"%s:L%d: reg=0x%02x, mask=0x%02x, value=0x%04x, orig=0x%04x, last_value=0x%04x, please check it:%s.\n",
339 __FUNCTION__, __LINE__, reg, mask, value, orig, tmp, (orig == tmp)?"EQUAL":"UNEQUAL");
340#endif
341
342 return status;
343}
344
345static int tlv320aic3x_index_read(unsigned char RegAddr, unsigned short *value)
346{
347 int status = -1;
348
349 status = tlv320aic3x_write(TLV320AIC3X_PRIV_INDEX, RegAddr);
350 if (status != 0)
351 {
352 printk(KERN_INFO"status: %d, RegAddr: 0x%04x\n", status, RegAddr);
353 return status;
354 }
355
356 status = tlv320aic3x_read(TLV320AIC3X_PRIV_DATA, value);
357 if (status != 0)
358 {
359 printk(KERN_INFO"status: %d, RegAddr: 0x%04x\n", status, RegAddr);
360 return status;
361 }
362
363 return status;
364}
365
366static int tlv320aic3x_index_write(char RegAddr, unsigned short value)
367{
368 int status = -1;
369
370 status = tlv320aic3x_write(TLV320AIC3X_PRIV_INDEX, RegAddr);
371 if (status != 0)
372 {
373 printk(KERN_INFO"status: %d, RegAddr: 0x%04x\n", status, RegAddr);
374 return status;
375 }
376
377 status = tlv320aic3x_write(TLV320AIC3X_PRIV_DATA, value);
378 if (status != 0)
379 {
380 printk(KERN_INFO"status: %d, RegAddr: 0x%04x\n", status, RegAddr);
381 return status;
382 }
383
384 return status;
385}
386
387static int tlv320aic3x_index_update_bits(char RegAddr, unsigned short mask, unsigned short value)
388{
389 int status = -1;
390 unsigned short orig;
391 unsigned short tmp;
392
393 status = tlv320aic3x_index_read(RegAddr, &orig);
394 if (status != 0)
395 {
396 printk(KERN_INFO"status: %d, RegAddr: 0x%04x\n", status, RegAddr);
397 }
398 else
399 {
400 tmp = orig & (~mask);
401 tmp |= (value & mask);;
402
403 if (tmp != orig)
404 {
405 status = tlv320aic3x_index_write(RegAddr, tmp);
406 if (status != 0)
407 {
408 printk(KERN_INFO"status: %d, RegAddr: 0x%04x\n", status, RegAddr);
409 }
410 }
411 }
412
413 return status;
414}
415
416
417#define TLV320AIC3X_STATE_OFF 0x00
418
419static char tlv320aic3x_init_ok = 0;
420static char connect_TLV320AIC3X = 0;
421static char TLV320AIC3X_work_state = TLV320AIC3X_STATE_OFF;
422
423static char l_connect_tlv320aic3x = 0;
424
425int tlv320aic3x_is_connect(void)
426{
427 return l_connect_tlv320aic3x;
428}
429
430int codec_tlv320aic3x_init(void)
431{
432 static char tlv320aic3x_init_ok = 0;
433 short value = 0;
434
435 if(0 == tlv320aic3x_init_ok){
436 //codec_tlv320aic3x_enable_mfpr();
437 /* check if has codec tlv320aic3x*/
438 tlv320aic3x_read(0xFE, &value);
439
440 if (0x10EC == value) {
441 tlv320aic3x_write(0x00, 0x00);
442 tlv320aic3x_init_ok = 1;
443 l_connect_tlv320aic3x = 1;
444
445 tlv320aic3x_init_ok = 1;
446 connect_TLV320AIC3X = 1;
447 }
448 }
449
450 printk(KERN_INFO"%s:L%d: tlv320aic3x_init_ok=%d, l_connect_tlv320aic3x =%d.\n",
451 __FUNCTION__, __LINE__, tlv320aic3x_init_ok, l_connect_tlv320aic3x);
452
453 return !tlv320aic3x_init_ok;
454}
455
456static int g_tlv320aic3x_mclk_type = 1; /* 0: use bitclk, 1: use i2s_mclk, 2, use bitclk and turn on i2s_mclk */
457static int g_tlv320aic3xmainmic_type = 0; /* 0: differential mode, 1: single mode */
458
459/***********************************************************************
460 INTCBind() could only use one lisr for ***all*** GPIOs,
461 So, headset detection is disabled by default on ASR1802S EVB.
462
463 So, we need to set g_tlv320aic3xheadset_plugged=1 by default;
464 thus user just need to plugin headset and no other operation/command is needed.
465 ************************************************************************/
466static int g_tlv320aic3xheadset_plugged = 1; /* 0: headset plug out, 1: headset plug in */
467static int g_tlv320aic3xheadset_mic = 0; /* 0: without HS_MIC, 1: with HS_MIC */
468
469/***********************************************************************
470 When we enable headset detection, could not power off codec
471 i.e could not call codec_tlv320aic3x_power_on/codec_tlv320aic3x_power_off
472 ************************************************************************/
473int g_tlv320aic3xheadset_detection_enabled = 0; /* 0: disable, 1: enable */
474
475#define is_speaker_on() (TLV320AIC3X_work_state & 0x01)
476#define is_headphone_on() (TLV320AIC3X_work_state & 0x02)
477#define is_main_mic_on() (TLV320AIC3X_work_state & 0x04)
478#define is_headset_mic_on() (TLV320AIC3X_work_state & 0x08)
479
480struct reg_value_group {
481 char reg;
482 unsigned short mask;
483 unsigned short value;
484};
485
486void disable_tlv320aic3x_MClock(void);
487void enable_tlv320aic3x_MClock(void);
488
489static int disableTLV320AIC3X = 0;
490static int disableTLV320AIC3XHsMic = 0;
491void disableCodecTLV320AIC3X(void)
492{
493 disableTLV320AIC3X = 1;
494}
495
496static int disableTLV320AIC3XDefaultPower = 0;
497void disableCodecTLV320AIC3XPower(void)
498{
499 disableTLV320AIC3XDefaultPower = 1;
500}
501
502void disableCodecTLV320AIC3XHsMic(void)
503{
504 disableTLV320AIC3XHsMic = 1;
505}
506
507int codec_tlv320aic3x_is_connect(void)
508{
509 return connect_TLV320AIC3X;
510}
511
512static void TLV320AIC3X_set_work_state(char device, char onoff)
513{
514 if (device == TLV320AIC3X_OUTPUT_DEVICE_SPEAKER)
515 {
516 if (onoff == TLV320AIC3X_DEVICE_OFF)
517 {
518 TLV320AIC3X_work_state &= 0xFE;
519 }
520 else if (onoff == TLV320AIC3X_DEVICE_ON)
521 {
522 TLV320AIC3X_work_state |= 0x01;
523 }
524 }
525 else if (device == TLV320AIC3X_OUTPUT_DEVICE_HEADPHONE)
526 {
527 if (onoff == TLV320AIC3X_DEVICE_OFF)
528 {
529 TLV320AIC3X_work_state &= 0xFD;
530 }
531 else if (onoff == TLV320AIC3X_DEVICE_ON)
532 {
533 TLV320AIC3X_work_state |= 0x02;
534 }
535 }
536 else if (device == TLV320AIC3X_INPUT_DEVICE_MAIN_MIC)
537 {
538 if (onoff == TLV320AIC3X_DEVICE_OFF)
539 {
540 TLV320AIC3X_work_state &= 0xFB;
541 }
542 else if (onoff == TLV320AIC3X_DEVICE_ON)
543 {
544 TLV320AIC3X_work_state |= 0x04;
545 }
546 }
547 else if (device == TLV320AIC3X_INPUT_DEVICE_HEADSET_MIC)
548 {
549 if (onoff == TLV320AIC3X_DEVICE_OFF)
550 {
551 TLV320AIC3X_work_state &= 0xF7;
552 }
553 else if (onoff == TLV320AIC3X_DEVICE_ON)
554 {
555 TLV320AIC3X_work_state |= 0x08;
556 }
557 }
558}
559
560/* audio control functions */
561static void tlv320aic3x_speaker_on(void)
562{
563#if 1
564 tlv320aic3x_index_write(0x3D, 0x3600); /*DAC Clock1 Generator Enable*/
565 tlv320aic3x_write(0x63, 0xf8de); /*LOUTMIX Power On*/
566 tlv320aic3x_write(0x61, 0x9804); /*DACL1 Power On*/
567 tlv320aic3x_write(0x62, 0x8800); /*Stereo1 DAC Digital Filter Power On*/
568 tlv320aic3x_write(0x65, 0xc800); /*OUTMIXL Power On*/
569 tlv320aic3x_write(0x66, 0x3000); /*OUTVOLL Power On*/
570 tlv320aic3x_write(0x8F, 0x3100); /*HP Deop Mode mode 2*/
571 tlv320aic3x_write(0x2A, 0x1250); /*DACL1 to Stereo DAC left Mixer*/
572 tlv320aic3x_write(0x4F, 0x0278); /*DACL1 to OUTMIXL*/
573 tlv320aic3x_write(0x52, 0x0278); /*DACR1 to OUTMIXR*/
574 tlv320aic3x_write(0x53, 0xc000); /*OUTVOLL to LOUTMIX Unmute*/
575 tlv320aic3x_write(0x03, 0x0808); /*LOUTL Unmute*/
576 tlv320aic3x_write(0x73, 0x0102); /*Stereo DAC sample Rate 128 FS*/
577 tlv320aic3x_write(0x05, 0x8000); /*enable Differential Line Output*/
578#else
579 tlv320aic3x_index_update_bits(0x3D, 1 << 10, 1 << 10); /*DAC Clock1 Generator Enable*/
580 tlv320aic3x_index_update_bits(0x3D, 1 << 9, 1 << 9); /*DAC Clock2 Generator Enable*/
581 tlv320aic3x_update_bit(0x63, 1 << 12, 1 << 12); /*LOUTMIX Power On*/
582 tlv320aic3x_update_bit(0x61, 1 << 12, 1 << 12); /*DACL1 Power On*/
583 tlv320aic3x_update_bit(0x61, 1 << 11, 1 << 11); /*DACR1 Power On*/
584 tlv320aic3x_update_bit(0x62, 1 << 11, 1 << 11); /*Stereo1 DAC Digital Filter Power On*/
585 tlv320aic3x_update_bit(0x65, 1 << 15, 1 << 15); /*OUTMIXL Power On*/
586 tlv320aic3x_update_bit(0x65, 1 << 14, 1 << 14); /*OUTMIXR Power On*/
587 tlv320aic3x_update_bit(0x66, 1 << 13, 1 << 13); /*OUTVOLL Power On*/
588 tlv320aic3x_update_bit(0x66, 1 << 12, 1 << 12); /*OUTVOLR Power On*/
589 tlv320aic3x_update_bit(0x8F, 1 << 13, 1 << 13); /*HP Deop Mode mode 2*/
590 tlv320aic3x_update_bit(0x2A, 1 << 14, 0); /*DACL1 to Stereo DAC left Mixer*/
591 tlv320aic3x_update_bit(0x2A, 1 << 1, 0); /*DACL1 to Stereo DAC Right Mixer*/
592 tlv320aic3x_update_bit(0x4F, 1, 0); /*DACL1 to OUTMIXL*/
593 tlv320aic3x_update_bit(0x52, 1, 0); /*DACR1 to OUTMIXR*/
594 tlv320aic3x_update_bit(0x53, 1 << 13, 0); /*OUTVOLL to LOUTMIX Unmute*/
595 tlv320aic3x_update_bit(0x53, 1 << 12, 0); /*OUTVOLR to LOUTMIX Unmute*/
596 tlv320aic3x_update_bit(0x03, 1 << 15, 0); /*LOUTL Unmute*/
597 tlv320aic3x_update_bit(0x03, 1 << 14, 0); /*OUTVOLL Unmute*/
598 tlv320aic3x_update_bit(0x03, 1 << 7, 0); /*LOUTR Unmute*/
599 tlv320aic3x_update_bit(0x03, 1 << 6, 0); /*OUTVOLR Unmute*/
600 tlv320aic3x_update_bit(0x73, 3 << 2, 0 << 2); /*Stereo DAC sample Rate 128 FS*/
601 tlv320aic3x_update_bit(0x05, 1 << 15, 1 << 15); /*enable Differential Line Output*/
602#endif
603}
604
605static void tlv320aic3x_speaker_off(void)
606{
607#if 1
608 tlv320aic3x_index_write(0x3D, 0x2000); /*DAC Clock1 Generator Enable*/
609 tlv320aic3x_write(0x63, 0xe8de); /*LOUTMIX Power Off*/
610 tlv320aic3x_write(0x61, 0x8000); /*DACL1 Power On*/
611 tlv320aic3x_write(0x62, 0x0000); /*Stereo1 DAC Digital Filter Power On*/
612 tlv320aic3x_write(0x65, 0x0000); /*OUTMIXL Power On*/
613 tlv320aic3x_write(0x66, 0x0000); /*OUTVOLL Power On*/
614 tlv320aic3x_write(0x8F, 0x1100); /*HP Deop Mode mode 2*/
615 tlv320aic3x_write(0x2A, 0x5250); /*DACL1 to Stereo DAC left Mixer*/
616 tlv320aic3x_write(0x4F, 0x0279); /*DACL1 to OUTMIXL*/
617 tlv320aic3x_write(0x52, 0x0279); /*DACR1 to OUTMIXR*/
618 tlv320aic3x_write(0x53, 0xf000); /*OUTVOLL to LOUTMIX Unmute*/
619 tlv320aic3x_write(0x03, 0xc8c8); /*LOUTL Unmute*/
620 tlv320aic3x_write(0x73, 0x0102); /*Stereo DAC sample Rate 128 FS*/
621 tlv320aic3x_write(0x05, 0x0000); /*disable Differential Line Output*/
622#else
623 tlv320aic3x_index_update_bits(0x3D, 1 << 10, 0); /*DAC Clock1 Generator Enable*/
624 tlv320aic3x_index_update_bits(0x3D, 1 << 9, 0); /*DAC Clock2 Generator Enable*/
625 tlv320aic3x_update_bit(0x63, 1 << 12, 0); /*LOUTMIX Power Off*/
626 tlv320aic3x_update_bit(0x61, 1 << 12, 0); /*DACL1 Power On*/
627 tlv320aic3x_update_bit(0x61, 1 << 11, 0); /*DACR1 Power On*/
628 tlv320aic3x_update_bit(0x62, 1 << 11, 0); /*Stereo1 DAC Digital Filter Power On*/
629 tlv320aic3x_update_bit(0x65, 1 << 15, 0); /*OUTMIXL Power On*/
630 tlv320aic3x_update_bit(0x65, 1 << 14, 0); /*OUTMIXR Power On*/
631 tlv320aic3x_update_bit(0x66, 1 << 13, 0); /*OUTVOLL Power On*/
632 tlv320aic3x_update_bit(0x66, 1 << 12, 0); /*OUTVOLR Power On*/
633 tlv320aic3x_update_bit(0x8F, 1 << 13, 0); /*HP Deop Mode mode 2*/
634 tlv320aic3x_update_bit(0x2A, 1 << 14, 1 << 14); /*DACL1 to Stereo DAC left Mixer*/
635 tlv320aic3x_update_bit(0x2A, 1 << 6, 1 << 6); /*DACR1 to Stereo DAC Right Mixer*/
636 tlv320aic3x_update_bit(0x4F, 1, 1); /*DACL1 to OUTMIXL*/
637 tlv320aic3x_update_bit(0x52, 1, 1); /*DACR1 to OUTMIXR*/
638 tlv320aic3x_update_bit(0x53, 1 << 13, 1 << 13); /*OUTVOLL to LOUTMIX Unmute*/
639 tlv320aic3x_update_bit(0x53, 1 << 12, 1 << 12); /*OUTVOLR to LOUTMIX Unmute*/
640 tlv320aic3x_update_bit(0x03, 1 << 15, 1 << 15); /*LOUTL Unmute*/
641 tlv320aic3x_update_bit(0x03, 1 << 14, 1 << 14); /*OUTVOLL Unmute*/
642 tlv320aic3x_update_bit(0x03, 1 << 7, 1 << 7); /*LOUTR Unmute*/
643 tlv320aic3x_update_bit(0x03, 1 << 6, 1 << 6); /*OUTVOLR Unmute*/
644 tlv320aic3x_update_bit(0x73, 3 << 2, 0 << 2); /*Stereo DAC sample Rate 128 FS*/
645 tlv320aic3x_update_bit(0x05, 1 << 15, 0 << 15); /*disable Differential Line Output*/
646#endif
647}
648
649static void tlv320aic3x_headphone_on(void)
650{
651#if 1
652 tlv320aic3x_index_write(0x3D, 0x3600); /*DAC Clock1 Generator Enable*/
653 tlv320aic3x_write(0x61, 0x9804); /*DACL1 Power On*/
654 tlv320aic3x_write(0x62, 0x8800); /*Stereo1 DAC Digital Filter Power On*/
655 tlv320aic3x_write(0x65, 0xcc00); /*OUTMIXL Power On*/
656 tlv320aic3x_write(0x66, 0x0c00); /*HPOVOLL Power On*/
657 tlv320aic3x_write(0x8E, 0x001d); /*Enable Headphone Output*/
658 tlv320aic3x_write(0x8F, 0x3100); /*HP Deop Mode mode 2*/
659 tlv320aic3x_write(0x2A, 0x1250); /*DACL1 to Stereo DAC left Mixer*/
660 tlv320aic3x_write(0x4F, 0x0278); /*DACL1 to OUTMIXL*/
661 tlv320aic3x_write(0x52, 0x0278); /*DACR1 to OUTMIXR*/
662 tlv320aic3x_write(0x45, 0x5000); /*HPOVOL to HPOMIX Unmute*/
663 tlv320aic3x_write(0x02, 0x0808); /*HPOL UnMute*/
664 tlv320aic3x_write(0x73, 0x0102); /*Stereo DAC sample Rate 128 FS*/
665
666#else
667 tlv320aic3x_index_update_bits(0x3D, 1 << 10, 1 << 10); /*DAC Clock1 Generator Enable*/
668 tlv320aic3x_index_update_bits(0x3D, 1 << 9, 1 << 9); /*DAC Clock2 Generator Enable*/
669 tlv320aic3x_update_bit(0x61, 1 << 12, 1 << 12); /*DACL1 Power On*/
670 tlv320aic3x_update_bit(0x61, 1 << 11, 1 << 11); /*DACR1 Power On*/
671 tlv320aic3x_update_bit(0x62, 1 << 11, 1 << 11); /*Stereo1 DAC Digital Filter Power On*/
672 tlv320aic3x_update_bit(0x65, 1 << 15, 1 << 15); /*OUTMIXL Power On*/
673 tlv320aic3x_update_bit(0x65, 1 << 14, 1 << 14); /*OUTMIXR Power On*/
674 tlv320aic3x_update_bit(0x66, 1 << 11, 1 << 11); /*HPOVOLL Power On*/
675 tlv320aic3x_update_bit(0x66, 1 << 10, 1 << 10); /*HPOVOLR Power On*/
676 tlv320aic3x_update_bit(0x8E, 1 << 4, 1 << 4); /*Enable Headphone Output*/
677 tlv320aic3x_update_bit(0x8E, 1, 1); /*HP Amp All Power On*/
678 tlv320aic3x_update_bit(0x8F, 1 << 13, 1 << 13); /*HP Deop Mode mode 2*/
679 tlv320aic3x_update_bit(0x2A, 1 << 14, 0); /*DACL1 to Stereo DAC left Mixer*/
680 tlv320aic3x_update_bit(0x2A, 1 << 1, 0); /*DACL1 to Stereo DAC Right Mixer*/
681 tlv320aic3x_update_bit(0x4F, 1, 0); /*DACL1 to OUTMIXL*/
682 tlv320aic3x_update_bit(0x52, 1, 0); /*DACR1 to OUTMIXR*/
683 tlv320aic3x_update_bit(0x45, 1 << 13, 0); /*HPOVOL to HPOMIX Unmute*/
684 tlv320aic3x_update_bit(0x02, 1 << 15, 0); /*HPOL UnMute*/
685 tlv320aic3x_update_bit(0x02, 1 << 14, 0); /*HPOVOLL Unmute*/
686 tlv320aic3x_update_bit(0x02, 1 << 7, 0); /*HPOR UnMute*/
687 tlv320aic3x_update_bit(0x02, 1 << 6, 0); /*HPOVOLR Unmute*/
688 tlv320aic3x_update_bit(0x73, 3 << 2, 0 << 2); /*Stereo DAC sample Rate 128 FS*/
689
690#endif
691}
692
693static void tlv320aic3x_headphone_off(void)
694{
695#if 1
696 tlv320aic3x_index_write(0x3D, 0x2000); /*DAC Clock1 Generator Enable*/
697 tlv320aic3x_write(0x61, 0x8000); /*DACL1 Power On*/
698 tlv320aic3x_write(0x62, 0x0000); /*Stereo1 DAC Digital Filter Power On*/
699 tlv320aic3x_write(0x65, 0x0000); /*OUTMIXL Power On*/
700 tlv320aic3x_write(0x66, 0x0000); /*HPOVOLL Power On*/
701 tlv320aic3x_write(0x8E, 0x000c); /*Enable Headphone Output*/
702 tlv320aic3x_write(0x8F, 0x1100); /*HP Deop Mode mode 2*/
703 tlv320aic3x_write(0x2A, 0x5252); /*DACR1 to Stereo DAC left Mixer*/
704 tlv320aic3x_write(0x4F, 0x0279); /*DACL1 to OUTMIXL*/
705 tlv320aic3x_write(0x52, 0x0279); /*DACR1 to OUTMIXR*/
706 tlv320aic3x_write(0x45, 0x7000); /*HPOVOL to HPOMIX Unmute*/
707 tlv320aic3x_write(0x02, 0xc8c8); /*HPOL UnMute*/
708 tlv320aic3x_write(0x73, 0x0102); /*Stereo DAC sample Rate 128 FS*/
709#else
710 tlv320aic3x_index_update_bits(0x3D, 1 << 10, 0); /*DAC Clock1 Generator Enable*/
711 tlv320aic3x_index_update_bits(0x3D, 1 << 9, 0); /*DAC Clock2 Generator Enable*/
712 tlv320aic3x_update_bit(0x61, 1 << 12, 0); /*DACL1 Power On*/
713 tlv320aic3x_update_bit(0x61, 1 << 11, 0); /*DACR1 Power On*/
714 tlv320aic3x_update_bit(0x62, 1 << 11, 0); /*Stereo1 DAC Digital Filter Power On*/
715 tlv320aic3x_update_bit(0x65, 1 << 15, 0); /*OUTMIXL Power On*/
716 tlv320aic3x_update_bit(0x65, 1 << 14, 0); /*OUTMIXR Power On*/
717 tlv320aic3x_update_bit(0x66, 1 << 11, 0); /*HPOVOLL Power On*/
718 tlv320aic3x_update_bit(0x66, 1 << 10, 0); /*HPOVOLR Power On*/
719 tlv320aic3x_update_bit(0x8E, 1 << 4, 0); /*Enable Headphone Output*/
720 tlv320aic3x_update_bit(0x8E, 1, 0); /*HP Amp All Power On*/
721 tlv320aic3x_update_bit(0x8F, 1 << 13, 0); /*HP Deop Mode mode 2*/
722 tlv320aic3x_update_bit(0x2A, 1 << 14, 1 << 14); /*DACR1 to Stereo DAC left Mixer*/
723 tlv320aic3x_update_bit(0x2A, 1 << 1, 1 << 1); /*DACL1 to Stereo DAC Right Mixer*/
724 tlv320aic3x_update_bit(0x4F, 1, 1); /*DACL1 to OUTMIXL*/
725 tlv320aic3x_update_bit(0x52, 1, 1); /*DACR1 to OUTMIXR*/
726 tlv320aic3x_update_bit(0x45, 1 << 13, 1 << 13); /*HPOVOL to HPOMIX Unmute*/
727 tlv320aic3x_update_bit(0x02, 1 << 15, 1 << 15); /*HPOL UnMute*/
728 tlv320aic3x_update_bit(0x02, 1 << 14, 1 << 14); /*HPOVOLL Unmute*/
729 tlv320aic3x_update_bit(0x02, 1 << 7, 1 << 7); /*HPOR UnMute*/
730 tlv320aic3x_update_bit(0x02, 1 << 6, 1 << 6); /*HPOVOLR Unmute*/
731 tlv320aic3x_update_bit(0x73, 3 << 2, 0 << 2); /*Stereo DAC sample Rate 128 FS*/
732#endif
733}
734
735static void tlv320aic3x_main_mic_on(void)
736{
737#if 1
738 tlv320aic3x_index_write(0x3D, 0x3600); /*ADC Clock Genaral Enable*/
739 tlv320aic3x_write(0x65, 0xc800); /*RECMIXL Power On*/
740 tlv320aic3x_write(0x61, 0x9804); /*ADCL Power On*/
741 tlv320aic3x_write(0x62, 0x8800); /*Stereo ADC Digital Filter Power On*/
742 tlv320aic3x_write(0x64, 0x4a00); /*BST2 Power On*/
743 tlv320aic3x_write(0x0D, 0x0540); /*IN2 Boost Control +40dB*/
744 tlv320aic3x_write(0x73, 0x0102); /*Stereo ADC Over Sample Rate 32 Fs*/
745 tlv320aic3x_write(0x3C, 0x006b); /*BST2 to RECMIXL Unmute*/
746 tlv320aic3x_write(0x3E, 0x006b); /*BST1 to RECMIXR Unmute*/
747 tlv320aic3x_write(0x27, 0x3860); /*Stereo ADC1 Left Channel Unmute*/
748#else
749 tlv320aic3x_index_update_bits(0x3D, 1 << 12, 1 << 12); /*ADC Clock Genaral Enable*/
750 tlv320aic3x_update_bit(0x65, 1 << 11, 1 << 11); /*RECMIXL Power On*/
751 tlv320aic3x_update_bit(0x61, 1 << 2, 1 << 2); /*ADCL Power On*/
752 tlv320aic3x_update_bit(0x62, 1 << 15, 1 << 15); /*Stereo ADC Digital Filter Power On*/
753 tlv320aic3x_update_bit(0x64, 1 << 14, 1 << 14); /*BST2 Power On*/
754 tlv320aic3x_update_bit(0x0D, 0xF << 8, 5 << 8); /*IN2 Boost Control +40dB*/
755 tlv320aic3x_update_bit(0x0D, 1 << 6, 1 << 6); /*IN2 Differential Mode*/
756 tlv320aic3x_update_bit(0x73, 3, 2); /*Stereo ADC Over Sample Rate 32 Fs*/
757 tlv320aic3x_update_bit(0x3C, 1 << 2, 0); /*BST2 to RECMIXL Unmute*/
758 tlv320aic3x_update_bit(0x3E, 1 << 2, 0); /*BST1 to RECMIXR Unmute*/
759 tlv320aic3x_update_bit(0x27, 1 << 14, 0); /*Stereo ADC1 Left Channel Unmute*/
760#endif
761}
762
763static void tlv320aic3x_main_mic_off(void)
764{
765#if 1
766 tlv320aic3x_index_write(0x3D, 0x2000); /*ADC Clock Genaral Enable*/
767 tlv320aic3x_write(0x65, 0x0000); /*RECMIXL Power On*/
768 tlv320aic3x_write(0x61, 0x8000); /*ADCL Power On*/
769 tlv320aic3x_write(0x62, 0x0000); /*Stereo ADC Digital Filter Power On*/
770 tlv320aic3x_write(0x64, 0x0a00); /*BST2 Power On*/
771 tlv320aic3x_write(0x0D, 0x0000); /*IN2 Boost Control +40dB*/
772 tlv320aic3x_write(0x73, 0x0102); /*Stereo ADC Over Sample Rate 128 Fs*/
773 tlv320aic3x_write(0x3C, 0x006f); /*BST2 to RECMIXL Unmute*/
774 tlv320aic3x_write(0x3E, 0x006f); /*BST2 to RECMIXL Unmute*/
775 tlv320aic3x_write(0x27, 0x7860); /*Stereo ADC1 Left Channel Unmute*/
776#else
777 tlv320aic3x_index_update_bits(0x3D, 1 << 12, 0); /*ADC Clock Genaral Enable*/
778 tlv320aic3x_update_bit(0x65, 1 << 11, 0); /*RECMIXL Power On*/
779 tlv320aic3x_update_bit(0x61, 1 << 2, 0); /*ADCL Power On*/
780 tlv320aic3x_update_bit(0x62, 1 << 15, 0); /*Stereo ADC Digital Filter Power On*/
781 tlv320aic3x_update_bit(0x64, 1 << 14, 0); /*BST2 Power On*/
782 tlv320aic3x_update_bit(0x0D, 0xF << 8, 0); /*IN2 Boost Control +40dB*/
783 tlv320aic3x_update_bit(0x0D, 1 << 6, 0); /*IN2 Differential Mode*/
784 tlv320aic3x_update_bit(0x73, 3, 2); /*Stereo ADC Over Sample Rate 128 Fs*/
785 tlv320aic3x_update_bit(0x3C, 1 << 2, 1 << 2); /*BST2 to RECMIXL Unmute*/
786 tlv320aic3x_update_bit(0x3E, 1 << 2, 1 << 2); /*BST2 to RECMIXL Unmute*/
787 tlv320aic3x_update_bit(0x27, 1 << 14, 1 << 14); /*Stereo ADC1 Left Channel Unmute*/
788#endif
789}
790
791static void tlv320aic3x_headset_mic_on(void)
792{
793#if 1
794 tlv320aic3x_index_write(0x3D, 0x3600); /*ADC Clock Genaral Enable*/
795 tlv320aic3x_write(0x65, 0xcc00); /*RECMIXL Power On*/
796 tlv320aic3x_write(0x61, 0x9804); /*ADCL Power On*/
797 tlv320aic3x_write(0x62, 0x8800); /*Stereo ADC Digital Filter Power On*/
798 tlv320aic3x_write(0x0D, 0x5000); /*IN1 Boost Control +40dB*/
799 tlv320aic3x_write(0x64, 0x4a04); /*BST1 Power On*/
800 tlv320aic3x_write(0x73, 0x0102); /*Stereo ADC Over Sample Rate 128 Fs*/
801 tlv320aic3x_write(0x3C, 0x006D); /*BST1 to RECMIXL Unmute*/
802 tlv320aic3x_write(0x3E, 0x006D); /*BST1 to RECMIXR Unmute*/
803 tlv320aic3x_write(0x27, 0x3820); /*Stereo ADC1 Left Channel Unmute*/
804#else
805 tlv320aic3x_index_update_bits(0x3D, 1 << 12, 1 << 12); /*ADC Clock Genaral Enable*/
806 tlv320aic3x_update_bit(0x65, 1 << 11, 1 << 11); /*RECMIXL Power On*/
807 tlv320aic3x_update_bit(0x65, 1 << 10, 1 << 10); /*RECMIXR Power On*/
808 tlv320aic3x_update_bit(0x61, 1 << 2, 1 << 2); /*ADCL Power On*/
809 tlv320aic3x_update_bit(0x61, 1 << 1, 1 << 1); /*ADCR Power On*/
810 tlv320aic3x_update_bit(0x62, 1 << 15, 1 << 15); /*Stereo ADC Digital Filter Power On*/
811 tlv320aic3x_update_bit(0x0D, 0xF << 12, 5 << 12); /*IN1 Boost Control +40dB*/
812 tlv320aic3x_update_bit(0x64, 1 << 15, 0 << 15); /*BST1 Power On*/
813 tlv320aic3x_update_bit(0x64, 1 << 4, 1 << 4); /*MIC2 SE Mode single-end mode*/
814 tlv320aic3x_update_bit(0x73, 3, 2); /*Stereo ADC Over Sample Rate 128 Fs*/
815 tlv320aic3x_update_bit(0x3C, 1 << 1, 0); /*BST1 to RECMIXL Unmute*/
816 tlv320aic3x_update_bit(0x3E, 1 << 1, 0); /*BST1 to RECMIXR Unmute*/
817 tlv320aic3x_update_bit(0x27, 1 << 14, 0); /*Stereo ADC1 Left Channel Unmute*/
818 tlv320aic3x_update_bit(0x27, 1 << 6, 0); /*Stereo ADC1 Right Channel Unmute*/
819#endif
820}
821
822static void tlv320aic3x_headset_mic_off(void)
823{
824#if 1
825 tlv320aic3x_index_write(0x3D, 0x2000); /*ADC Clock Genaral Enable*/
826 tlv320aic3x_write(0x65, 0x0000); /*recmixl power on*/
827 tlv320aic3x_write(0x61, 0x8000); /*adcl power on*/
828 tlv320aic3x_write(0x62, 0x0000); /*stereo adc digital filter power on*/
829 tlv320aic3x_write(0x0d, 0x0540); /*in1 boost control +40db*/
830 tlv320aic3x_write(0x64, 0x4a00); /*bst1 power on*/
831 tlv320aic3x_write(0x73, 0x0102); /*stereo adc over sample rate 128 fs*/
832 tlv320aic3x_write(0x3c, 0x006b); /*bst1 to recmixl unmute*/
833 tlv320aic3x_write(0x3e, 0x006b); /*bst1 to recmixr unmute*/
834 tlv320aic3x_write(0x27, 0x7860); /*stereo adc1 left channel unmute*/
835#else
836 tlv320aic3x_index_update_bits(0x3D, 1 << 12, 0); /*ADC Clock Genaral Enable*/
837 tlv320aic3x_update_bit(0x65, 1 << 11, 0); /*RECMIXL Power On*/
838 tlv320aic3x_update_bit(0x65, 1 << 10, 0); /*RECMIXR Power On*/
839 tlv320aic3x_update_bit(0x61, 1 << 2, 0); /*ADCL Power On*/
840 tlv320aic3x_update_bit(0x61, 1 << 1, 0); /*ADCR Power On*/
841 tlv320aic3x_update_bit(0x62, 1 << 15, 0); /*Stereo ADC Digital Filter Power On*/
842 tlv320aic3x_update_bit(0x0D, 0xF << 12, 0); /*IN1 Boost Control +40dB*/
843 tlv320aic3x_update_bit(0x64, 1 << 15, 0); /*BST1 Power On*/
844 tlv320aic3x_update_bit(0x64, 1 << 4, 0); /*MIC2 SE Mode single-end mode*/
845 tlv320aic3x_update_bit(0x73, 3, 2); /*Stereo ADC Over Sample Rate 128 Fs*/
846 tlv320aic3x_update_bit(0x3C, 1 << 1, 1 << 1); /*BST1 to RECMIXL Unmute*/
847 tlv320aic3x_update_bit(0x3E, 1 << 1, 1 << 1); /*BST1 to RECMIXR Unmute*/
848 tlv320aic3x_update_bit(0x27, 1 << 14, 1 << 14); /*Stereo ADC1 Left Channel Unmute*/
849 tlv320aic3x_update_bit(0x27, 1 << 6, 1 << 6); /*Stereo ADC1 Right Channel Unmute*/
850#endif
851}
852
853void tlv320aic3x_mute_mic(int mute)
854{
855#if 1
856 if (mute) {
857 tlv320aic3x_write(0x1c, 0xafaf);
858 } else {
859 tlv320aic3x_write(0x1c, 0x2f2f);
860 }
861#else
862 if (mute) {
863 tlv320aic3x_update_bit(0x1c, (1 << 15), (1 << 15));
864 tlv320aic3x_update_bit(0x1c, (1 << 7), (1 << 7));
865 } else {
866 tlv320aic3x_update_bit(0x1c, (1 << 15), (0 << 15));
867 tlv320aic3x_update_bit(0x1c, (1 << 7), (0 << 7));
868 }
869#endif
870 return;
871}
872 /*volume level: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 */
873int gain_output_ctrl[11] = { 0x0A, 0x09, 0x08, 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00};
874int gain_digital_vol[11] = { 0xAFAF, 0xB7B7, 0xBFBF, 0xC7C7, 0xCFCF, 0xD7D7, 0xDDDD, 0xE5E5, 0xEDED, 0xF5F5, 0xFFFF};
875
876void tlv320aic3x_adjust_gain(int gain)
877{
878 /* gain is within 0~10 */
879#if 1
880 tlv320aic3x_update_bit(0x02, (0x3F << 8), (gain_output_ctrl[gain] << 8));/* Headphone output control */
881 tlv320aic3x_update_bit(0x02, (0x3F << 0), (gain_output_ctrl[gain] << 0));
882
883 tlv320aic3x_update_bit(0x03, (0x3F << 8), (gain_output_ctrl[gain] << 8));/* Line Output Control 1 */
884 tlv320aic3x_update_bit(0x03, (0x3F << 0), (gain_output_ctrl[gain] << 0));
885
886 tlv320aic3x_write(0x19, gain_digital_vol[gain]); /* DACL1/R1 Digital Volume */
887#else
888 tlv320aic3x_update_bit(0x02, (0x3F << 8), (gain_output_ctrl[gain] << 8));/* Headphone output control */
889 tlv320aic3x_update_bit(0x02, (0x3F << 0), (gain_output_ctrl[gain] << 0));
890
891 tlv320aic3x_update_bit(0x03, (0x3F << 8), (gain_output_ctrl[gain] << 8));/* Line Output Control 1 */
892 tlv320aic3x_update_bit(0x03, (0x3F << 0), (gain_output_ctrl[gain] << 0));
893
894 tlv320aic3x_write(0x19, gain_digital_vol[gain]); /* DACL1/R1 Digital Volume */
895#endif
896 return;
897}
898
899void tlv320aic3x_check_HS_mic(void)
900{
901 /* Enable MICBIAS1 Short Current Detector, Threshold:1500uA */
902 tlv320aic3x_update_bit(0x93, (7 << 9), (5 << 9));
903 return;
904}
905
906#define tlv320aic3x_speaker_on_REG_GROUP_NUM 23
907static struct reg_value_group tlv320aic3x_speaker_on_reg_group[] = {
908 {0x3D, 1 << 10, 1 << 10}, /*DAC Clock1 Generator Enable*/
909 {0x3D, 1 << 9, 1 << 9}, /*DAC Clock2 Generator Enable*/
910 {0x63, 1 << 12, 1 << 12}, /*LOUTMIX Power On*/
911 {0x61, 1 << 12, 1 << 12}, /*DACL1 Power On*/
912 {0x61, 1 << 11, 1 << 11}, /*DACR1 Power On*/
913 {0x62, 1 << 11, 1 << 11}, /*Stereo1 DAC Digital Filter Power On*/
914 {0x65, 1 << 15, 1 << 15}, /*OUTMIXL Power On*/
915 {0x65, 1 << 14, 1 << 14}, /*OUTMIXR Power On*/
916 {0x66, 1 << 13, 1 << 13}, /*OUTVOLL Power On*/
917 {0x66, 1 << 12, 1 << 12}, /*OUTVOLR Power On*/
918 {0x8F, 1 << 13, 1 << 13}, /*HP Deop Mode mode 2*/
919 {0x2A, 1 << 14, 0}, /*DACL1 to Stereo DAC left Mixer*/
920 {0x2A, 1 << 1, 0}, /*DACL1 to Stereo DAC Right Mixer*/
921 {0x4F, 1, 0}, /*DACL1 to OUTMIXL*/
922 {0x52, 1, 0}, /*DACR1 to OUTMIXR*/
923 {0x53, 1 << 13, 0}, /*OUTVOLL to LOUTMIX Unmute*/
924 {0x53, 1 << 12, 0}, /*OUTVOLR to LOUTMIX Unmute*/
925 {0x03, 1 << 15, 0}, /*LOUTL Unmute*/
926 {0x03, 1 << 14, 0}, /*OUTVOLL Unmute*/
927 {0x03, 1 << 7, 0}, /*LOUTR Unmute*/
928 {0x03, 1 << 6, 0}, /*OUTVOLR Unmute*/
929 {0x73, 3 << 2, 0 << 2}, /*Stereo DAC sample Rate 128 FS*/
930 {0x05, 1 << 15, 1 << 15}, /*enable Differential Line Output*/
931};
932
933#define TLV320AIC3X_SPEAKER_OFF_REG_GROUP_NUM 23
934static struct reg_value_group TLV320AIC3X_speaker_off_reg_group[] = {
935 {0x3D, 1 << 10, 0}, /*DAC Clock1 Generator Enable*/
936 {0x3D, 1 << 9, 0}, /*DAC Clock2 Generator Enable*/
937 {0x63, 1 << 12, 0}, /*LOUTMIX Power Off*/
938 {0x61, 1 << 12, 0}, /*DACL1 Power On*/
939 {0x61, 1 << 11, 0}, /*DACR1 Power On*/
940 {0x62, 1 << 11, 0}, /*Stereo1 DAC Digital Filter Power On*/
941 {0x65, 1 << 15, 0}, /*OUTMIXL Power On*/
942 {0x65, 1 << 14, 0}, /*OUTMIXR Power On*/
943 {0x66, 1 << 13, 0}, /*OUTVOLL Power On*/
944 {0x66, 1 << 12, 0}, /*OUTVOLR Power On*/
945 {0x8F, 1 << 13, 0}, /*HP Deop Mode mode 2*/
946 {0x2A, 1 << 14, 1 << 14}, /*DACL1 to Stereo DAC left Mixer*/
947 {0x2A, 1 << 6, 1 << 6}, /*DACR1 to Stereo DAC Right Mixer*/
948 {0x4F, 1, 1}, /*DACL1 to OUTMIXL*/
949 {0x52, 1, 1}, /*DACR1 to OUTMIXR*/
950 {0x53, 1 << 13, 1 << 13}, /*OUTVOLL to LOUTMIX Unmute*/
951 {0x53, 1 << 12, 1 << 12}, /*OUTVOLR to LOUTMIX Unmute*/
952 {0x03, 1 << 15, 1 << 15}, /*LOUTL Unmute*/
953 {0x03, 1 << 14, 1 << 14}, /*OUTVOLL Unmute*/
954 {0x03, 1 << 7, 1 << 7}, /*LOUTR Unmute*/
955 {0x03, 1 << 6, 1 << 6}, /*OUTVOLR Unmute*/
956 {0x73, 3 << 2, 0 << 2}, /*Stereo DAC sample Rate 128 FS*/
957 {0x05, 1 << 15, 0 << 15}, /*disable Differential Line Output*/
958};
959
960#define tlv320aic3x_headphone_on_REG_GROUP_NUM 22
961static struct reg_value_group tlv320aic3x_headphone_on_reg_group[] = {
962 {0x3D, 1 << 10, 1 << 10}, /*DAC Clock1 Generator Enable*/
963 {0x3D, 1 << 9, 1 << 9}, /*DAC Clock2 Generator Enable*/
964 {0x61, 1 << 12, 1 << 12}, /*DACL1 Power On*/
965 {0x61, 1 << 11, 1 << 11}, /*DACR1 Power On*/
966 {0x62, 1 << 11, 1 << 11}, /*Stereo1 DAC Digital Filter Power On*/
967 {0x65, 1 << 15, 1 << 15}, /*OUTMIXL Power On*/
968 {0x65, 1 << 14, 1 << 14}, /*OUTMIXR Power On*/
969 {0x66, 1 << 11, 1 << 11}, /*HPOVOLL Power On*/
970 {0x66, 1 << 10, 1 << 10}, /*HPOVOLR Power On*/
971 {0x8E, 1 << 4, 1 << 4}, /*Enable Headphone Output*/
972 {0x8E, 1, 1}, /*HP Amp All Power On*/
973 {0x8F, 1 << 13, 1 << 13}, /*HP Deop Mode mode 2*/
974 {0x2A, 1 << 14, 0}, /*DACL1 to Stereo DAC left Mixer*/
975 {0x2A, 1 << 1, 0}, /*DACL1 to Stereo DAC Right Mixer*/
976 {0x4F, 1, 0}, /*DACL1 to OUTMIXL*/
977 {0x52, 1, 0}, /*DACR1 to OUTMIXR*/
978 {0x45, 1 << 13, 0}, /*HPOVOL to HPOMIX Unmute*/
979 {0x02, 1 << 15, 0}, /*HPOL UnMute*/
980 {0x02, 1 << 14, 0}, /*HPOVOLL Unmute*/
981 {0x02, 1 << 7, 0}, /*HPOR UnMute*/
982 {0x02, 1 << 6, 0}, /*HPOVOLR Unmute*/
983 {0x73, 3 << 2, 0 << 2}, /*Stereo DAC sample Rate 128 FS*/
984};
985
986#define TLV320AIC3X_HEADPHONE_OFF_REG_GROUP_NUM 22
987static struct reg_value_group TLV320AIC3X_headphone_off_reg_group[] = {
988 {0x3D, 1 << 10, 0}, /*DAC Clock1 Generator Enable*/
989 {0x3D, 1 << 9, 0}, /*DAC Clock2 Generator Enable*/
990 {0x61, 1 << 12, 0}, /*DACL1 Power On*/
991 {0x61, 1 << 11, 0}, /*DACR1 Power On*/
992 {0x62, 1 << 11, 0}, /*Stereo1 DAC Digital Filter Power On*/
993 {0x65, 1 << 15, 0}, /*OUTMIXL Power On*/
994 {0x65, 1 << 14, 0}, /*OUTMIXR Power On*/
995 {0x66, 1 << 11, 0}, /*HPOVOLL Power On*/
996 {0x66, 1 << 10, 0}, /*HPOVOLR Power On*/
997 {0x8E, 1 << 4, 0}, /*Enable Headphone Output*/
998 {0x8E, 1, 0}, /*HP Amp All Power On*/
999 {0x8F, 1 << 13, 0}, /*HP Deop Mode mode 2*/
1000 {0x2A, 1 << 14, 1 << 14}, /*DACR1 to Stereo DAC left Mixer*/
1001 {0x2A, 1 << 1, 1 << 1}, /*DACL1 to Stereo DAC Right Mixer*/
1002 {0x4F, 1, 1}, /*DACL1 to OUTMIXL*/
1003 {0x52, 1, 1}, /*DACR1 to OUTMIXR*/
1004 {0x45, 1 << 13, 1 << 13}, /*HPOVOL to HPOMIX Unmute*/
1005 {0x02, 1 << 15, 1 << 15}, /*HPOL UnMute*/
1006 {0x02, 1 << 14, 1 << 14}, /*HPOVOLL Unmute*/
1007 {0x02, 1 << 7, 1 << 7}, /*HPOR UnMute*/
1008 {0x02, 1 << 6, 1 << 6}, /*HPOVOLR Unmute*/
1009 {0x73, 3 << 2, 0 << 2}, /*Stereo DAC sample Rate 128 FS*/
1010};
1011
1012#define tlv320aic3x_main_mic_on_REG_GROUP_NUM 11
1013static struct reg_value_group tlv320aic3x_main_mic_on_reg_group[] = {
1014 {0x3D, 1 << 12, 1 << 12}, /*ADC Clock Genaral Enable*/
1015 {0x65, 1 << 11, 1 << 11}, /*RECMIXL Power On*/
1016 {0x61, 1 << 2, 1 << 2}, /*ADCL Power On*/
1017 {0x62, 1 << 15, 1 << 15}, /*Stereo ADC Digital Filter Power On*/
1018 {0x64, 1 << 14, 1 << 14}, /*BST2 Power On*/
1019 {0x0D, 0xF << 8, 5 << 8}, /*IN2 Boost Control +40dB*/
1020 {0x0D, 1 << 6, 1 << 6}, /*IN2 Differential Mode*/
1021 {0x73, 3, 2}, /*Stereo ADC Over Sample Rate 32 Fs*/
1022 {0x3C, 1 << 2, 0}, /*BST2 to RECMIXL Unmute*/
1023 {0x3E, 1 << 2, 0}, /*BST1 to RECMIXR Unmute*/
1024 {0x27, 1 << 14, 0}, /*Stereo ADC1 Left Channel Unmute*/
1025};
1026static struct reg_value_group tlv320aic3x_main_mic_on_reg_group_singlemode[] = {
1027 {0x3D, 1 << 12, 1 << 12}, /*ADC Clock Genaral Enable*/
1028 {0x65, 1 << 11, 1 << 11}, /*RECMIXL Power On*/
1029 {0x61, 1 << 2, 1 << 2}, /*ADCL Power On*/
1030 {0x62, 1 << 15, 1 << 15}, /*Stereo ADC Digital Filter Power On*/
1031 {0x64, 1 << 14, 1 << 14}, /*BST2 Power On*/
1032 {0x0D, 0xF << 8, 5 << 8}, /*IN2 Boost Control +40dB*/
1033 {0x0D, 1 << 6, 0}, /*IN2 Single Mode*/
1034 {0x73, 3, 2}, /*Stereo ADC Over Sample Rate 32 Fs*/
1035 {0x3C, 1 << 2, 0}, /*BST2 to RECMIXL Unmute*/
1036 {0x3E, 1 << 2, 0}, /*BST1 to RECMIXR Unmute*/
1037 {0x27, 1 << 14, 0}, /*Stereo ADC1 Left Channel Unmute*/
1038};
1039
1040
1041
1042#define TLV320AIC3X_MAIN_MIC_OFF_REG_GROUP_NUM 11
1043static struct reg_value_group TLV320AIC3X_main_mic_off_reg_group[] = {
1044 {0x3D, 1 << 12, 0}, /*ADC Clock Genaral Enable*/
1045 {0x65, 1 << 11, 0}, /*RECMIXL Power On*/
1046 {0x61, 1 << 2, 0}, /*ADCL Power On*/
1047 {0x62, 1 << 15, 0}, /*Stereo ADC Digital Filter Power On*/
1048 {0x64, 1 << 14, 0}, /*BST2 Power On*/
1049 {0x0D, 0xF << 8, 0}, /*IN2 Boost Control +40dB*/
1050 {0x0D, 1 << 6, 0}, /*IN2 Differential Mode*/
1051 {0x73, 3, 2}, /*Stereo ADC Over Sample Rate 128 Fs*/
1052 {0x3C, 1 << 2, 1 << 2}, /*BST2 to RECMIXL Unmute*/
1053 {0x3E, 1 << 2, 1 << 2}, /*BST2 to RECMIXL Unmute*/
1054 {0x27, 1 << 14, 1 << 14}, /*Stereo ADC1 Left Channel Unmute*/
1055};
1056
1057#define tlv320aic3x_headset_mic_on_REG_GROUP_NUM 14
1058static struct reg_value_group tlv320aic3x_headset_mic_on_reg_group[] = {
1059 {0x3D, 1 << 12, 1 << 12}, /*ADC Clock Genaral Enable*/
1060 {0x65, 1 << 11, 1 << 11}, /*RECMIXL Power On*/
1061 {0x65, 1 << 10, 1 << 10}, /*RECMIXR Power On*/
1062 {0x61, 1 << 2, 1 << 2}, /*ADCL Power On*/
1063 {0x61, 1 << 1, 1 << 1}, /*ADCR Power On*/
1064 {0x62, 1 << 15, 1 << 15}, /*Stereo ADC Digital Filter Power On*/
1065 {0x0D, 0xF << 12, 5 << 12}, /*IN1 Boost Control +40dB*/
1066 {0x64, 1 << 15, 0 << 15}, /*BST1 Power On*/
1067 {0x64, 1 << 4, 1 << 4}, /*MIC2 SE Mode single-end mode*/
1068 {0x73, 3, 2}, /*Stereo ADC Over Sample Rate 128 Fs*/
1069 {0x3C, 1 << 1, 0}, /*BST1 to RECMIXL Unmute*/
1070 {0x3E, 1 << 1, 0}, /*BST1 to RECMIXR Unmute*/
1071 {0x27, 1 << 14, 0}, /*Stereo ADC1 Left Channel Unmute*/
1072 {0x27, 1 << 6, 0}, /*Stereo ADC1 Right Channel Unmute*/
1073};
1074
1075#define TLV320AIC3X_HEADSET_MIC_OFF_REG_GROUP_NUM 14
1076static struct reg_value_group TLV320AIC3X_headset_mic_off_reg_group[] = {
1077 {0x3D, 1 << 12, 0}, /*ADC Clock Genaral Enable*/
1078 {0x65, 1 << 11, 0}, /*RECMIXL Power On*/
1079 {0x65, 1 << 10, 0}, /*RECMIXR Power On*/
1080 {0x61, 1 << 2, 0}, /*ADCL Power On*/
1081 {0x61, 1 << 1, 0}, /*ADCR Power On*/
1082 {0x62, 1 << 15, 0}, /*Stereo ADC Digital Filter Power On*/
1083 {0x0D, 0xF << 12, 0}, /*IN1 Boost Control +40dB*/
1084 {0x64, 1 << 15, 0}, /*BST1 Power On*/
1085 {0x64, 1 << 4, 0}, /*MIC2 SE Mode single-end mode*/
1086 {0x73, 3, 2}, /*Stereo ADC Over Sample Rate 128 Fs*/
1087 {0x3C, 1 << 1, 1 << 1}, /*BST1 to RECMIXL Unmute*/
1088 {0x3E, 1 << 1, 1 << 1}, /*BST1 to RECMIXR Unmute*/
1089 {0x27, 1 << 14, 1 << 14}, /*Stereo ADC1 Left Channel Unmute*/
1090 {0x27, 1 << 6, 1 << 6}, /*Stereo ADC1 Right Channel Unmute*/
1091};
1092/////////////////////////////////////////////////////////////////////////////////
1093
1094#define TLV320AIC3X_HEADSET_DETECT_ON_REG_GROUP_NUM 3
1095static struct reg_value_group TLV320AIC3X_headset_detect_on_reg_group[] = {
1096 {0x64, 1 << 2, 1 << 2}, /*JD1 Multilevel Power on*/
1097 {0xC0, 1 << 15, 1 << 15}, /*GPIO1 Pin as IRQ output*/
1098 {0xBD, 7 << 7, 4 << 7}, /*jd1_1, jd1_1_stricky disable, Polarity Normal*/
1099};
1100
1101#define TLV320AIC3X_HEADSET_DETECT_OFF_REG_GROUP_NUM 3
1102static struct reg_value_group TLV320AIC3X_headset_detect_off_reg_group[] = {
1103 {0x64, 1 << 2, 0 << 2}, /*JD1 Multilevel Power off*/
1104 {0xC0, 1 << 15, 0 << 15}, /*GPIO1 Pin as IRQ output*/
1105 {0xBD, 7 << 7, 0 << 7}, /*jd1_1, jd1_1_stricky disable, Polarity Normal*/
1106};
1107
1108
1109int tlv320aic3x_reg_dump(void)
1110{
1111 unsigned char index;
1112 unsigned short value;
1113 int status = -1;
1114
1115 printk(KERN_INFO"tlv320aic3x_reg_dump_enter\n");
1116 for (index = 0; index < 0xFF; index++)
1117 {
1118 // if (tlv320aic3x_readable_register(index))
1119 // {
1120 status = tlv320aic3x_read(index, &value);
1121 if (status != 0)
1122 {
1123 printk(KERN_INFO"status: 0x%x\n", status);
1124 return -1;
1125 }
1126 printk(KERN_INFO"index: 0x%x, value: 0x%x\n", index, value);
1127 // }
1128 }
1129
1130 return 0;
1131}
1132
1133/*
1134 I2S1 BCLK Polarity Invert
1135 I2S1 PCM Mode A
1136 */
1137static void TLV320AIC3X_set_dai_fmt(char enable)
1138{
1139#if 0
1140 if (TLV320AIC3X_DEVICE_ON == enable)
1141 {
1142 if(0 == G_AudioModemMaster){
1143 /* GSSP is slave, tlv320aic3x is master */
1144 tlv320aic3x_write(0x70, 0x0082);
1145 } else {
1146 /* GSSP is master, tlv320aic3x is slave */
1147 tlv320aic3x_write(0x70, 0x8082);
1148 }
1149 }
1150 else if (TLV320AIC3X_DEVICE_OFF == enable)
1151 {
1152 if(0 == G_AudioModemMaster){
1153 /* GSSP is slave, tlv320aic3x is master */
1154 tlv320aic3x_write(0x70, 0x0000);
1155 } else {
1156 /* GSSP is master, tlv320aic3x is slave */
1157 tlv320aic3x_write(0x70, 0x8000);
1158 }
1159 }
1160#else
1161 if (TLV320AIC3X_DEVICE_ON == enable)
1162 {
1163 tlv320aic3x_update_bit(0x70, (1 << 7) | 3, (1 << 7) | 2);
1164 if(0 == G_AudioModemMaster){// gssp slave, tlv320aic3x master
1165 tlv320aic3x_update_bit(0x70, (1 << 15) , (0 << 15) );// set tlv320aic3x master
1166 }
1167 }
1168 else if (TLV320AIC3X_DEVICE_OFF == enable)
1169 {
1170 tlv320aic3x_update_bit(0x70, (1 << 7) | 3, 0);
1171 }
1172#endif
1173}
1174
1175/*FS = bitrate = 8K
1176 BCLK = 512K = 64FS , 0x73
1177 FOUT = (sysclk * (N + 2)) / ((M + 2) / (K + 2))
1178 SYSCLK = PLL = 26M
1179 FOUT = (26 * 34) / (9 * 4) = 24.555
1180 CLK = FOUT / 12 = 2048K = 256 * FS
1181 */
1182static void tlv320aic3x_set_sysclk(char enable)
1183{
1184#if 1
1185 if (TLV320AIC3X_DEVICE_ON == enable)
1186 {
1187 tlv320aic3x_write(0xFA, 0x0001); /*Enable MCLK Input*/
1188 tlv320aic3x_write(0x73, 0x0002); /*DAC Over Sample Rate: 128Fs, ADC Over Sample Rate: 32Fs*/
1189 if (3 == Audio_Codec_Fsync_Rate)
1190 {
1191 printk(KERN_INFO"%s, sys clock comes from PLL when Fsync = 48K.\n", __FUNCTION__);
1192 tlv320aic3x_update_bit(0x64, 1 << 9, 1 << 9); /*PLL Power On*/
1193 tlv320aic3x_update_bit(0x73, 7 << 12, 1 << 12); /*sel_i2s_pre_div1 = 1/2*/
1194 }
1195 }
1196 else if (TLV320AIC3X_DEVICE_OFF == enable)
1197 {
1198 tlv320aic3x_write(0xFA, 0x0000); /*Disable MCLK Input*/
1199 if (3 == Audio_Codec_Fsync_Rate)
1200 {
1201 printk(KERN_INFO"%s, sys clock comes from PLL when Fsync = 48K.\n", __FUNCTION__);
1202 tlv320aic3x_update_bit(0x64, 1 << 9, 0); /*PLL Power Off*/
1203 }
1204 }
1205#else
1206 int bclk_type = BCLK_256_FS;
1207
1208 if (TLV320AIC3X_DEVICE_ON == enable)
1209 {
1210 tlv320aic3x_update_bit(0xFA, 1, 1); /*Enable MCLK Input*/
1211 tlv320aic3x_update_bit(0x64, 1 << 9, 1 << 9); /*PLL Power On*/
1212
1213 tlv320aic3x_update_bit(0x73, 3 << 2, 0 << 2); /*128Fs*/
1214 tlv320aic3x_update_bit(0x73, 3, 2); /*32Fs*/
1215
1216 if(1 == g_tlv320aic3x_mclk_type){/*use I2S_SYSCLK as MCLK , 2.048M/4.096M*/
1217 tlv320aic3x_update_bit(0x73, 7 << 12, 0 << 12); /*I2S Clock Pre-Divider = 0 for divide 1*/
1218 }
1219 else if(0 == g_tlv320aic3x_mclk_type){//using bitclk as tlv320aic3x mclk
1220 tlv320aic3x_update_bit(0x73, 7 << 12, 0 << 12); /*I2S Clock Pre-Divider = 0 for divide 1*/
1221 tlv320aic3x_update_bit(0x80, 3 << 14, 1 << 14); /*System Clock from PLL*/
1222 tlv320aic3x_update_bit(0x80, 3 << 12, 1 << 12); /*PLL from bclk*/
1223 tlv320aic3x_update_bit(0x82, 1 << 11, 1 << 11); /*PLL M bypass */
1224
1225 if(BCLK_64_FS == bclk_type){ // 64fs
1226 tlv320aic3x_update_bit(0x81, 0x1FF << 7 , 6 << 7);/*PLL K = 0,PLL N = 6*/
1227 }
1228 else if(BCLK_128_FS == bclk_type){// 128fs
1229 tlv320aic3x_update_bit(0x81, 0x1FF << 7 , 2 << 7);/*PLL K = 0,PLL N = 2*/
1230 }
1231 else if(BCLK_256_FS == bclk_type){// 256fs
1232 tlv320aic3x_update_bit(0x81, 0x1FF << 7 , 0 << 7);/*PLL K = 0,PLL N = 0*/
1233 }
1234 else if(BCLK_32_FS == bclk_type){// 32fs
1235 tlv320aic3x_update_bit(0x81, 0x1FF << 7 , 14 << 7);/*PLL K = 0,PLL N = 14*/
1236 }
1237
1238 }
1239 }
1240 else if (TLV320AIC3X_DEVICE_OFF == enable)
1241 {
1242 tlv320aic3x_update_bit(0xFA, 1, 0); /*disable MCLK Input*/
1243 tlv320aic3x_update_bit(0x64, 1 << 9, 0); /*PLL Power off*/
1244 }
1245#endif
1246}
1247
1248static void TLV320AIC3X_set_sys_power(char enable)
1249{
1250 if (TLV320AIC3X_DEVICE_ON == enable)
1251 {
1252 tlv320aic3x_update_bit(0x63, 1 << 11, 1 << 11); /*MICBIAS Bandgap Power On*/
1253 tlv320aic3x_update_bit(0x63, 1 << 15, 1 << 15); /*VREF1 Power On*/
1254 tlv320aic3x_update_bit(0x63, 1 << 14, 1 << 14); /*VREF Slow*/
1255 tlv320aic3x_update_bit(0x63, 1 << 4, 1 << 4); /*VREF2 Power On*/
1256 tlv320aic3x_update_bit(0x63, 1 << 3, 1 << 3); /*VREF2 Slow*/
1257 tlv320aic3x_update_bit(0x63, 1 << 13, 1 << 13); /*MBIAS Power On*/
1258 tlv320aic3x_update_bit(0x61, 1 << 15, 1 << 15); /*I2S Power On*/
1259 tlv320aic3x_update_bit(0x8E, 1 << 3, 1 << 3); /*Charge Pump Power On*/
1260 tlv320aic3x_update_bit(0x64, 1 << 11, 1 << 11); /*MICBIAS1 Power On*/
1261 }
1262 else if (TLV320AIC3X_DEVICE_OFF == enable)
1263 {
1264 tlv320aic3x_update_bit(0x63, 1 << 11, 0); /*MICBIAS Bandgap Power Off*/
1265 tlv320aic3x_update_bit(0x63, 1 << 15, 0); /*VREF1 Power Off*/
1266 tlv320aic3x_update_bit(0x63, 1 << 14, 0); /*VREF Slow*/
1267 tlv320aic3x_update_bit(0x63, 1 << 4, 0); /*VREF2 Power Off*/
1268 tlv320aic3x_update_bit(0x63, 1 << 3, 0); /*VREF2 Slow*/
1269 tlv320aic3x_update_bit(0x63, 1 << 13, 0); /*MBIAS Power Off*/
1270 tlv320aic3x_update_bit(0x61, 1 << 15, 0); /*I2S Power Off*/
1271 tlv320aic3x_update_bit(0x8E, 1 << 3, 0); /*Charge Pump Power Off*/
1272 tlv320aic3x_update_bit(0x64, 1 << 11, 0); /*MICBIAS1 Power Off*/
1273 }
1274}
1275
1276static void TLV320AIC3X_device_enable(char device, char enable)
1277{
1278 int length;
1279 int index;
1280 struct reg_value_group *reg_group = NULL;
1281
1282 if ((device == TLV320AIC3X_OUTPUT_DEVICE_SPEAKER) && (enable == TLV320AIC3X_DEVICE_ON))
1283 {
1284 reg_group = tlv320aic3x_speaker_on_reg_group;
1285 length = tlv320aic3x_speaker_on_REG_GROUP_NUM;
1286 }
1287 else if ((device == TLV320AIC3X_OUTPUT_DEVICE_SPEAKER) && (enable == TLV320AIC3X_DEVICE_OFF))
1288 {
1289 reg_group = TLV320AIC3X_speaker_off_reg_group;
1290 length = TLV320AIC3X_SPEAKER_OFF_REG_GROUP_NUM;
1291 }
1292 else if ((device == TLV320AIC3X_OUTPUT_DEVICE_HEADPHONE) && (enable == TLV320AIC3X_DEVICE_ON))
1293 {
1294 reg_group = tlv320aic3x_headphone_on_reg_group;
1295 length = tlv320aic3x_headphone_on_REG_GROUP_NUM;
1296 }
1297 else if ((device == TLV320AIC3X_OUTPUT_DEVICE_HEADPHONE) && (enable == TLV320AIC3X_DEVICE_OFF))
1298 {
1299 reg_group = TLV320AIC3X_headphone_off_reg_group;
1300 length = TLV320AIC3X_HEADPHONE_OFF_REG_GROUP_NUM;
1301 }
1302 else if ((device == TLV320AIC3X_INPUT_DEVICE_MAIN_MIC) && (enable == TLV320AIC3X_DEVICE_ON))
1303 {
1304 if(g_tlv320aic3xmainmic_type == 0)
1305 reg_group = tlv320aic3x_main_mic_on_reg_group;
1306 else
1307 reg_group = tlv320aic3x_main_mic_on_reg_group_singlemode;
1308 length = tlv320aic3x_main_mic_on_REG_GROUP_NUM;
1309 }
1310 else if ((device == TLV320AIC3X_INPUT_DEVICE_MAIN_MIC) && (enable == TLV320AIC3X_DEVICE_OFF))
1311 {
1312 reg_group = TLV320AIC3X_main_mic_off_reg_group;
1313 length = TLV320AIC3X_MAIN_MIC_OFF_REG_GROUP_NUM;
1314 }
1315 else if ((device == TLV320AIC3X_INPUT_DEVICE_HEADSET_MIC) && (enable == TLV320AIC3X_DEVICE_ON))
1316 {
1317 reg_group = tlv320aic3x_headset_mic_on_reg_group;
1318 length = tlv320aic3x_headset_mic_on_REG_GROUP_NUM;
1319 }
1320 else if ((device == TLV320AIC3X_INPUT_DEVICE_HEADSET_MIC) && (enable == TLV320AIC3X_DEVICE_OFF))
1321 {
1322 reg_group = TLV320AIC3X_headset_mic_off_reg_group;
1323 length = TLV320AIC3X_HEADSET_MIC_OFF_REG_GROUP_NUM;
1324 }
1325 else if ((device == TLV320AIC3X_INPUT_DEVICE_HEADSET_DETECT) && (enable == TLV320AIC3X_DEVICE_ON))
1326 {
1327 reg_group = TLV320AIC3X_headset_detect_on_reg_group;
1328 length = TLV320AIC3X_HEADSET_DETECT_ON_REG_GROUP_NUM;
1329 }
1330 else if ((device == TLV320AIC3X_INPUT_DEVICE_HEADSET_DETECT) && (enable == TLV320AIC3X_DEVICE_OFF))
1331 {
1332 reg_group = TLV320AIC3X_headset_detect_off_reg_group;
1333 length = TLV320AIC3X_HEADSET_DETECT_OFF_REG_GROUP_NUM;
1334 }
1335
1336 if (reg_group == NULL)
1337 return;
1338
1339 if (enable == TLV320AIC3X_DEVICE_ON)
1340 {
1341 for (index = 0; index < length; index++)
1342 {
1343 if (reg_group[index].reg != 0x3D)
1344 tlv320aic3x_update_bit(reg_group[index].reg, reg_group[index].mask, reg_group[index].value);
1345 else
1346 tlv320aic3x_index_update_bits(reg_group[index].reg, reg_group[index].mask, reg_group[index].value);
1347 }
1348 TLV320AIC3X_set_work_state(device, enable);
1349 //printk(KERN_INFO"device enabled:%e{TLV320AIC3X_DEVICE}", device);
1350 }
1351 else if (enable == TLV320AIC3X_DEVICE_OFF)
1352 {
1353 for (index = 0; index < length; index++)
1354 {
1355 if (reg_group[index].reg != 0x3D)
1356 tlv320aic3x_update_bit(reg_group[index].reg, reg_group[index].mask, reg_group[index].value);
1357 else
1358 tlv320aic3x_index_update_bits(reg_group[index].reg, reg_group[index].mask, reg_group[index].value);
1359 }
1360 TLV320AIC3X_set_work_state(device, enable);
1361 //printk(KERN_INFO"device disabled:%e{TLV320AIC3X_DEVICE}", device);
1362 }
1363}
1364
1365static void TLV320AIC3X_speaker_enable(char enable)
1366{
1367#ifdef RECONFIGURE_POWER_INCALL
1368 TLV320AIC3X_set_dai_fmt(enable);
1369 tlv320aic3x_set_sysclk(enable);
1370 TLV320AIC3X_set_sys_power(enable);
1371#endif
1372 TLV320AIC3X_device_enable(TLV320AIC3X_OUTPUT_DEVICE_SPEAKER, enable);
1373 return;
1374}
1375
1376static void TLV320AIC3X_headphone_enable(char enable)
1377{
1378#ifdef RECONFIGURE_POWER_INCALL
1379 TLV320AIC3X_set_dai_fmt(enable);
1380 tlv320aic3x_set_sysclk(enable);
1381 TLV320AIC3X_set_sys_power(enable);
1382#endif
1383
1384 TLV320AIC3X_device_enable(TLV320AIC3X_OUTPUT_DEVICE_HEADPHONE, enable);
1385 return;
1386}
1387
1388static void TLV320AIC3X_main_mic_enable(char enable)
1389{
1390#ifdef RECONFIGURE_POWER_INCALL
1391 TLV320AIC3X_set_dai_fmt(enable);
1392 tlv320aic3x_set_sysclk(enable);
1393 TLV320AIC3X_set_sys_power(enable);
1394#endif
1395
1396 TLV320AIC3X_device_enable(TLV320AIC3X_INPUT_DEVICE_MAIN_MIC, enable);
1397 return;
1398}
1399
1400static void TLV320AIC3X_headset_mic_enable(char enable)
1401{
1402#ifdef RECONFIGURE_POWER_INCALL
1403 TLV320AIC3X_set_dai_fmt(enable);
1404 tlv320aic3x_set_sysclk(enable);
1405 TLV320AIC3X_set_sys_power(enable);
1406#endif
1407
1408 TLV320AIC3X_device_enable(TLV320AIC3X_INPUT_DEVICE_HEADSET_MIC, enable);
1409 return;
1410}
1411
1412static void TLV320AIC3X_device_select(char device, char onoff)
1413{
1414 if (tlv320aic3x_init_ok == 0)
1415 {
1416 printk(KERN_INFO"TLV320AIC3X not init\n");
1417 return;
1418 }
1419 switch (onoff)
1420 {
1421 case TLV320AIC3X_DEVICE_ON:
1422 if (device == TLV320AIC3X_OUTPUT_DEVICE_SPEAKER)
1423 {
1424 if (is_speaker_on())
1425 {
1426 printk(KERN_INFO"already enabled\n");
1427 return;
1428 }
1429 else
1430 {
1431 if (is_headphone_on())
1432 {
1433 TLV320AIC3X_headphone_enable(TLV320AIC3X_DEVICE_OFF);
1434 }
1435 TLV320AIC3X_speaker_enable(TLV320AIC3X_DEVICE_ON);
1436 }
1437 }
1438 else if (device == TLV320AIC3X_OUTPUT_DEVICE_HEADPHONE)
1439 {
1440 if (is_headphone_on())
1441 {
1442 printk(KERN_INFO"already enabled\n");
1443 return;
1444 }
1445 else
1446 {
1447 if (is_speaker_on())
1448 {
1449 TLV320AIC3X_speaker_enable(TLV320AIC3X_DEVICE_OFF);
1450 }
1451 TLV320AIC3X_headphone_enable(TLV320AIC3X_DEVICE_ON);
1452 }
1453 }
1454 else if (device == TLV320AIC3X_INPUT_DEVICE_MAIN_MIC)
1455 {
1456 if (is_main_mic_on())
1457 {
1458 printk(KERN_INFO"already enabled\n");
1459 return;
1460 }
1461 else
1462 {
1463 if (is_headset_mic_on())
1464 {
1465 TLV320AIC3X_headset_mic_enable(TLV320AIC3X_DEVICE_OFF);
1466 }
1467 TLV320AIC3X_main_mic_enable(TLV320AIC3X_DEVICE_ON);
1468 }
1469 }
1470 else if (device == TLV320AIC3X_INPUT_DEVICE_HEADSET_MIC)
1471 {
1472 if (is_headset_mic_on())
1473 {
1474 printk(KERN_INFO"already enabled\n");
1475 return;
1476 }
1477 else
1478 {
1479 if (is_main_mic_on())
1480 {
1481 TLV320AIC3X_main_mic_enable(TLV320AIC3X_DEVICE_OFF);
1482 }
1483 TLV320AIC3X_headset_mic_enable(TLV320AIC3X_DEVICE_ON);
1484 }
1485 }
1486 break;
1487
1488 case TLV320AIC3X_DEVICE_OFF:
1489 if (device == TLV320AIC3X_OUTPUT_DEVICE_SPEAKER)
1490 {
1491 if (!is_speaker_on())
1492 {
1493 printk(KERN_INFO"already disabled\n");
1494 return;
1495 }
1496 else
1497 {
1498 TLV320AIC3X_speaker_enable(TLV320AIC3X_DEVICE_OFF);
1499 }
1500 }
1501 else if (device == TLV320AIC3X_OUTPUT_DEVICE_HEADPHONE)
1502 {
1503 if (!is_headphone_on())
1504 {
1505 printk(KERN_INFO"already disabled\n");
1506 return;
1507 }
1508 else
1509 {
1510 TLV320AIC3X_headphone_enable(TLV320AIC3X_DEVICE_OFF);
1511 }
1512 }
1513 else if (device == TLV320AIC3X_INPUT_DEVICE_MAIN_MIC)
1514 {
1515 if (!is_main_mic_on())
1516 {
1517 printk(KERN_INFO"already disabled\n");
1518 return;
1519 }
1520 else
1521 {
1522 TLV320AIC3X_main_mic_enable(TLV320AIC3X_DEVICE_OFF);
1523 }
1524 }
1525 else if (device == TLV320AIC3X_INPUT_DEVICE_HEADSET_MIC)
1526 {
1527 if (!is_headset_mic_on())
1528 {
1529 printk(KERN_INFO"already disabled\n");
1530 return;
1531 }
1532 else
1533 {
1534 TLV320AIC3X_headset_mic_enable(TLV320AIC3X_DEVICE_OFF);
1535 }
1536 }
1537
1538 if (is_speaker_on())
1539 TLV320AIC3X_speaker_enable(TLV320AIC3X_DEVICE_ON);
1540 if (is_headphone_on())
1541 TLV320AIC3X_headphone_enable(TLV320AIC3X_DEVICE_ON);
1542 if (is_main_mic_on())
1543 TLV320AIC3X_main_mic_enable(TLV320AIC3X_DEVICE_ON);
1544 if (is_headset_mic_on())
1545 TLV320AIC3X_headset_mic_enable(TLV320AIC3X_DEVICE_ON);
1546 break;
1547
1548 default:
1549 break;
1550 }
1551}
1552
1553
1554void codec_tlv320aic3x_set_headphone_gain(void)
1555{
1556#if 0
1557 // -6db
1558 tlv320aic3x_update_bit(0x45, (1 << 12), (1 << 12));
1559
1560#else
1561
1562 tlv320aic3x_write(0x45, 0x5000);
1563#endif
1564
1565 return;
1566}
1567
1568void codec_tlv320aic3x_set_headphone_mic_gain(void)
1569{
1570#if 0
1571 // +24db
1572 tlv320aic3x_update_bit(0x1c, (0x7F << 8), (0x6F << 8));
1573 tlv320aic3x_update_bit(0x1c, (0x7F << 0), (0x6F << 0));
1574
1575 // +24db: Boost will cause something like white noise in background, so just remove it.
1576 //tlv320aic3x_update_bit(0x1E, (3 << 14), (2 << 14));
1577 //tlv320aic3x_update_bit(0x1E, (3 << 12), (2 << 12));
1578#else
1579 tlv320aic3x_write(0x1c, 0x6f6f);
1580#endif
1581 return;
1582}
1583
1584void codec_TLV320AIC3X_mute_headphone(int mute)
1585{
1586 if(mute){
1587 tlv320aic3x_update_bit(0x02, (1 << 15), (1 << 15));
1588 tlv320aic3x_update_bit(0x02, (1 << 7), (1 << 7));
1589 }
1590 else{
1591 tlv320aic3x_update_bit(0x02, (1 << 15), (0 << 15));
1592 tlv320aic3x_update_bit(0x02, (1 << 7), (0 << 7));
1593 }
1594 return;
1595}
1596
1597void codec_TLV320AIC3X_mute_speaker(int mute)
1598{
1599 if(mute){
1600 tlv320aic3x_update_bit(0x03, (1 << 15), (1 << 15));
1601 tlv320aic3x_update_bit(0x03, (1 << 7), (1 << 7));
1602 }
1603 else{
1604 tlv320aic3x_update_bit(0x03, (1 << 15), (0 << 15));
1605 tlv320aic3x_update_bit(0x03, (1 << 7), (0 << 7));
1606 }
1607 return;
1608}
1609
1610void codec_TLV320AIC3X_set_speaker_mic_gain(void)
1611{
1612 // +0db
1613 tlv320aic3x_update_bit(0x1c, (0x7F << 8), (0x2F << 8));
1614 tlv320aic3x_update_bit(0x1c, (0x7F << 0), (0x2F << 0));
1615
1616 return;
1617}
1618
1619
1620void codec_tlv320aic3x_enable_headphone_main_mic(void)
1621{
1622 if(!codec_tlv320aic3x_is_connect()) {return;}
1623
1624 printk(KERN_INFO"codec_tlv320aic3x_enable_headphone_main_mic\n");
1625
1626#ifdef RECONFIGURE_POWER_INCALL
1627 enable_tlv320aic3x_MClock();
1628#endif
1629 TLV320AIC3X_device_select(TLV320AIC3X_OUTPUT_DEVICE_HEADPHONE, TLV320AIC3X_DEVICE_ON);
1630 TLV320AIC3X_device_select(TLV320AIC3X_INPUT_DEVICE_MAIN_MIC, TLV320AIC3X_DEVICE_ON);
1631 codec_tlv320aic3x_set_headphone_gain();
1632 return;
1633}
1634
1635void codec_TLV320AIC3X_enable_headphone(void)
1636{
1637 if(disableTLV320AIC3XHsMic){
1638 return codec_tlv320aic3x_enable_headphone_main_mic();
1639 }
1640
1641 if(!codec_tlv320aic3x_is_connect()) {return;}
1642
1643 printk(KERN_INFO"codec_TLV320AIC3X_enable_headphone\n");
1644#ifdef RECONFIGURE_POWER_INCALL
1645 enable_tlv320aic3x_MClock();
1646#endif
1647 TLV320AIC3X_device_select(TLV320AIC3X_OUTPUT_DEVICE_HEADPHONE, TLV320AIC3X_DEVICE_ON);
1648 TLV320AIC3X_device_select(TLV320AIC3X_INPUT_DEVICE_HEADSET_MIC, TLV320AIC3X_DEVICE_ON);
1649
1650 codec_tlv320aic3x_set_headphone_gain();
1651 codec_tlv320aic3x_set_headphone_mic_gain();
1652 return;
1653}
1654
1655void codec_TLV320AIC3X_enable_headphone_only(void)
1656{
1657 if(!codec_tlv320aic3x_is_connect()) {return;}
1658
1659 printk(KERN_INFO"codec_TLV320AIC3X_enable_headphone_only\n");
1660#ifdef RECONFIGURE_POWER_INCALL
1661 enable_tlv320aic3x_MClock();
1662#endif
1663 TLV320AIC3X_device_select(TLV320AIC3X_OUTPUT_DEVICE_HEADPHONE, TLV320AIC3X_DEVICE_ON);
1664 return;
1665}
1666
1667void codec_TLV320AIC3X_enable_main_mic_only(void)
1668{
1669 if(!codec_tlv320aic3x_is_connect()) {return;}
1670
1671 printk(KERN_INFO"codec_TLV320AIC3X_enable_main_mic_only\n");
1672#ifdef RECONFIGURE_POWER_INCALL
1673 enable_tlv320aic3x_MClock();
1674#endif
1675 TLV320AIC3X_device_select(TLV320AIC3X_INPUT_DEVICE_HEADSET_MIC, TLV320AIC3X_DEVICE_ON);
1676 return;
1677}
1678
1679void codec_TLV320AIC3X_enable_speaker(void)
1680{
1681 if(!codec_tlv320aic3x_is_connect()) {return;}
1682
1683 printk(KERN_INFO"codec_TLV320AIC3X_enable_speaker\n");
1684#ifdef RECONFIGURE_POWER_INCALL
1685 enable_tlv320aic3x_MClock();
1686#endif
1687 TLV320AIC3X_device_select(TLV320AIC3X_OUTPUT_DEVICE_SPEAKER, TLV320AIC3X_DEVICE_ON);
1688 TLV320AIC3X_device_select(TLV320AIC3X_INPUT_DEVICE_MAIN_MIC, TLV320AIC3X_DEVICE_ON);
1689
1690 codec_TLV320AIC3X_set_speaker_mic_gain();
1691 return;
1692}
1693
1694void codec_TLV320AIC3X_enable_speaker_only(void)
1695{
1696 if(!codec_tlv320aic3x_is_connect()) {return;}
1697
1698 printk(KERN_INFO"codec_TLV320AIC3X_enable_speaker_only\n");
1699 TLV320AIC3X_device_select(TLV320AIC3X_OUTPUT_DEVICE_SPEAKER, TLV320AIC3X_DEVICE_ON);
1700 return;
1701}
1702
1703void codec_TLV320AIC3X_disable_path(void)
1704{
1705 if(!codec_tlv320aic3x_is_connect()) {return;}
1706
1707 printk(KERN_INFO"codec_TLV320AIC3X_disable_path\n");
1708
1709 if(is_speaker_on()){
1710 TLV320AIC3X_device_select(TLV320AIC3X_OUTPUT_DEVICE_SPEAKER, TLV320AIC3X_DEVICE_OFF);
1711 }
1712 if(is_headphone_on()){
1713 TLV320AIC3X_device_select(TLV320AIC3X_OUTPUT_DEVICE_HEADPHONE, TLV320AIC3X_DEVICE_OFF);
1714 }
1715 if(is_main_mic_on()){
1716 TLV320AIC3X_device_select(TLV320AIC3X_INPUT_DEVICE_MAIN_MIC, TLV320AIC3X_DEVICE_OFF);
1717 }
1718 if(is_headset_mic_on()){
1719 TLV320AIC3X_device_select(TLV320AIC3X_INPUT_DEVICE_HEADSET_MIC, TLV320AIC3X_DEVICE_OFF);
1720 }
1721
1722#ifdef RECONFIGURE_POWER_INCALL
1723 disable_tlv320aic3x_MClock();
1724#endif
1725 return;
1726}
1727
1728//Kestrel/Falcon/NezhaC
1729void disable_tlv320aic3x_MClock(void)
1730{
1731 printk(KERN_INFO"disable_tlv320aic3x_MClock, g_tlv320aic3x_mclk_type=%d\n", g_tlv320aic3x_mclk_type);
1732
1733#if 0 //yjg
1734 if(g_tlv320aic3x_mclk_type){
1735 /*GPIO-20 function 0 (default), GPIO-20*/
1736 /* *(volatile unsigned long *)(SSP1_I2S_CLOCK_REG_ADDR) = 0x7820130B; *//*8k, sysclk_en = 0*/
1737 /* *(volatile unsigned long *)(MFPRX_GPIO_20) = 0xB0C0; */
1738 iounmap(i2s_clk_reg);
1739 release_mem_region(SSP1_I2S_CLOCK_REG_ADDR, 4);
1740 }
1741#endif
1742 return;
1743}
1744
1745extern char * get_MCLK_start_addr(void);
1746#ifdef CONFIG_CPU_ASR1901
1747extern int enable_pmu_audio_clk(void);
1748#endif
1749//Kestrel/Flacon/NezhaC
1750void enable_tlv320aic3x_MClock(void)
1751{
1752#ifdef TLV320AIC3X_DEBUG_CLOSE
1753 int reg_value = 0;
1754
1755 printk(KERN_INFO"enable_tlv320aic3x_MClock, g_tlv320aic3x_mclk_type=%d, Audio_Codec_Fsync_Rate=%d\n", g_tlv320aic3x_mclk_type, Audio_Codec_Fsync_Rate);
1756 printk("enable_tlv320aic3x_MClock, g_tlv320aic3x_mclk_type=%d, Audio_Codec_Fsync_Rate=%d\n", g_tlv320aic3x_mclk_type, Audio_Codec_Fsync_Rate);
1757 if (cpu_is_asr1803()) {
1758 printk(KERN_INFO"%s, platform is Falcon.\n", __FUNCTION__);
1759 } else if (cpu_is_asr1806()) {
1760 printk(KERN_INFO"%s, platform is Falcon-T.\n", __FUNCTION__);
1761 } else if (cpu_is_asr1901() || cpu_is_asr1906()) {
1762 printk(KERN_INFO"%s, platform is Kestrel.\n", __FUNCTION__);
1763 } else if (cpu_is_asr1903()) {
1764 printk(KERN_INFO"%s, platform is Lapwing.\n", __FUNCTION__);
1765 } else {
1766 printk(KERN_INFO"%s, platform is Nezhac or Nezha3.\n", __FUNCTION__);
1767 }
1768#endif
1769
1770 if (cpu_is_asr1901() || cpu_is_asr1906()) {
1771 printk(KERN_INFO"%s, platform is kestrel.\n", __FUNCTION__);
1772#ifdef Kestrel_Z2
1773 __raw_writel(0x1043, VCXO_OUT_MFPR_reg);
1774 __raw_writel(0x3, PM_MN_CLK_reg);
1775
1776 if(0 == Audio_Codec_Fsync_Rate){
1777 /* config 2.048MHz MCLK for 8KHz Fsync of PCM */
1778 __raw_writel(0x00980001, GPCR_reg);
1779 } else {
1780 /* config 4.096MHz MCLK for 16KHz Fsync of PCM */
1781 __raw_writel(0x004c0001, GPCR_reg);
1782 }
1783
1784 printk(KERN_INFO"%s, VCXO_OUT_MFPR_reg is 0x%0x, PM_MN_CLK_reg is 0x%0x, GPCR_reg is 0x%0x.\n",
1785 __FUNCTION__, *(unsigned int *)VCXO_OUT_MFPR_reg, *(unsigned int *)PM_MN_CLK_reg, *(unsigned int *)GPCR_reg);
1786
1787#else
1788 MCLK_CLK_CTRL_reg = get_MCLK_start_addr();
1789 if (NULL == MCLK_CLK_CTRL_reg) {
1790 printk(KERN_INFO"%s, MCLK_CLK_CTRL_reg is NULL.\n", __FUNCTION__, MCLK_CLK_CTRL_reg);
1791 return;
1792 }
1793
1794 MCLK_MN_DIV_reg = (char *)MCLK_CLK_CTRL_reg + 4;
1795
1796 __raw_writel(0x3, MCLK_CLK_CTRL_reg);
1797
1798 if(0 == Audio_Codec_Fsync_Rate){
1799 /* config 2.048MHz MCLK for 8KHz Fsync of PCM */
1800 printk("--->%s%d\n", __FUNCTION__, __LINE__);
1801 __raw_writel(0x004b0004, MCLK_MN_DIV_reg);
1802 } else if (1 == Audio_Codec_Fsync_Rate){
1803 /* config 4.096MHz MCLK for 16KHz Fsync of PCM */
1804 __raw_writel(0x004b0008, MCLK_MN_DIV_reg);
1805 } else if (3 == Audio_Codec_Fsync_Rate) {
1806 /* config 12.288MHz MCLK for 48KHz Fsync of PCM */
1807 //__raw_writel(0x004b0018, MCLK_MN_DIV_reg);//1.MCLK 12.288MHz direct connection
1808
1809 __raw_writel(0x000a0001, MCLK_MN_DIV_reg);//MCLK 3.84MHz for PLL and for HP detection
1810
1811 tlv320aic3x_write(0x73, 0x1002);
1812 tlv320aic3x_write(0x80, 0x4000);//2.MCLK 3.84MHz for PLL
1813 //tlv320aic3x_write(0x80, 0x5000);//3.BCLK 3.84MHz for PLL
1814 tlv320aic3x_write(0x81, 0x3F02);
1815 tlv320aic3x_write(0x82, 0x3000);
1816 } else {
1817 printk(KERN_INFO"%s, please check Audio_Codec_Fsync_Rate = %d.\n",__FUNCTION__, Audio_Codec_Fsync_Rate);
1818 }
1819
1820 printk(KERN_INFO"%s, Audio_Codec_Fsync_Rate = %d.\n",__FUNCTION__, Audio_Codec_Fsync_Rate);
1821 printk(KERN_INFO"%s, MCLK_CLK_CTRL_reg is 0x%0x, MCLK_MN_DIV_reg is 0x%0x.\n",
1822 __FUNCTION__, *(unsigned int *)MCLK_CLK_CTRL_reg, *(unsigned int *)MCLK_MN_DIV_reg);
1823#endif
1824 } else {
1825 printk(KERN_INFO"%s, platform is NezhaC, Falcon, .etc.\n", __FUNCTION__);
1826 printk("--->%s%d\n", __FUNCTION__, __LINE__);
1827 struct clk * mclk = devm_clk_get(&g_tlv320aic3x_client->dev, "i2s_sys_clk");
1828 if(IS_ERR(mclk)){
1829 printk(KERN_INFO"mclk get failed\n");
1830 return;
1831 }
1832
1833 int ret = clk_prepare_enable(mclk);
1834 if(ret){
1835 printk(KERN_INFO"mclk prepare enable failed");
1836 return;
1837 }
1838
1839 if(g_tlv320aic3x_mclk_type){
1840printk("--->%s%d\n", __FUNCTION__, __LINE__);
1841 if(0 == Audio_Codec_Fsync_Rate){
1842 /*i2s_sysclk = 2M for 8k*/
1843
1844#ifdef TLV320AIC3X_DEBUG_CLOSE
1845 reg_value = ioread32(SSP1_I2S_CLOCK_reg);
1846 //reg_value = *(volatile int*)(i2s_clk_reg);
1847 printk(KERN_INFO"read: reg_value=0x%x\n", reg_value);
1848 //printk(KERN_INFO"read: *register_address = 0x%x, reg_value=0x%x\n",
1849 //*(unsigned int *)i2s_clk_reg, reg_value);
1850#endif
1851 printk("--->%s%d\n", __FUNCTION__, __LINE__);
1852 clk_set_rate(mclk, 2048000);
1853 // clk_set_rate(mclk, 10000000);
1854 int rate = clk_get_rate(mclk);
1855 printk(KERN_INFO"mclk rate is %d", rate);
1856 printk("--->%s%d mclk rate is %d\n", __FUNCTION__, __LINE__, rate);
1857 /* write value to register */
1858 //*(volatile unsigned int *)i2s_clk_reg = 0xF820130B;
1859
1860#ifdef TLV320AIC3X_DEBUG_CLOSE
1861 /* read value from register */
1862 printk(KERN_INFO"NB, write:0xF820130B(Nezhac, Nezha3),0xE0C472D8(Falcon),*register_address = 0x%x\n", *(unsigned int *)SSP1_I2S_CLOCK_reg);
1863#endif
1864 }
1865 else{
1866 /*i2s_sysclk = 4M for 16k*/
1867
1868#ifdef TLV320AIC3X_DEBUG_CLOSE
1869 reg_value = ioread32(SSP1_I2S_CLOCK_reg);
1870 printk(KERN_INFO"read: reg_value=0x%x\n", reg_value);
1871 //printk(KERN_INFO"read: *register_address = %x\n", *(unsigned int *)i2s_clk_reg);
1872
1873 //reg_value = *(volatile int*)(i2s_clk_reg);
1874 //printk(KERN_INFO"read: *register_address = 0x%x, reg_value=0x%x\n",
1875 //*(unsigned int *)i2s_clk_reg, reg_value);
1876#endif
1877 clk_set_rate(mclk, 4096000);
1878 int rate = clk_get_rate(mclk);
1879 printk(KERN_INFO"mclk rate is %d", rate);
1880#ifdef TLV320AIC3X_DEBUG_CLOSE
1881 /* write value to register */
1882 //*(volatile unsigned int *)i2s_clk_reg = 0xF840130B;
1883
1884 /* read value from register */
1885 printk(KERN_INFO"WB, write: 0xF840130B(Nezhac, Nezha3),0xE18872D8(Falcon), *register_address = %x\n", *(unsigned int *)SSP1_I2S_CLOCK_reg);
1886#endif
1887 }
1888 }
1889 }
1890 return;
1891}
1892EXPORT_SYMBOL_GPL(enable_tlv320aic3x_MClock);
1893
1894void codec_tlv320aic3x_power_on(void)
1895{
1896 printk(KERN_INFO"codec_tlv320aic3x_power_on\n");
1897
1898 enable_tlv320aic3x_MClock();
1899 TLV320AIC3X_set_dai_fmt(1);
1900 tlv320aic3x_set_sysclk(1);
1901 TLV320AIC3X_set_sys_power(1);
1902}
1903
1904void codec_tlv320aic3x_power_off(void)
1905{
1906 printk(KERN_INFO"codec_tlv320aic3x_power_off\n");
1907
1908 TLV320AIC3X_set_dai_fmt(0);
1909 tlv320aic3x_set_sysclk(0);
1910 TLV320AIC3X_set_sys_power(0);
1911 disable_tlv320aic3x_MClock();
1912}
1913
1914void codec_tlv320aic3x_enable_headset_detect(void)
1915{
1916 if(!codec_tlv320aic3x_is_connect()) {return;}
1917
1918 printk(KERN_INFO"codec_tlv320aic3x_enable_headset_detect\n");
1919
1920 g_tlv320aic3xheadset_detection_enabled = 1;
1921 g_tlv320aic3xheadset_plugged = 0;
1922
1923 TLV320AIC3X_device_enable(TLV320AIC3X_INPUT_DEVICE_HEADSET_DETECT, 1);
1924
1925 return;
1926}
1927
1928void codec_tlv320aic3x_disable_headset_detect(void)
1929{
1930 if(!codec_tlv320aic3x_is_connect()) {return;}
1931
1932 printk(KERN_INFO"codec_tlv320aic3x_disable_headset_detect\n");
1933
1934 TLV320AIC3X_device_enable(TLV320AIC3X_INPUT_DEVICE_HEADSET_DETECT, 0);
1935
1936 g_tlv320aic3xheadset_detection_enabled = 0;
1937 return;
1938}
1939
1940/* HS Detection */
1941static struct mfd_cell headset_devs_tlv320aic3x[] = {
1942 {
1943 .name = "tlv320aic3x-headset",
1944 .id = -1,
1945 },
1946};
1947
1948static void tlv320aic3x_headset_detection_init(struct i2c_client *client)
1949{
1950 int ret = 0;
1951
1952 headset_devs_tlv320aic3x[0].platform_data = client;
1953 headset_devs_tlv320aic3x[0].pdata_size = sizeof(struct i2c_client);
1954
1955 ret = mfd_add_devices(&client->dev, 0, &headset_devs_tlv320aic3x[0],
1956 ARRAY_SIZE(headset_devs_tlv320aic3x), NULL,
1957 0,
1958 NULL);
1959 if (ret) {
1960 printk(KERN_INFO"Failed to add headset subdev\n");
1961 return;
1962 }
1963
1964 return;
1965}
1966
1967
1968void codec_tlv320aic3x_switch_headset(char on)
1969{
1970 if(on == 1)
1971 {
1972 //codec_TLV320AIC3X_disable_path();
1973 //msleep(10);
1974 //ACMSetMSAVoicePath(ATC_HEADSET);
1975
1976 codec_TLV320AIC3X_enable_headphone();
1977 }
1978 else
1979 {
1980 //codec_TLV320AIC3X_disable_path();
1981 //msleep(10);
1982
1983 //ACMSetMSAVoicePath(ATC_HANDSET);
1984 codec_TLV320AIC3X_enable_speaker();
1985 }
1986
1987 return;
1988}
1989
1990/* Headset function and report to userspace for ACM */
1991
1992void tlv320aic3x_get_headset_status(void)
1993{
1994 unsigned short value = 0;
1995 int status = -1;
1996
1997 if(!codec_tlv320aic3x_is_connect()) {return;}
1998
1999 status = tlv320aic3x_read(0xBF, &value);
2000 if(0 != status)
2001 {
2002 printk(KERN_INFO"%s: Read register [0xBF] error = 0x%x\n", __FUNCTION__, status);
2003 return;
2004 }
2005
2006 if((value & 0x3000) == 0)
2007 {/* headset plug in: bit 12 & 13 is 1 */
2008 g_tlv320aic3xheadset_plugged = 1;
2009
2010 /* Enable MICBIAS1 Short Current Detector, Threshold:1500uA */
2011 tlv320aic3x_update_bit(0x93, (7 << 9), (5 << 9));
2012
2013 /* wait mic bias stable*/
2014 mdelay(100);
2015
2016 value = 0;
2017 status = tlv320aic3x_read(0xBE, &value);
2018 if(0 != status)
2019 {
2020 printk(KERN_INFO"%s: Read register [0xBE] error = 0x%x\n", __FUNCTION__, status);
2021 return;
2022 }
2023
2024 /* MICBIAS1 Over Current status */
2025 if((1 == g_tlv320aic3xheadset_plugged) && ((value & (1 << 3)) == 0))
2026 {
2027 /* Headset with mic */
2028 g_tlv320aic3xheadset_mic = 1;
2029 printk(KERN_INFO"Headset(with mic) plugin!\n");
2030 }
2031 else if((1 == g_tlv320aic3xheadset_plugged) && ((value & (1 << 3)) != 0))
2032 {
2033 /* Headset without mic */
2034 g_tlv320aic3xheadset_mic = 0;
2035 printk(KERN_INFO"Headset(without mic) plugin!\n");
2036 }
2037 }
2038 else if((value & 0x3000) == 0x3000)
2039 {/* headset plug out: bit 12 & 13 is 0 */
2040 g_tlv320aic3xheadset_plugged = 0;
2041 g_tlv320aic3xheadset_mic = 0;
2042
2043 /* Disable MICBIAS1 Short Current Detector */
2044 tlv320aic3x_update_bit(0x93, (7 << 9), (0 << 9));
2045
2046 printk(KERN_INFO"Headset plugout!\n");
2047 }
2048
2049 return;
2050}
2051
2052
2053int tlv320aic3x_get_headset_mic_status(void)
2054{
2055 return g_tlv320aic3xheadset_mic;
2056}
2057EXPORT_SYMBOL_GPL(tlv320aic3x_get_headset_mic_status);
2058
2059int tlv320aic3x_get_headset_plugged_status(void)
2060{
2061 return g_tlv320aic3xheadset_plugged;
2062}
2063EXPORT_SYMBOL_GPL(tlv320aic3x_get_headset_plugged_status);
2064
2065void codec_tlv320aic3x_clear_headset_status(void)
2066{
2067 if(!codec_tlv320aic3x_is_connect()) {return;}
2068
2069 printk(KERN_INFO"codec_tlv320aic3x_clear_headset_status\n");
2070
2071 tlv320aic3x_write(0xBF, 0);
2072 return;
2073}
2074
2075void codec_tlv320aic3x_use_bitclk(void)
2076{
2077 printk(KERN_INFO"codec_tlv320aic3x_use_bitclk\n");
2078 g_tlv320aic3x_mclk_type = 0;
2079 return;
2080}
2081
2082void codec_tlv320aic3x_use_bitclk_with_mclk_on(void)
2083{
2084 printk(KERN_INFO"codec_tlv320aic3x_use_bitclk_with_mclk_on\n");
2085 g_tlv320aic3x_mclk_type = 2;
2086 return;
2087}
2088
2089void codec_tlv320aic3x_set_mainmic_singlemode(void)
2090{
2091 printk(KERN_INFO"codec_tlv320aic3x_set_mainmic_singlemode\n");
2092 g_tlv320aic3xmainmic_type = 1;
2093 return;
2094}
2095
2096void tlv320aic3x_Enable_Headsetdetection(void)
2097{
2098 /* Init headset detection for tlv320aic3x */
2099 if(codec_tlv320aic3x_is_connect() && (g_tlv320aic3xheadset_detection_enabled == 0))
2100 {
2101 codec_tlv320aic3x_enable_headset_detect();
2102 }
2103}
2104EXPORT_SYMBOL_GPL(tlv320aic3x_Enable_Headsetdetection);
2105
2106void tlv320aic3x_Disable_Headsetdetection(void)
2107{
2108 /* Init headset detection for tlv320aic3x */
2109 if(codec_tlv320aic3x_is_connect() && (g_tlv320aic3xheadset_detection_enabled == 1))
2110 {
2111 codec_tlv320aic3x_disable_headset_detect();
2112 }
2113}
2114EXPORT_SYMBOL_GPL(tlv320aic3x_Disable_Headsetdetection);
2115
2116void codec_tlv320aic3x_dump(void)
2117{
2118 tlv320aic3x_reg_dump();
2119}
2120
2121/* debug fs for tlv320aic3x register interface of read and write. */
2122static int reg_tlv320aic3x = 0xffff;
2123struct dentry *tlv320aic3x_dump_reg = NULL;
2124
2125static ssize_t tlv320aic3x_dump_read(struct file *file, char __user *user_buf,
2126 size_t count, loff_t *ppos)
2127{
2128 unsigned short reg_val = 0;
2129 unsigned short out_val = 0;
2130 int i;
2131 int len = 0;
2132 unsigned char str[255] = {0};
2133
2134 if (reg_tlv320aic3x == 0xffff)
2135 {
2136 len = snprintf(str, sizeof(str) - 1, "%s\n",
2137 "tlv320aic3x: register dump:");
2138 for (i = 0; i < tlv320aic3x_reg_NUM; i++)
2139 {
2140
2141 reg_val = tlv320aic3x_read(i, &out_val);
2142 pr_info("%s: [0x%02x]=0x%02x\n", __FUNCTION__, i, out_val);
2143 }
2144
2145 }
2146 else
2147 {
2148 reg_val = tlv320aic3x_read(reg_tlv320aic3x, &out_val);
2149 len = snprintf(str, sizeof(str), "reg_tlv320aic3x=0x%02x, val=0x%04x\n",
2150 reg_tlv320aic3x, out_val);
2151 printk(KERN_INFO"%s:%s\n", __FUNCTION__, str);
2152
2153 }
2154
2155 return 0;
2156}
2157
2158/*
2159 read example:
2160 echo 0x90 > /sys/kernel/debug/tlv320aic3x_reg
2161 cat /sys/kernel/debug/tlv320aic3x_reg
2162 read all register:
2163 echo + > /sys/kernel/debug/tlv320aic3x_reg
2164 cat /sys/kernel/debug/tlv320aic3x_reg
2165 write example: echo 0x90 0x10 > /sys/kernel/debug/tlv320aic3x_reg
2166
2167 read register example:
2168 echo 0x3F > /sys/kernel/debug/tlv320aic3x_reg
2169 cat /sys/kernel/debug/tlv320aic3x_reg
2170
2171 read all registers example:
2172 echo + > /sys/kernel/debug/tlv320aic3x_reg
2173 cat /sys/kernel/debug/tlv320aic3x_reg
2174
2175 config Gain example:
2176 echo 0xFF 0x00 > /sys/kernel/debug/tlv320aic3x_reg
2177 echo 0xFF 0x01 > /sys/kernel/debug/tlv320aic3x_reg
2178 echo 0xFF 0x02 > /sys/kernel/debug/tlv320aic3x_reg
2179 echo 0xFF 0x03 > /sys/kernel/debug/tlv320aic3x_reg
2180 echo 0xFF 0x04 > /sys/kernel/debug/tlv320aic3x_reg
2181 echo 0xFF 0x05 > /sys/kernel/debug/tlv320aic3x_reg
2182 echo 0xFF 0x06 > /sys/kernel/debug/tlv320aic3x_reg
2183 echo 0xFF 0x07 > /sys/kernel/debug/tlv320aic3x_reg
2184 cat /sys/kernel/debug/tlv320aic3x_reg
2185
2186 write the register example:
2187 echo 0x2C 0x01 > /sys/kernel/debug/tlv320aic3x_reg
2188 cat /sys/kernel/debug/tlv320aic3x_reg
2189 */
2190static ssize_t tlv320aic3x_dump_write(struct file *file,
2191 const char __user *user_buf,
2192 size_t count, loff_t *ppos)
2193{
2194 int reg_val;
2195 //struct pm80x_chip *chip = file->private_data;
2196 int i = 0;
2197 int ret;
2198
2199 char messages[20];
2200 memset(messages, '\0', 20);
2201
2202 if (copy_from_user(messages, user_buf, count))
2203 return -EFAULT;
2204
2205 if ('+' == messages[0]) {
2206 /* enable to get all the reg value */
2207 reg_tlv320aic3x = 0xffff;
2208 pr_info("%s: read all reg enabled!\n", __FUNCTION__);
2209 } else {
2210 if (messages[1] != 'x') {
2211 pr_err("Right format: 0x[addr]\n");
2212 return -EINVAL;
2213 }
2214
2215 if (strlen(messages) > 5) {
2216 while (messages[i] != ' ')
2217 i++;
2218 messages[i] = '\0';
2219 if (kstrtouint(messages, 16, &reg_tlv320aic3x) < 0)
2220 return -EINVAL;
2221 i++;
2222 if (kstrtouint(messages + i, 16, &reg_val) < 0)
2223 return -EINVAL;
2224
2225 {
2226 /* config the registers */
2227 ret = tlv320aic3x_write(reg_tlv320aic3x, reg_val & 0xffff);
2228 if (ret < 0) {
2229 pr_err("write reg error!\n");
2230 return -EINVAL;
2231 }
2232
2233 printk(KERN_INFO"%s/L%d: addr=0x%02x, val=0x%04x.\n", __FUNCTION__, __LINE__, reg_tlv320aic3x, reg_val);
2234
2235 }
2236
2237 } else {
2238 /* point out the register address for read. */
2239 if (kstrtouint(messages, 16, &reg_tlv320aic3x) < 0)
2240 return -EINVAL;
2241 }
2242 }
2243
2244 return count;
2245}
2246
2247static const struct file_operations tlv320aic3x_dump_ops = {
2248 .open = simple_open,
2249 .read = tlv320aic3x_dump_read,
2250 .write = tlv320aic3x_dump_write,
2251};
2252
2253static inline int tlv320aic3x_dump_debugfs_init(struct pm80x_chip *chip)
2254{
2255
2256 tlv320aic3x_dump_reg = debugfs_create_file("tlv320aic3x_dump_reg", S_IRUGO | S_IFREG,
2257 NULL, NULL, &tlv320aic3x_dump_ops);
2258
2259 if (tlv320aic3x_dump_reg == NULL) {
2260 pr_err("create tlv320aic3x debugfs error!\n");
2261 return -ENOENT;
2262 } else if (tlv320aic3x_dump_reg == ERR_PTR(-ENODEV)) {
2263 pr_err("CONFIG_DEBUG_FS is not enabled!\n");
2264 return -ENOENT;
2265 }
2266
2267 return 0;
2268}
2269
2270static void tlv320aic3x_dump_debugfs_remove(struct pm80x_chip *chip)
2271{
2272 if (NULL != tlv320aic3x_dump_reg){
2273 debugfs_remove_recursive(tlv320aic3x_dump_reg);
2274 }
2275
2276 return;
2277}
2278
2279
2280
2281/* debug fs for tlv320aic3x audio control of Earphone, speaker or HS... */
2282
2283struct dentry *tlv320aic3x_audio_control = NULL;
2284
2285static ssize_t tlv320aic3x_audio_read(struct file *file, char __user *user_buf,
2286 size_t count, loff_t *ppos)
2287{
2288
2289#ifdef TLV320AIC3X_DEBUG
2290 printk(KERN_INFO"%s/L%d.\n", __FUNCTION__, __LINE__);
2291#endif
2292 return 0;
2293
2294}
2295
2296/*
22971:enable earphone, enable MIC1
22982:disable earphone, enable MIC1
2299
23003:enable speaker, enable MIC1
23014:disable speaker, enable MIC1
2302
23035:enable Headphone, enable HSMIC
23046:disable Headphone, enable HSMIC
2305control command:
2306enable earphone and MIC1: echo 1 > /sys/kernel/debug/tlv320aic3x_audio
2307disable earphone and MIC1: echo 2 > /sys/kernel/debug/tlv320aic3x_audio
2308
2309enable speaker and MIC1: echo 3 > /sys/kernel/debug/tlv320aic3x_audio
2310disable speaker and MIC1: echo 4 > /sys/kernel/debug/tlv320aic3x_audio
2311
2312enable Headphone and HSMIC echo 5 > /sys/kernel/debug/tlv320aic3x_audio
2313disable Headphone and HSMIC echo 6 > /sys/kernel/debug/tlv320aic3x_audio
2314 */
2315static char msg[10];
2316
2317static ssize_t tlv320aic3x_audio_write(struct file *file,
2318 const char __user *user_buf,
2319 size_t count, loff_t *ppos)
2320{
2321 int ret = 0;
2322 size_t tmp_count = 0;
2323
2324 printk(KERN_INFO"%s/L%d.\n", __FUNCTION__, __LINE__);
2325
2326 memset(msg, 0x00, sizeof(msg));
2327 tmp_count = count;
2328
2329 if (tmp_count >= sizeof(msg)){
2330 tmp_count = sizeof(msg) - 1;
2331 }
2332
2333 /* copy the content from user space to kernel space */
2334 ret = copy_from_user(msg, user_buf, tmp_count);
2335 if (ret){
2336 printk(KERN_ALERT"copy from user fail \n");
2337 return -EFAULT;
2338 }
2339
2340 switch (msg[0]){
2341 case '1':/* input command# echo 1 > /sys/kernel/debug/tlv320aic3x_audio */
2342 printk(KERN_INFO "input %c. \n", msg[0]);
2343 tlv320aic3x_check_HS_mic();
2344 break;
2345
2346 case '2':/* input command# echo 2 > /sys/kernel/debug/tlv320aic3x_audio */
2347 printk(KERN_INFO "input %c. \n", msg[0]);
2348 enable_tlv320aic3x_MClock();
2349 tlv320aic3x_speaker_off();
2350 tlv320aic3x_main_mic_off();
2351 break;
2352
2353 case '3':/* input command# echo 3 > /sys/kernel/debug/tlv320aic3x_audio */
2354 printk(KERN_INFO "input %c. \n", msg[0]);
2355 enable_tlv320aic3x_MClock();
2356 tlv320aic3x_headphone_on();
2357 tlv320aic3x_headset_mic_on();
2358 break;
2359
2360 case '4':/* input command# echo 4 > /sys/kernel/debug/tlv320aic3x_audio */
2361 printk(KERN_INFO "input %c. \n", msg[0]);
2362 codec_tlv320aic3x_enable_headset_detect();
2363 break;
2364
2365 case '5':/* input command# echo 5 > /sys/kernel/debug/tlv320aic3x_audio */
2366 printk(KERN_INFO "input %c. \n", msg[0]);
2367 enable_tlv320aic3x_MClock();
2368 tlv320aic3x_headphone_off();
2369 tlv320aic3x_headset_mic_off();
2370 break;
2371
2372 case '6':/* input command# echo 6 > /sys/kernel/debug/tlv320aic3x_audio */
2373 printk(KERN_INFO "input %c. \n", msg[0]);
2374 tlv320aic3x_mute_mic(1);
2375 break;
2376
2377 case '7':/* input command# echo 7 > /sys/kernel/debug/tlv320aic3x_audio */
2378 enable_tlv320aic3x_MClock();
2379 tlv320aic3x_speaker_on();
2380 tlv320aic3x_main_mic_on();
2381 break;
2382
2383 case '8':/* input command# echo 8 > /sys/kernel/debug/tlv320aic3x_audio */
2384 enable_tlv320aic3x_MClock();
2385 tlv320aic3x_speaker_off();
2386 tlv320aic3x_main_mic_off();
2387 break;
2388
2389 case '9':/* input command# echo 9 > /sys/kernel/debug/tlv320aic3x_audio */
2390 enable_tlv320aic3x_MClock();
2391 codec_tlv320aic3x_enable_headphone_main_mic();
2392 break;
2393
2394 default:/* input command# */
2395 printk(KERN_INFO "input invalid. \n");
2396 break;
2397 }
2398
2399 return tmp_count;
2400}
2401
2402static const struct file_operations tlv320aic3x_audio_ops = {
2403 .open = simple_open,
2404 .read = tlv320aic3x_audio_read,
2405 .write = tlv320aic3x_audio_write,
2406};
2407
2408static inline int tlv320aic3x_audio_debugfs_init(struct pm80x_chip *chip)
2409{
2410
2411 tlv320aic3x_audio_control = debugfs_create_file("tlv320aic3x_audio", S_IRUGO | S_IFREG,
2412 NULL, NULL, &tlv320aic3x_audio_ops);
2413
2414 if (tlv320aic3x_audio_control == NULL) {
2415 pr_err("create tlv320aic3x debugfs error!\n");
2416 return -ENOENT;
2417 } else if (tlv320aic3x_audio_control == ERR_PTR(-ENODEV)) {
2418 pr_err("CONFIG_DEBUG_FS is not enabled!\n");
2419 return -ENOENT;
2420 }
2421
2422 return 0;
2423}
2424
2425static void tlv320aic3x_audio_debugfs_remove(struct pm80x_chip *chip)
2426{
2427 if (NULL != tlv320aic3x_audio_control){
2428 debugfs_remove_recursive(tlv320aic3x_audio_control);
2429 }
2430
2431 return;
2432};
2433
2434/* register codec to ALSA. */
2435static const struct snd_kcontrol_new tlv320aic3x_snd_controls[] = {
2436
2437 SOC_SINGLE("Reset Register", TLV320AIC3X_RESET_REG00, 0, 0xff, 0), //0x00
2438
2439 SOC_SINGLE("Clock Manager 1", TLV320AIC3X_CLK_MANAGER_REG01, 0, 0xff, 0), //0x01
2440 SOC_SINGLE("Clock Manager 2", TLV320AIC3X_CLK_MANAGER_REG02, 0, 0xff, 0), //0x02
2441 SOC_SINGLE("Clock Manager 3", TLV320AIC3X_CLK_MANAGER_REG03, 0, 0xff, 0), //0x03
2442 SOC_SINGLE("Clock Manager 4", TLV320AIC3X_CLK_MANAGER_REG04, 0, 0xff, 0), //0x04
2443 SOC_SINGLE("Clock Manager 5", TLV320AIC3X_CLK_MANAGER_REG05, 0, 0xff, 0), //0x05
2444 SOC_SINGLE("Clock Manager 6", TLV320AIC3X_CLK_MANAGER_REG06, 0, 0xff, 0), //0x06
2445 SOC_SINGLE("Clock Manager 7", TLV320AIC3X_CLK_MANAGER_REG07, 0, 0xff, 0), //0x07
2446 SOC_SINGLE("Clock Manager 8", TLV320AIC3X_CLK_MANAGER_REG08, 0, 0xff, 0), //0x08
2447
2448 SOC_SINGLE("ADC SDP Register", TLV320AIC3X_SDPIN_REG09, 0, 0xff, 0), //0x09
2449 SOC_SINGLE("DAC SDP Register", TLV320AIC3X_SDPOUT_REG0A, 0, 0xff, 0), //0x0A
2450
2451 SOC_SINGLE("System Manager 1", TLV320AIC3X_SYSTEM_REG0B, 0, 0xff, 0), //0x0B
2452 SOC_SINGLE("System Manager 2", TLV320AIC3X_SYSTEM_REG0C, 0, 0xff, 0), //0x0C
2453 SOC_SINGLE("System Manager 3", TLV320AIC3X_SYSTEM_REG0D, 0, 0xff, 0), //0x0D
2454 SOC_SINGLE("System Manager 4", TLV320AIC3X_SYSTEM_REG0E, 0, 0xff, 0), //0x0E
2455 SOC_SINGLE("System Manager 5", TLV320AIC3X_SYSTEM_REG0F, 0, 0xff, 0), //0x0F
2456 SOC_SINGLE("System Manager 6", TLV320AIC3X_SYSTEM_REG10, 0, 0xff, 0), //0x10
2457 SOC_SINGLE("System Manager 7", TLV320AIC3X_SYSTEM_REG11, 0, 0xff, 0), //0x11
2458 SOC_SINGLE("System Manager 8", TLV320AIC3X_SYSTEM_REG12, 0, 0xff, 0), //0x12
2459 SOC_SINGLE("System Manager 9", TLV320AIC3X_SYSTEM_REG13, 0, 0xff, 0), //0x13
2460 SOC_SINGLE("System Manager 10", TLV320AIC3X_SYSTEM_REG14, 0, 0xff, 0), //0x14
2461
2462 SOC_SINGLE("ADC RAMP Register", TLV320AIC3X_ADC_REG15, 0, 0xff, 0), //0x15
2463 SOC_SINGLE("ADC Register", TLV320AIC3X_ADC_REG16, 0, 0xff, 0), //0x16
2464 SOC_SINGLE("ADC Volume Register", TLV320AIC3X_ADC_REG17, 0, 0xff, 0), //0x17
2465 SOC_SINGLE("ADC ALC Register1", TLV320AIC3X_ADC_REG18, 0, 0xff, 0), //0x18
2466 SOC_SINGLE("ADC ALC Register2", TLV320AIC3X_ADC_REG19, 0, 0xff, 0), //0x19
2467 SOC_SINGLE("ADC Mute Register1", TLV320AIC3X_ADC_REG1A, 0, 0xff, 0), //0x1A
2468 SOC_SINGLE("ADC Mute Register2", TLV320AIC3X_ADC_REG1B, 0, 0xff, 0), //0x1B
2469 SOC_SINGLE("ADC EQ Register1", TLV320AIC3X_ADC_REG1C, 0, 0xff, 0), //0x1C
2470 SOC_SINGLE("ADC EQ Register2", TLV320AIC3X_ADC_REG1E, 0, 0xff, 0), //0x1E
2471
2472 SOC_SINGLE("DAC Mute Register", TLV320AIC3X_DAC_REG31, 0, 0xff, 0), //0x31
2473 SOC_SINGLE("DAC Volume Register", TLV320AIC3X_DAC_REG32, 0, 0xff, 0), //0x32
2474 SOC_SINGLE("DAC Offset Register", TLV320AIC3X_DAC_REG33, 0, 0xff, 0), //0x33
2475 SOC_SINGLE("DAC DRC Register1", TLV320AIC3X_DAC_REG34, 0, 0xff, 0), //0x34
2476 SOC_SINGLE("DAC DRC Register2", TLV320AIC3X_DAC_REG35, 0, 0xff, 0), //0x35
2477 SOC_SINGLE("DAC RAMP Register", TLV320AIC3X_DAC_REG37, 0, 0xff, 0), //0x37
2478
2479 SOC_SINGLE("GPIO AFSEL Register", TLV320AIC3X_GPIO_REG44, 0, 0xff, 0), //0x44
2480 SOC_SINGLE("GPIO CTL Register", TLV320AIC3X_GP_REG45, 0, 0xff, 0), //0x45
2481
2482};
2483
2484void tlv320aic3x_register_init(void)
2485{
2486
2487 tlv320aic3x_write( 0x00, 0x00);
2488 tlv320aic3x_write( 0x01, 0x80);
2489 tlv320aic3x_write( 0x07, 0x02);
2490 tlv320aic3x_write( 0x65, 0x00);
2491
2492 tlv320aic3x_write( 0x02, 0xaa);
2493 tlv320aic3x_write( 0x03, 0x91);
2494 tlv320aic3x_write( 0x04, 0xc0);
2495 tlv320aic3x_write( 0x05, 0x00);
2496
2497 tlv320aic3x_write( 0x06, 0x00);
2498 tlv320aic3x_write( 0x0b, 0x01);
2499 tlv320aic3x_write( 0x09, 0xc0);
2500 tlv320aic3x_write( 0x10, 0x00);
2501
2502 tlv320aic3x_write( 0x15, 0xf8);
2503 tlv320aic3x_write( 0x16, 0xb4);
2504 tlv320aic3x_write( 0x25, 0xc0);
2505 tlv320aic3x_write( 0x2c, 0x00);
2506
2507 tlv320aic3x_write( 0x5c, 0x80);
2508 tlv320aic3x_write( 0x5d, 0x01);
2509 tlv320aic3x_write( 0x5d, 0x09);
2510 tlv320aic3x_write( 0x2c, 0x32);
2511
2512}
2513
2514static int tlv320aic3x_codec_probe(struct snd_soc_component *component)
2515{
2516#ifdef TLV320AIC3X_DEBUG
2517 printk(KERN_INFO"%s/L%d.\n", __FUNCTION__, __LINE__);
2518#endif
2519
2520 // tlv320aic3x_write(TLV320AIC3X_RESET_REG00, 0x1f);
2521 // tlv320aic3x_write(TLV320AIC3X_RESET_REG00, 0x80);
2522
2523 printk("%s, wait for codec internal init\n", __func__);
2524 msleep(5);
2525
2526 tlv320aic3x_register_init();
2527
2528 // tlv320aic3x_write(TLV320AIC3X_SYSTEM_REG0D, 0x01);
2529 // tlv320aic3x_write(TLV320AIC3X_RESET_REG00, 0x1f);
2530 enable_tlv320aic3x_MClock();
2531 snd_soc_add_component_controls(component, tlv320aic3x_snd_controls, ARRAY_SIZE(tlv320aic3x_snd_controls));
2532
2533 return 0;
2534}
2535
2536static unsigned int tlv320aic3x_codec_read(struct snd_soc_component *component, unsigned int reg)
2537{
2538 unsigned short out_val = 0;
2539 int ret;
2540
2541 ret = tlv320aic3x_read(reg, &out_val);
2542
2543 if(ret)
2544 {
2545 printk("%s, read reg[0x%02x] fail\n", __func__, reg);
2546 return -EIO;
2547 }
2548
2549 out_val = out_val & 0xff;
2550
2551#ifdef TLV320AIC3X_DEBUG
2552 printk(KERN_INFO"%s/L%d.[0x%02x]=[0x%04x]\n", __FUNCTION__, __LINE__, reg, out_val);
2553#endif
2554
2555 return out_val;
2556}
2557
2558static int tlv320aic3x_codec_write(struct snd_soc_component *component,
2559 unsigned int reg, unsigned int value)
2560{
2561 int ret = 0;
2562
2563#ifdef TLV320AIC3X_DEBUG
2564 printk(KERN_INFO"%s/L%d.[0x%02x]=[0x%04x]\n", __FUNCTION__, __LINE__, reg, value);
2565#endif
2566
2567 ret = tlv320aic3x_write(reg, value & 0xFFFF);
2568
2569 return ret;
2570}
2571
2572/* tlv320aic3x_dai_ops */
2573
2574static int tlv320aic3x_digital_mute(struct snd_soc_dai *codec_dai, int mute)
2575{
2576#ifdef TLV320AIC3X_DEBUG
2577 printk(KERN_INFO"%s/L%d.\n", __FUNCTION__, __LINE__);
2578#endif
2579
2580 return 0;
2581}
2582
2583static int tlv320aic3x_hw_params(struct snd_pcm_substream *substream,
2584 struct snd_pcm_hw_params *params,
2585 struct snd_soc_dai *dai)
2586{
2587#ifdef TLV320AIC3X_DEBUG
2588 printk(KERN_INFO"%s/L%d.\n", __FUNCTION__, __LINE__);
2589#endif
2590
2591 return 0;
2592}
2593
2594static int tlv320aic3x_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
2595{
2596#ifdef TLV320AIC3X_DEBUG
2597 printk(KERN_INFO"%s/L%d.\n", __FUNCTION__, __LINE__);
2598#endif
2599
2600 return 0;
2601}
2602
2603static int tlv320aic3x_set_dai_sysclk(struct snd_soc_dai *dai,
2604 int clk_id, unsigned int freq, int dir)
2605{
2606#ifdef TLV320AIC3X_DEBUG
2607 printk(KERN_INFO"%s/L%d.\n", __FUNCTION__, __LINE__);
2608#endif
2609
2610 return 0;
2611}
2612
2613static const struct snd_soc_component_driver soc_component_dev_tlv320aic3x = {
2614 .probe = tlv320aic3x_codec_probe,
2615 .read = tlv320aic3x_codec_read,
2616 .write = tlv320aic3x_codec_write,
2617#if 0
2618 .suspend_bias_off = 1,
2619 .idle_bias_on = 1,
2620 .use_pmdown_time = 1,
2621 .endianness = 1,
2622 .non_legacy_dai_naming = 1,
2623#endif
2624};
2625
2626static struct snd_soc_dai_ops tlv320aic3x_dai_ops = {
2627 .digital_mute = tlv320aic3x_digital_mute,
2628 .hw_params = tlv320aic3x_hw_params,
2629 .set_fmt = tlv320aic3x_set_dai_fmt,
2630 .set_sysclk = tlv320aic3x_set_dai_sysclk,
2631};
2632
2633static struct snd_soc_dai_driver tlv320aic3x_dai[] ={
2634 {
2635 /* DAI I2S(SAI1) */
2636 .name = "tlv320aic3x-i2s",
2637 .id = 1,
2638 .playback = {
2639 .stream_name = "I2S Playback",
2640 .channels_min = 2,
2641 .channels_max = 2,
2642 .rates = SNDRV_PCM_RATE_8000_48000,
2643 .formats = SNDRV_PCM_FORMAT_S16_LE | \
2644 SNDRV_PCM_FORMAT_S18_3LE,
2645 },
2646 .capture = {
2647 .stream_name = "I2S Capture",
2648 .channels_min = 2,
2649 .channels_max = 2,
2650 .rates = SNDRV_PCM_RATE_8000_48000,
2651 .formats = SNDRV_PCM_FORMAT_S16_LE | \
2652 SNDRV_PCM_FORMAT_S18_3LE,
2653 },
2654 .ops = &tlv320aic3x_dai_ops,
2655 }, {
2656 /* DAI PCM(SAI2) */
2657 .name = "tlv320aic3x-pcm",
2658 .id = 2,
2659 .playback = {
2660 .stream_name = "PCM Playback",
2661 .channels_min = 1,
2662 .channels_max = 2,
2663 .rates = SNDRV_PCM_RATE_8000_48000,
2664 .formats = SNDRV_PCM_FORMAT_S8| \
2665 SNDRV_PCM_FORMAT_S16_LE | \
2666 SNDRV_PCM_FORMAT_S20_3LE | \
2667 SNDRV_PCM_FORMAT_S24,
2668 },
2669 .capture = {
2670 .stream_name = "PCM Capture",
2671 .channels_min = 1,
2672 .channels_max = 2,
2673 .rates = SNDRV_PCM_RATE_8000_48000,
2674 .formats = SNDRV_PCM_FORMAT_S8| \
2675 SNDRV_PCM_FORMAT_S16_LE | \
2676 SNDRV_PCM_FORMAT_S20_3LE | \
2677 SNDRV_PCM_FORMAT_S24,
2678 },
2679 .ops = &tlv320aic3x_dai_ops,
2680 },
2681};
2682
2683#ifdef HEADSET_DETECTION
2684irqreturn_t codec_irq_handler(int irq, void *dev_id)
2685{
2686 printk(KERN_INFO"%s/L%d.\n", __FUNCTION__, __LINE__);
2687
2688 /* check the headset plug in/out */
2689 tlv320aic3x_get_headset_status();
2690
2691 return IRQ_HANDLED;
2692}
2693#endif
2694
2695//Kestrel
2696void audio_set_codec_vdd(int on_off)
2697{
2698 struct regulator *vdd_1v8 = NULL;
2699 struct regulator *vdd_3v3 = NULL;
2700 static int codec_on_off = 0;
2701
2702 printk(KERN_INFO"%s: codec now:%d, to be:%d\n", __FUNCTION__, codec_on_off, on_off);
2703
2704 if (!(cpu_is_asr1901() || cpu_is_asr1906()) || codec_on_off == on_off)
2705 {
2706 return;
2707 }
2708
2709 if(on_off) {
2710 /* 1V8 */
2711 vdd_1v8 = regulator_get(&g_tlv320aic3x_client->dev, "vdd18");
2712 if (IS_ERR_OR_NULL(vdd_1v8)) {
2713 if (PTR_ERR(vdd_1v8) < 0) {
2714 printk(KERN_INFO"%s: the regulator for vdd_1v8 not found.\n", __FUNCTION__);
2715 }
2716 } else {
2717 tlv320aic3x_regulator_vdd_1v8 = vdd_1v8;
2718 printk(KERN_INFO"%s: the regulator for vdd_1v8 is OK.\n", __FUNCTION__);
2719 }
2720
2721 if (tlv320aic3x_regulator_vdd_1v8 > 0) {
2722 if (regulator_set_voltage(tlv320aic3x_regulator_vdd_1v8, 1800000, 1800000))
2723 printk(KERN_INFO"fail to set regulator with 1.8v.\n");
2724 if (regulator_enable(tlv320aic3x_regulator_vdd_1v8))
2725 printk(KERN_INFO"fail to enable regulator vdd_1v8.\n");
2726 }
2727
2728 /* 3V3 */
2729 vdd_3v3 = regulator_get(&g_tlv320aic3x_client->dev, "vdd33");
2730 if (IS_ERR_OR_NULL(vdd_3v3)) {
2731 if (PTR_ERR(vdd_3v3) < 0) {
2732 printk(KERN_INFO"%s: the regulator for vdd_3v3 not found.\n", __FUNCTION__);
2733 }
2734 } else {
2735 tlv320aic3x_regulator_vdd_3v3 = vdd_3v3;
2736 printk(KERN_INFO"%s: the regulator for vdd_3v3 is OK.\n", __FUNCTION__);
2737 }
2738
2739 if (tlv320aic3x_regulator_vdd_3v3 > 0) {
2740 if (regulator_set_voltage(tlv320aic3x_regulator_vdd_3v3, 3300000, 3300000))
2741 printk(KERN_INFO"fail to set regulator with 3.3v.\n");
2742 if (regulator_enable(tlv320aic3x_regulator_vdd_3v3))
2743 printk(KERN_INFO"fail to enable regulator vdd_3v3.\n");
2744 }
2745
2746 codec_on_off = 1;
2747 }
2748 else {
2749 if (tlv320aic3x_regulator_vdd_1v8 > 0) {
2750 if (regulator_disable(tlv320aic3x_regulator_vdd_1v8))
2751 printk(KERN_INFO"fail to disable regulator vdd_1v8\n");
2752 }
2753
2754 if (tlv320aic3x_regulator_vdd_3v3 > 0) {
2755 if (regulator_disable(tlv320aic3x_regulator_vdd_3v3))
2756 printk(KERN_INFO"fail to disable regulator vdd_3v3\n");
2757 }
2758
2759 codec_on_off = 0;
2760 }
2761}
2762EXPORT_SYMBOL_GPL(audio_set_codec_vdd);
2763
2764
2765//Kestrel/NezhaC/Falcon
2766static void tlv320aic3x_config_init(void)
2767{
2768 struct pinctrl_state *pin_AUDIO = NULL;
2769 int gpio_1V8 = 0;
2770 int gpio_3V3 = 0;
2771#ifdef HEADSET_DETECTION
2772 int ret = -1;
2773#endif
2774
2775#ifdef TLV320AIC3X_DEBUG
2776 printk(KERN_INFO"%s/L%d.\n", __FUNCTION__, __LINE__);
2777#endif
2778
2779 if (cpu_is_asr1803()) {
2780 printk(KERN_INFO"%s, platform is Falcon.\n", __FUNCTION__);
2781 } else if (cpu_is_asr1806()) {
2782 printk(KERN_INFO"%s, platform is Falcon-T.\n", __FUNCTION__);
2783 } else if (cpu_is_asr1901() || cpu_is_asr1906()) {
2784 printk(KERN_INFO"%s, platform is Kestrel.\n", __FUNCTION__);
2785 } else if (cpu_is_asr1903()) {
2786 printk(KERN_INFO"%s, platform is Lapwing.\n", __FUNCTION__);
2787 } else if (cpu_is_asr1802s()) {
2788 printk(KERN_INFO"%s, platform is Nezhac.\n", __FUNCTION__);
2789 } else {
2790 printk(KERN_INFO"%s, please check the platform.\n", __FUNCTION__);
2791 }
2792
2793 /*
2794 NezhaC AUDIO_PIN_CTRL = TDS_DIO10 = function 1 , GPIO-78
2795 Config MPFR in arch/arm/boot/dts/asr1802s-p201.dts
2796 */
2797 pin_AUDIO = pinctrl_lookup_state(g_tlv320aic3x_pinctrl, "default");
2798
2799 pinctrl_select_state(g_tlv320aic3x_pinctrl, pin_AUDIO);
2800
2801 /* config MPFR of device node "asrmicro,tlv320aic3x" */
2802 if (cpu_is_asr1802s()) {
2803 gpio_tds_dio10 = of_get_named_gpio(g_tlv320aic3x_node, "tds_dio10-gpio", 0);/* GPIO[78] */
2804 gpio_vcxo_out = of_get_named_gpio(g_tlv320aic3x_node, "vcxo_out-gpio", 0);/* GPIO[126] */
2805 }
2806
2807 printk(KERN_INFO"%s/L%d, gpio_tds_dio10 = %d, gpio_vcxo_out = %d\n", __FUNCTION__, __LINE__, gpio_tds_dio10, gpio_vcxo_out);
2808
2809 /* TDS_DIO10 */
2810 //gpio_request(gpio_tds_dio10, "TDS_DIO10");
2811 //gpio_direction_output(gpio_tds_dio10, 0);
2812
2813 /* VCXO_OUT */
2814 if (cpu_is_asr1802s()) {
2815 gpio_request(gpio_vcxo_out, "VCXO_OUT");
2816 gpio_direction_input(gpio_vcxo_out);
2817 }
2818
2819 /* config VDD */
2820 if (cpu_is_asr1802s()) {
2821 gpio_1V8 = of_get_named_gpio(g_tlv320aic3x_node, "1V8-gpio", 0);
2822 }
2823
2824 gpio_3V3 = of_get_named_gpio(g_tlv320aic3x_node, "3V3-gpio", 0);
2825
2826 printk(KERN_INFO"%s/L%d, gpio_1V8=%d, gpio_3V3=%d.\n", __FUNCTION__, __LINE__, gpio_1V8, gpio_3V3);
2827
2828 /* GPIO_31 for CODEC_1V8_EN.
2829 GPIO_32 for CODEC_3V3_EN. */
2830 //gpio_31_CODEC_1V8_EN = mfp_to_gpio(MFP_PIN_GPIO31);
2831 //gpio_32_CODEC_3V3_EN = mfp_to_gpio(MFP_PIN_GPIO32);
2832
2833 if (cpu_is_asr1802s()) {
2834 gpio_31_CODEC_1V8_EN = gpio_1V8;
2835 }
2836
2837 gpio_32_CODEC_3V3_EN = gpio_3V3;
2838
2839 if (cpu_is_asr1802s()) {
2840 if (gpio_31_CODEC_1V8_EN) {
2841 if (gpio_request(gpio_31_CODEC_1V8_EN, "power on/off 1V8")) {
2842 gpio_31_CODEC_1V8_EN = 0;
2843 } else {
2844 gpio_direction_output(gpio_31_CODEC_1V8_EN, 0);
2845 }
2846 }
2847 }
2848
2849 if (gpio_32_CODEC_3V3_EN >= 0) {
2850 if (gpio_request(gpio_32_CODEC_3V3_EN, "power on/off 3V3")) {
2851 gpio_32_CODEC_3V3_EN = 0;
2852 } else {
2853 gpio_direction_output(gpio_32_CODEC_3V3_EN, 0);
2854 }
2855 }
2856
2857 if (cpu_is_asr1802s()) {
2858 gpio_direction_output(gpio_31_CODEC_1V8_EN, 1);
2859 }
2860
2861 if (gpio_32_CODEC_3V3_EN >= 0) {
2862 gpio_direction_output(gpio_32_CODEC_3V3_EN, 1);
2863 }
2864
2865 /* Power on for ASR1901 kestrel */
2866 audio_set_codec_vdd(1);
2867
2868#ifdef HEADSET_DETECTION
2869 /* CODEC_IRQ */
2870 gpio_CODEC_IRQ = of_get_named_gpio(g_tlv320aic3x_node, "irq-gpio", 0); //GPIO[1]
2871 printk(KERN_INFO"%s/L%d, gpio_CODEC_IRQ=%d.\n", __FUNCTION__, __LINE__, gpio_CODEC_IRQ);
2872
2873 gpio_request(gpio_CODEC_IRQ, "CODEC_IRQ");
2874 gpio_direction_input(gpio_CODEC_IRQ);
2875
2876 irq_codec = gpio_to_irq(gpio_CODEC_IRQ);
2877 printk(KERN_INFO"%s/L%d, irq_codec=%d.\n", __FUNCTION__, __LINE__, irq_codec);
2878
2879 /* request irq */
2880 ret = request_threaded_irq(irq_codec, NULL, codec_irq_handler,
2881 IRQF_SHARED | IRQF_TRIGGER_RISING |
2882 IRQF_TRIGGER_FALLING | IRQF_ONESHOT, "tlv320aic3x-headset_detection",
2883 g_tlv320aic3x_client);
2884 if (ret < 0) {
2885 printk(KERN_INFO"%s: request irq failed!\n",__FUNCTION__);
2886 }
2887#endif
2888
2889#if 0 //The vdds should be supplied
2890 /* Power off for ASR1901 kestrel */
2891 audio_set_codec_vdd(0);
2892#endif
2893
2894 return;
2895}
2896
2897static int g_fsync_rate = 0;
2898static ssize_t tlv320aic3x_switch_rate_show(struct device *dev, struct device_attribute *attr,
2899 char *buf)
2900{
2901 int s = 0;
2902
2903 s += sprintf(buf, "%d", g_fsync_rate);
2904 return s;
2905}
2906
2907static ssize_t tlv320aic3x_switch_rate_set(struct device *dev,
2908 struct device_attribute *attr,
2909 const char *buf, size_t count)
2910{
2911 int ret;
2912
2913 ret = kstrtoint(buf, 10, &g_fsync_rate);
2914 if (ret)
2915 return ret;
2916
2917 Audio_Codec_Fsync_Rate = g_fsync_rate;
2918 enable_tlv320aic3x_MClock();
2919 printk(KERN_INFO"%s, Audio_Codec_Fsync_Rate=%d\n", __FUNCTION__, Audio_Codec_Fsync_Rate);
2920
2921 return count;
2922}
2923static DEVICE_ATTR(tlv320aic3x_switch_rate, 0644, tlv320aic3x_switch_rate_show, tlv320aic3x_switch_rate_set);
2924
2925
2926
2927
2928
2929
2930
2931
2932
2933
2934/* i2c driver */
2935static int tlv320aic3x_probe(struct i2c_client *client,
2936 const struct i2c_device_id *id)
2937{
2938 int ret = 0;
2939
2940 printk(KERN_INFO"[tlv320aic3x codec-dai probe: begin] %s/L%d.\n", __FUNCTION__, __LINE__);
2941 printk("--->%s/L%d\n", __FUNCTION__, __LINE__);
2942 if (NULL == client) {
2943 printk(KERN_INFO"Please check codec input parameter for client.\n");
2944 return 0;
2945 }
2946
2947 g_tlv320aic3x_client = client;
2948
2949 g_tlv320aic3x_pinctrl = devm_pinctrl_get(&client->dev);
2950 if (NULL == g_tlv320aic3x_pinctrl){
2951 printk(KERN_INFO"Please check codec input parameter for g_tlv320aic3x_pinctrl.\n");
2952 return 0;
2953 }
2954
2955 g_tlv320aic3x_node = client->dev.of_node;
2956 if (NULL == g_tlv320aic3x_node){
2957 printk(KERN_INFO"Please check codec input parameter for g_tlv320aic3x_node.\n");
2958 return 0;
2959 }
2960
2961
2962 g_reset_gpio = of_get_named_gpio(g_tlv320aic3x_node, "reset-gpio", 0);/* GPIO[120] */
2963 if (unlikely(g_reset_gpio < 0)) {
2964 printk("g_reset_gpio undefined\n");
2965
2966 }
2967 else
2968 {
2969 printk("g_reset_gpio get success \n");
2970 gpio_request(g_reset_gpio, "g_eth_0v9_pin");
2971 gpio_direction_output(g_reset_gpio, 1);
2972 mdelay(50);
2973 gpio_direction_output(g_reset_gpio, 0);
2974 mdelay(50);
2975 gpio_direction_output(g_reset_gpio, 1);
2976
2977 }
2978
2979
2980 tlv320aic3x_dump_debugfs_init(NULL);
2981
2982
2983 // tlv320aic3x_audio_debugfs_init(NULL);
2984
2985 /* Power on the tlv320aic3x. */
2986 //tlv320aic3x_config_init();
2987
2988 /* initiate the TLV320AIC3X codec. */
2989 // codec_tlv320aic3x_init();
2990
2991 // if (!tlv320aic3x_is_connect()) {
2992 // printk(KERN_INFO"Please check codec tlv320aic3x OK or not.\n");
2993 // return 0;
2994 // }
2995
2996#ifdef CONFIG_CPU_ASR1901
2997 if(!enable_pmu_audio_clk())
2998 {
2999#endif
3000 // enable_tlv320aic3x_MClock();
3001 // tlv320aic3x_set_sysclk(1);
3002#ifdef CONFIG_CPU_ASR1901
3003 }
3004#endif
3005
3006#if 0
3007 /* if debug the codec in kernel, could open the procedure */
3008
3009 /* enable the path. */
3010 codec_tlv320aic3x_power_on();
3011
3012 //codec_tlv320aic3x_enable_headphone_main_mic();
3013 //codec_tlv320aic3x_switch_headset(1);
3014
3015 tlv320aic3x_headphone_on();
3016 tlv320aic3x_headset_mic_on();
3017
3018 codec_tlv320aic3x_set_headphone_gain();
3019 codec_tlv320aic3x_set_headphone_mic_gain();
3020#endif
3021
3022#if 0
3023 /* if debug the codec in kernel, could open the procedure for spk */
3024
3025 /* enable the path. */
3026 codec_tlv320aic3x_power_on();
3027
3028 tlv320aic3x_speaker_on();
3029 tlv320aic3x_main_mic_on();
3030 /* Enable the speaker path using the command:echo 7 > /sys/kernel/debug/tlv320aic3x_audio */
3031 /* Enable PA from CP or Enable PA using the command:echo 0 > /sys/kernel/debug/tlv320aic3x_audio */
3032#endif
3033 /*
3034 create the platform device, and platform driver will register codec to ALSA.
3035 which will be for device node, such as /dev/snd/timer, control0, ...
3036 snd_soc_register_codec(&client->dev, &soc_codec_dev_tlv320aic3x,
3037 tlv320aic3x_dai, ARRAY_SIZE(tlv320aic3x_dai));
3038 int snd_soc_register_card(struct snd_soc_card *card)
3039 */
3040 ret = devm_snd_soc_register_component(&client->dev, &soc_component_dev_tlv320aic3x,
3041 tlv320aic3x_dai, ARRAY_SIZE(tlv320aic3x_dai));
3042
3043 if (ret < 0) {
3044 printk(KERN_INFO"Failed to register codec tlv320aic3x: %d.\n", ret);
3045 return ret;
3046 }
3047
3048 /* Headset detection platform device */
3049 //tlv320aic3x_headset_detection_init(client);
3050
3051 /* create the interface for audio_if command "config_pcm" */
3052 ret = device_create_file(&client->dev, &dev_attr_tlv320aic3x_switch_rate);
3053 if (ret < 0) {
3054 printk(KERN_INFO"attr tlv320aic3x_switch_rate create fail: %d.\n", ret);
3055 return ret;
3056
3057 printk(KERN_INFO"[tlvv320aic3x codec-dai probe: end] %s/L%d.\n", __FUNCTION__, __LINE__);
3058 }
3059
3060
3061 return 0;
3062}
3063
3064static int tlv320aic3x_remove(struct i2c_client *client)
3065{
3066#ifdef TLV320AIC3X_DEBUG
3067 printk(KERN_INFO"%s/L%d.\n", __FUNCTION__, __LINE__);
3068#endif
3069
3070 tlv320aic3x_dump_debugfs_remove(NULL);
3071
3072 // tlv320aic3x_audio_debugfs_remove(NULL);
3073
3074 /* free gpio resource. */
3075 //gpio_free(gpio_tds_dio10);
3076 if (cpu_is_asr1802s()) {
3077 gpio_free(gpio_vcxo_out);
3078 }
3079
3080 if (cpu_is_asr1802s()) {
3081 gpio_free(gpio_31_CODEC_1V8_EN);
3082 }
3083
3084 if (gpio_32_CODEC_3V3_EN >= 0) {
3085 gpio_free(gpio_32_CODEC_3V3_EN);
3086 }
3087
3088 /* Power off for ASR1901 kestrel */
3089 audio_set_codec_vdd(0);
3090
3091#ifdef HEADSET_DETECTION
3092 gpio_free(gpio_CODEC_IRQ);
3093 free_irq(irq_codec, g_tlv320aic3x_client);
3094#endif
3095 /* disable the path. */
3096 //codec_tlv320aic3x_disable_path();
3097 //codec_tlv320aic3x_disable_path_app();
3098
3099 codec_tlv320aic3x_power_off();
3100
3101 g_tlv320aic3x_client = NULL;
3102
3103 mfd_remove_devices(&client->dev);
3104 return 0;
3105}
3106
3107void tlv320aic3x_shutdown(struct i2c_client *client)
3108{
3109#ifdef TLV320AIC3X_DEBUG
3110 printk(KERN_INFO"%s/L%d.\n", __FUNCTION__, __LINE__);
3111#endif
3112
3113 return;
3114}
3115
3116static struct i2c_driver tlv320aic3x_driver = {
3117 .driver = {
3118 .name = "tlv320aic3x",
3119 .of_match_table = of_match_ptr(tlv320aic3x_dt_ids),
3120 },
3121 .probe = tlv320aic3x_probe,
3122 .remove = tlv320aic3x_remove,
3123 //.shutdown = tlv320aic3x_shutdown,
3124 .id_table = tlv320aic3x_dt_table,
3125};
3126
3127static int tlv320aic3x_i2c_init(void)
3128{
3129 return i2c_add_driver(&tlv320aic3x_driver);
3130}
3131module_init(tlv320aic3x_i2c_init);
3132
3133static void tlv320aic3x_i2c_exit(void)
3134{
3135 i2c_del_driver(&tlv320aic3x_driver);
3136}
3137module_exit(tlv320aic3x_i2c_exit);
3138
3139MODULE_DESCRIPTION("Driver for tlv320aic3x");
3140MODULE_AUTHOR("wenchen@asrmicro.com");
3141MODULE_LICENSE("GPL");