| b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 1 | #ifndef _DT_BINDING_TIMER_MMP_H |
| 2 | #define _DT_BINDING_TIMER_MMP_H |
| 3 | |
| 4 | /* timer flag bit definition */ |
| 5 | /* bit[0]: MMP_TIMER_FLAG_SHADOW |
| 6 | * Indicate if the timer has shadow registers. If it has, |
| 7 | * counter could be read out directly. |
| 8 | * bit[1]: MMP_TIMER_FLAG_CRSR |
| 9 | * Indicate if timer has CRSR register. If it has, |
| 10 | * counter could be restarted by directly writing CRSR. |
| 11 | * bit[2]: MMP_TIMER_FLAG_PLVR |
| 12 | * Indicate if tiemr needs preload value when it restarts. |
| 13 | */ |
| 14 | #define MMP_TIMER_FLAG_SHADOW (1 << 0) |
| 15 | #define MMP_TIMER_FLAG_CRSR (1 << 1) |
| 16 | #define MMP_TIMER_FLAG_PLVR (1 << 2) |
| 17 | |
| 18 | #define MMP_TIMER_ALL_CPU (0xFFFFFFFF) |
| 19 | |
| 20 | #define MMP_TIMER_COUNTER_NOTUSED 0 |
| 21 | #define MMP_TIMER_COUNTER_CLKSRC (1 << 0) |
| 22 | #define MMP_TIMER_COUNTER_CLKEVT (1 << 1) |
| 23 | #define MMP_TIMER_COUNTER_DELAY (1 << 2) |
| 24 | #define MMP_TIMER_USAGE_MSK (MMP_TIMER_COUNTER_CLKSRC | \ |
| 25 | MMP_TIMER_COUNTER_CLKEVT | \ |
| 26 | MMP_TIMER_COUNTER_DELAY) |
| 27 | |
| 28 | #endif |