| b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* |
| 3 | * Copyright (c) 2017 MediaTek Inc. |
| 4 | * Author: Yong Wu <yong.wu@mediatek.com> |
| 5 | */ |
| 6 | #ifndef __DTS_IOMMU_PORT_MT2712_H |
| 7 | #define __DTS_IOMMU_PORT_MT2712_H |
| 8 | |
| 9 | #define MTK_M4U_ID(larb, port) (((larb) << 5) | (port)) |
| 10 | |
| 11 | #define M4U_LARB0_ID 0 |
| 12 | #define M4U_LARB1_ID 1 |
| 13 | #define M4U_LARB2_ID 2 |
| 14 | #define M4U_LARB3_ID 3 |
| 15 | #define M4U_LARB4_ID 4 |
| 16 | #define M4U_LARB5_ID 5 |
| 17 | #define M4U_LARB6_ID 6 |
| 18 | #define M4U_LARB7_ID 7 |
| 19 | #define M4U_LARB8_ID 8 |
| 20 | #define M4U_LARB9_ID 9 |
| 21 | |
| 22 | /* larb0 */ |
| 23 | #define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 0) |
| 24 | #define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 1) |
| 25 | #define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 2) |
| 26 | #define M4U_PORT_DISP_OD_R MTK_M4U_ID(M4U_LARB0_ID, 3) |
| 27 | #define M4U_PORT_DISP_OD_W MTK_M4U_ID(M4U_LARB0_ID, 4) |
| 28 | #define M4U_PORT_MDP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 5) |
| 29 | #define M4U_PORT_MDP_WDMA MTK_M4U_ID(M4U_LARB0_ID, 6) |
| 30 | #define M4U_PORT_DISP_RDMA2 MTK_M4U_ID(M4U_LARB0_ID, 7) |
| 31 | |
| 32 | /* larb1 */ |
| 33 | #define M4U_PORT_HW_VDEC_MC_EXT MTK_M4U_ID(M4U_LARB1_ID, 0) |
| 34 | #define M4U_PORT_HW_VDEC_PP_EXT MTK_M4U_ID(M4U_LARB1_ID, 1) |
| 35 | #define M4U_PORT_HW_VDEC_UFO_EXT MTK_M4U_ID(M4U_LARB1_ID, 2) |
| 36 | #define M4U_PORT_HW_VDEC_VLD_EXT MTK_M4U_ID(M4U_LARB1_ID, 3) |
| 37 | #define M4U_PORT_HW_VDEC_VLD2_EXT MTK_M4U_ID(M4U_LARB1_ID, 4) |
| 38 | #define M4U_PORT_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(M4U_LARB1_ID, 5) |
| 39 | #define M4U_PORT_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(M4U_LARB1_ID, 6) |
| 40 | #define M4U_PORT_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(M4U_LARB1_ID, 7) |
| 41 | #define M4U_PORT_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(M4U_LARB1_ID, 8) |
| 42 | #define M4U_PORT_HW_VDEC_TILE MTK_M4U_ID(M4U_LARB1_ID, 9) |
| 43 | #define M4U_PORT_HW_IMG_RESZ_EXT MTK_M4U_ID(M4U_LARB1_ID, 10) |
| 44 | |
| 45 | /* larb2 */ |
| 46 | #define M4U_PORT_CAM_DMA0 MTK_M4U_ID(M4U_LARB2_ID, 0) |
| 47 | #define M4U_PORT_CAM_DMA1 MTK_M4U_ID(M4U_LARB2_ID, 1) |
| 48 | #define M4U_PORT_CAM_DMA2 MTK_M4U_ID(M4U_LARB2_ID, 2) |
| 49 | |
| 50 | /* larb3 */ |
| 51 | #define M4U_PORT_VENC_RCPU MTK_M4U_ID(M4U_LARB3_ID, 0) |
| 52 | #define M4U_PORT_VENC_REC MTK_M4U_ID(M4U_LARB3_ID, 1) |
| 53 | #define M4U_PORT_VENC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 2) |
| 54 | #define M4U_PORT_VENC_SV_COMV MTK_M4U_ID(M4U_LARB3_ID, 3) |
| 55 | #define M4U_PORT_VENC_RD_COMV MTK_M4U_ID(M4U_LARB3_ID, 4) |
| 56 | #define M4U_PORT_VENC_CUR_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 5) |
| 57 | #define M4U_PORT_VENC_REF_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 6) |
| 58 | #define M4U_PORT_VENC_CUR_LUMA MTK_M4U_ID(M4U_LARB3_ID, 7) |
| 59 | #define M4U_PORT_VENC_REF_LUMA MTK_M4U_ID(M4U_LARB3_ID, 8) |
| 60 | |
| 61 | /* larb4 */ |
| 62 | #define M4U_PORT_DISP_OVL1 MTK_M4U_ID(M4U_LARB4_ID, 0) |
| 63 | #define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(M4U_LARB4_ID, 1) |
| 64 | #define M4U_PORT_DISP_WDMA1 MTK_M4U_ID(M4U_LARB4_ID, 2) |
| 65 | #define M4U_PORT_DISP_OD1_R MTK_M4U_ID(M4U_LARB4_ID, 3) |
| 66 | #define M4U_PORT_DISP_OD1_W MTK_M4U_ID(M4U_LARB4_ID, 4) |
| 67 | #define M4U_PORT_MDP_RDMA1 MTK_M4U_ID(M4U_LARB4_ID, 5) |
| 68 | #define M4U_PORT_MDP_WROT1 MTK_M4U_ID(M4U_LARB4_ID, 6) |
| 69 | |
| 70 | /* larb5 */ |
| 71 | #define M4U_PORT_DISP_OVL2 MTK_M4U_ID(M4U_LARB5_ID, 0) |
| 72 | #define M4U_PORT_DISP_WDMA2 MTK_M4U_ID(M4U_LARB5_ID, 1) |
| 73 | #define M4U_PORT_MDP_RDMA2 MTK_M4U_ID(M4U_LARB5_ID, 2) |
| 74 | #define M4U_PORT_MDP_WROT0 MTK_M4U_ID(M4U_LARB5_ID, 3) |
| 75 | |
| 76 | /* larb6 */ |
| 77 | #define M4U_PORT_JPGDEC_WDMA_0 MTK_M4U_ID(M4U_LARB6_ID, 0) |
| 78 | #define M4U_PORT_JPGDEC_WDMA_1 MTK_M4U_ID(M4U_LARB6_ID, 1) |
| 79 | #define M4U_PORT_JPGDEC_BSDMA_0 MTK_M4U_ID(M4U_LARB6_ID, 2) |
| 80 | #define M4U_PORT_JPGDEC_BSDMA_1 MTK_M4U_ID(M4U_LARB6_ID, 3) |
| 81 | |
| 82 | /* larb7 */ |
| 83 | #define M4U_PORT_MDP_RDMA3 MTK_M4U_ID(M4U_LARB7_ID, 0) |
| 84 | #define M4U_PORT_MDP_WROT2 MTK_M4U_ID(M4U_LARB7_ID, 1) |
| 85 | |
| 86 | /* larb8 */ |
| 87 | #define M4U_PORT_VDO MTK_M4U_ID(M4U_LARB8_ID, 0) |
| 88 | #define M4U_PORT_NR MTK_M4U_ID(M4U_LARB8_ID, 1) |
| 89 | #define M4U_PORT_WR_CHANNEL0 MTK_M4U_ID(M4U_LARB8_ID, 2) |
| 90 | |
| 91 | /* larb9 */ |
| 92 | #define M4U_PORT_TVD MTK_M4U_ID(M4U_LARB9_ID, 0) |
| 93 | #define M4U_PORT_WR_CHANNEL1 MTK_M4U_ID(M4U_LARB9_ID, 1) |
| 94 | |
| 95 | #endif |