| b.liu | b17525e | 2025-05-14 17:22:29 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* |
| 3 | * Copyright (C) |
| 4 | * |
| 5 | * Author: |
| 6 | */ |
| 7 | |
| 8 | #ifndef _DT_BINDINGS_SOC_ZX297520V3_IRQ_H |
| 9 | #define _DT_BINDINGS_SOC_ZX297520V3_IRQ_H |
| 10 | |
| 11 | #include <linux/irq.h> |
| 12 | |
| 13 | //#define WDT_INT (0) |
| 14 | #define UART1_MIX_INT (27) |
| 15 | #define UART2_MIX_INT (59) |
| 16 | #define UART3_MIX_INT (28) |
| 17 | #define UART4_MIX_INT (19) |
| 18 | |
| 19 | #define SSP0_INT (3) |
| 20 | #define RTC_ALARM_INT (6) |
| 21 | #define RTC_TIMER_INT (5) |
| 22 | //#define I2S0_INT (6) |
| 23 | //#define I2S1_INT (7) |
| 24 | #define I2C1_INT (15) |
| 25 | #define I2C0_INT (7) /*pmic i2c*/ |
| 26 | #define I2C2_INT (54) |
| 27 | #define I2C3_INT (67) |
| 28 | |
| 29 | #define KEYPAD_INT (9) |
| 30 | |
| 31 | #define SD1_INT (39) |
| 32 | #define SD0_INT (39) |
| 33 | |
| 34 | //#define EX21_INT (gpio_to_irq(21)) |
| 35 | //#define EX22_INT (gpio_to_irq(22)) |
| 36 | //#define EX23_INT (gpio_to_irq(23)) |
| 37 | //#define EX24_INT (gpio_to_irq(24)) |
| 38 | #if 0 |
| 39 | |
| 40 | #define ICP_PS2AP_INT (13) |
| 41 | #define ICP_M02AP_INT (14) |
| 42 | #define AP_TIMER0_INT (15) |
| 43 | #define AP_TIMER1_INT (16) |
| 44 | #define AP_TIMER2_INT (17) |
| 45 | #define GSM_RFSSCR_INT (18) |
| 46 | #define GSM_RFSSCT_INT (19) |
| 47 | #define GSM_GP0_INT (20) |
| 48 | #define GSM_T_INT (21) |
| 49 | #define GSM_TL_INT (22) |
| 50 | #define GPRS0_INT (23) |
| 51 | #define GPRS1_INT (24) |
| 52 | #define DSP0_INT (25) |
| 53 | #define DSP1_INT (26) |
| 54 | #define DSP2_INT (27) |
| 55 | #define DSP3_INT (28) |
| 56 | #define DSP4_INT (29) |
| 57 | #define DSP6_INT (30) |
| 58 | #define DSP7_INT (31) |
| 59 | #define SPCU_PW_INT (32) |
| 60 | #define ROUT1_INT (33) |
| 61 | #define PS_DMA_INT (34) |
| 62 | #define NAND_INT (35) |
| 63 | #define USB_INT (36) |
| 64 | #define USB_POWERDWN_UP_INT (37) |
| 65 | #define USB_POWERDWN_DOWN_INT (38) |
| 66 | #define HSIC_INT (39) |
| 67 | #define HSIC_POWERDWN_UP_INT (40) |
| 68 | #define HSIC_POWERDWN_DOWN_INT (41) |
| 69 | #define LTE_LPM_TIMER5_INT (42) |
| 70 | #define GSM_USIM_INT (43) |
| 71 | |
| 72 | |
| 73 | |
| 74 | #define EX8IN1_INT (44) |
| 75 | #define EX0_INT (45) |
| 76 | #define EX1_INT (46) |
| 77 | #define EX2_INT (47) |
| 78 | #define EX3_INT (48) |
| 79 | #define EX4_INT (49) |
| 80 | #define EX5_INT (50) |
| 81 | #define EX6_INT (51) |
| 82 | #define EX7_INT (52) |
| 83 | #define SD1_DATA1_INT (53) |
| 84 | #define UART0_RXD_INT (54) |
| 85 | #define SPI_FC0_INT (55) /*spi nand*/ |
| 86 | #define SSP1_INT (56) |
| 87 | #define SD0_DATA1_INT (57) |
| 88 | #define EFUSE_INT (58) |
| 89 | #define RSA_INT (59) |
| 90 | #define HASH_INT (60) |
| 91 | #define GMAC_INT (61) |
| 92 | #define AP_TIMER3_INT (62) |
| 93 | #define AP_TIMER4_INT (63) |
| 94 | #define FRM_ARM_INT (64) |
| 95 | #define WD_FRAME_INT (65) |
| 96 | #define ICP_PHY2AP_INT (66) |
| 97 | #define MCU_LCD_INT (67) |
| 98 | #define VOU_OSD_INT (68) |
| 99 | #define TDM_INT (69) |
| 100 | #define RESERVED_INT (70) |
| 101 | #define SYS_COUNTER_INT (71) |
| 102 | #define PWM_INT (72) |
| 103 | #define GMACPHY_WAKE_INT (73) |
| 104 | #define GMACPHY_INT (74) |
| 105 | #define USIM1_INT (75) |
| 106 | |
| 107 | |
| 108 | #define IRQ_ZX297520V3_SPI_NUM (77) |
| 109 | |
| 110 | /* pcu ext8_1 */ |
| 111 | #define EX8_INT (0) |
| 112 | #define EX9_INT (1) |
| 113 | #define EX10_INT (2) |
| 114 | #define EX11_INT (3) |
| 115 | #define EX12_INT (4) |
| 116 | #define EX13_INT (5) |
| 117 | #define EX14_INT (6) |
| 118 | #define EX15_INT (7) |
| 119 | |
| 120 | #endif |
| 121 | |
| 122 | #endif /* _DT_BINDINGS_SOC_ZX297520V3_IRQ_H */ |