| b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ |
| 2 | * |
| 3 | * linux/sound/soc/hisilicon/hi3660-i2s.c |
| 4 | * |
| 5 | * I2S IP driver for hi3660. |
| 6 | * |
| 7 | * Copyright (c) 2001-2021, Huawei Tech. Co., Ltd. |
| 8 | * |
| 9 | */ |
| 10 | |
| 11 | #ifndef _HI3660_I2S_H |
| 12 | #define _HI3660_I2S_H |
| 13 | |
| 14 | enum hisi_bits { |
| 15 | HII2S_BITS_16, |
| 16 | HII2S_BITS_18, |
| 17 | HII2S_BITS_20, |
| 18 | HII2S_BITS_24, |
| 19 | }; |
| 20 | |
| 21 | enum hisi_i2s_rates { |
| 22 | HII2S_FS_RATE_8KHZ = 0, |
| 23 | HII2S_FS_RATE_16KHZ = 1, |
| 24 | HII2S_FS_RATE_32KHZ = 2, |
| 25 | HII2S_FS_RATE_48KHZ = 4, |
| 26 | HII2S_FS_RATE_96KHZ = 5, |
| 27 | HII2S_FS_RATE_192KHZ = 6, |
| 28 | }; |
| 29 | |
| 30 | #define HI_ASP_CFG_R_RST_CTRLEN_REG 0x0 |
| 31 | #define HI_ASP_CFG_R_RST_CTRLDIS_REG 0x4 |
| 32 | #define HI_ASP_CFG_R_GATE_EN_REG 0xC |
| 33 | #define HI_ASP_CFG_R_GATE_DIS_REG 0x10 |
| 34 | #define HI_ASP_CFG_R_GATE_CLKEN_REG 0x14 |
| 35 | #define HI_ASP_CFG_R_GATE_CLKSTAT_REG 0x18 |
| 36 | #define HI_ASP_CFG_R_GATE_CLKDIV_EN_REG 0x1C |
| 37 | #define HI_ASP_CFG_R_CLK1_DIV_REG 0x20 |
| 38 | #define HI_ASP_CFG_R_CLK2_DIV_REG 0x24 |
| 39 | #define HI_ASP_CFG_R_CLK3_DIV_REG 0x28 |
| 40 | #define HI_ASP_CFG_R_CLK4_DIV_REG 0x2C |
| 41 | #define HI_ASP_CFG_R_CLK5_DIV_REG 0x30 |
| 42 | #define HI_ASP_CFG_R_CLK6_DIV_REG 0x34 |
| 43 | #define HI_ASP_CFG_R_CLK_SEL_REG 0x38 |
| 44 | #define HI_ASP_CFG_R_SEC_REG 0x100 |
| 45 | |
| 46 | |
| 47 | #define HI_ASP_SIO_VERSION_REG (0x3C) |
| 48 | #define HI_ASP_SIO_MODE_REG (0x40) |
| 49 | #define HI_ASP_SIO_INTSTATUS_REG (0x44) |
| 50 | #define HI_ASP_SIO_INTCLR_REG (0x48) |
| 51 | #define HI_ASP_SIO_I2S_LEFT_XD_REG (0x4C) |
| 52 | #define HI_ASP_SIO_I2S_RIGHT_XD_REG (0x50) |
| 53 | #define HI_ASP_SIO_I2S_LEFT_RD_REG (0x54) |
| 54 | #define HI_ASP_SIO_I2S_RIGHT_RD_REG (0x58) |
| 55 | #define HI_ASP_SIO_CT_SET_REG (0x5C) |
| 56 | #define HI_ASP_SIO_CT_CLR_REG (0x60) |
| 57 | #define HI_ASP_SIO_RX_STA_REG (0x68) |
| 58 | #define HI_ASP_SIO_TX_STA_REG (0x6C) |
| 59 | #define HI_ASP_SIO_DATA_WIDTH_SET_REG (0x78) |
| 60 | #define HI_ASP_SIO_I2S_START_POS_REG (0x7C) |
| 61 | #define HI_ASP_SIO_I2S_POS_FLAG_REG (0x80) |
| 62 | #define HI_ASP_SIO_SIGNED_EXT_REG (0x84) |
| 63 | #define HI_ASP_SIO_I2S_POS_MERGE_EN_REG (0x88) |
| 64 | #define HI_ASP_SIO_INTMASK_REG (0x8C) |
| 65 | #define HI_ASP_SIO_I2S_DUAL_RX_CHN_REG (0xA0) |
| 66 | #define HI_ASP_SIO_I2S_DUAL_TX_CHN_REG (0xC0) |
| 67 | |
| 68 | |
| 69 | #define HI_ASP_CFG_R_CLK_SEL_EN BIT(2) |
| 70 | #define HI_ASP_CFG_R_CLK_SEL 0x140010 |
| 71 | #define HI_ASP_CFG_R_CLK1_DIV_SEL 0xbcdc9a |
| 72 | #define HI_ASP_CFG_R_CLK4_DIV_SEL 0x00ff000f |
| 73 | #define HI_ASP_CFG_R_CLK6_DIV_SEL 0x00ff003f |
| 74 | #define HI_ASP_CFG_SIO_MODE 0 |
| 75 | #define HI_ASP_SIO_MODE_SEL_EN BIT(0) |
| 76 | #define HI_ASP_MASK 0xffffffff |
| 77 | |
| 78 | #define HI_ASP_SIO_RX_ENABLE BIT(13) |
| 79 | #define HI_ASP_SIO_TX_ENABLE BIT(12) |
| 80 | #define HI_ASP_SIO_RX_FIFO_DISABLE BIT(11) |
| 81 | #define HI_ASP_SIO_TX_FIFO_DISABLE BIT(10) |
| 82 | #define HI_ASP_SIO_RX_DATA_MERGE BIT(9) |
| 83 | #define HI_ASP_SIO_TX_DATA_MERGE BIT(8) |
| 84 | #define HI_ASP_SIO_RX_FIFO_THRESHOLD (0x5 << 4) |
| 85 | #define HI_ASP_SIO_TX_FIFO_THRESHOLD (0xB << 0) |
| 86 | #define HI_ASP_SIO_RX_FIFO_THRESHOLD_CLR (0xF << 4) |
| 87 | #define HI_ASP_SIO_TX_FIFO_THRESHOLD_CLR (0xF << 0) |
| 88 | #define HI_ASP_SIO_BURST (0x4) |
| 89 | |
| 90 | |
| 91 | enum hisi_i2s_formats { |
| 92 | HII2S_FORMAT_I2S, |
| 93 | HII2S_FORMAT_PCM_STD, |
| 94 | HII2S_FORMAT_PCM_USER, |
| 95 | HII2S_FORMAT_LEFT_JUST, |
| 96 | HII2S_FORMAT_RIGHT_JUST, |
| 97 | }; |
| 98 | |
| 99 | #endif/* _HI3660_I2S_H */ |