marvell/obm/Common/Flash/QSPI/qspi_common.h

#ifndef _QSPI_COMMON_H
#define _QSPI_COMMON_H

// ---------------------------------------------------------------
// Memory Map
// ---------------------------------------------------------------
#define QSPI0_REG_BASE		0xd420B000 //QSPI1_IPS_BASE_ADDR
#define QSPI0_ARDB_BASE		0xa0000000 //AHB RX Data Buffer base addr(QSPI_ARDB0 to QSPI_ARDB31)
#define QSPI0_AMBA_BASE		0x80000000 //AHB base addr
#define QSPI0_FLASH_A1_BASE_Z1	0x80300000
#define QSPI0_FLASH_A1_TOP_Z1	0x88300000
#define QSPI0_FLASH_A1_BASE	0x80000000
#define QSPI0_FLASH_A1_TOP	0x88000000
#define QSPI0_FLASH_A2_BASE	0x88000000
#define QSPI0_FLASH_A2_TOP	0x90000000
#define QSPI0_FLASH_B1_BASE	0x90000000
#define QSPI0_FLASH_B1_TOP	0x98000000
#define QSPI0_FLASH_B2_BASE	0x98000000
#define QSPI0_FLASH_B2_TOP	0xa0000000

// ---------------------------------------------------------------
// Register definitions
// ---------------------------------------------------------------
#define QSPI_MCR_OFFSET		0x000
#define QSPI_IPCR_OFFSET	0x008
#define QSPI_FLSHCR_OFFSET	0x00C
#define QSPI_BUF0CR_OFFSET	0x010
#define QSPI_BUF1CR_OFFSET	0x014
#define QSPI_BUF2CR_OFFSET	0x018
#define QSPI_BUF3CR_OFFSET	0x01C
#define QSPI_BFGENCR_OFFSET	0x020
#define QSPI_SOCCR_OFFSET	0x024
#define QSPI_BUF0IND_OFFSET	0x030
#define QSPI_BUF1IND_OFFSET	0x034
#define QSPI_BUF2IND_OFFSET	0x038
#define QSPI_DLACR_OFFSET	0x03C
#define QSPI_SFAR_OFFSET	0x100
#define QSPI_SFACR_OFFSET	0x104
#define QSPI_SMPR_OFFSET	0x108
#define QSPI_RBSR_OFFSET	0x10C
#define QSPI_RBCT_OFFSET	0x110
#define QSPI_TBSR_OFFSET	0x150
#define QSPI_TBDR_OFFSET	0x154
#define QSPI_TBCT_OFFSET	0x158
#define QSPI_SR_OFFSET		0x15C
#define QSPI_FR_OFFSET		0x160
#define QSPI_RSER_OFFSET	0x164
#define QSPI_SPNDST_OFFSET	0x168
#define QSPI_SPTRCLR_OFFSET	0x16C
#define QSPI_SFA1AD_OFFSET	0x180
#define QSPI_SFA2AD_OFFSET	0x184
#define QSPI_SFB1AD_OFFSET	0x188
#define QSPI_SFB2AD_OFFSET	0x18C
#define QSPI_DLPV_OFFSET	0x190
#define QSPI_RBDR0_OFFSET	0x200
#define QSPI_LUTKEY_OFFSET	0x300
#define QSPI_LCKCR_OFFSET	0x304
#define QSPI_LUT0_OFFSET	0x310
#define QSPI_LUT1_OFFSET	0x314
#define QSPI_LUT2_OFFSET	0x318
#define QSPI_LUT3_OFFSET	0x31C

// ---------------------------------------------------------------
// Register definitions 
// ---------------------------------------------------------------
#define QSPI0_MCR		(QSPI0_REG_BASE + QSPI_MCR_OFFSET)
#define QSPI0_IPCR		(QSPI0_REG_BASE + QSPI_IPCR_OFFSET)
#define QSPI0_FLSHCR		(QSPI0_REG_BASE + QSPI_FLSHCR_OFFSET)
#define QSPI0_BUF0CR		(QSPI0_REG_BASE + QSPI_BUF0CR_OFFSET)
#define QSPI0_BUF1CR		(QSPI0_REG_BASE + QSPI_BUF1CR_OFFSET)
#define QSPI0_BUF2CR		(QSPI0_REG_BASE + QSPI_BUF2CR_OFFSET)
#define QSPI0_BUF3CR		(QSPI0_REG_BASE + QSPI_BUF3CR_OFFSET)
#define QSPI0_BFGENCR		(QSPI0_REG_BASE + QSPI_BFGENCR_OFFSET)
#define QSPI0_SOCCR		(QSPI0_REG_BASE + QSPI_SOCCR_OFFSET)
#define QSPI0_BUF0IND		(QSPI0_REG_BASE + QSPI_BUF0IND_OFFSET)
#define QSPI0_BUF1IND		(QSPI0_REG_BASE + QSPI_BUF1IND_OFFSET)
#define QSPI0_BUF2IND		(QSPI0_REG_BASE + QSPI_BUF2IND_OFFSET)
#define QSPI0_DLACR		(QSPI0_REG_BASE + QSPI_DLACR_OFFSET)
#define QSPI0_SFAR		(QSPI0_REG_BASE + QSPI_SFAR_OFFSET)
#define QSPI0_SFACR		(QSPI0_REG_BASE + QSPI_SFACR_OFFSET)
#define QSPI0_SMPR		(QSPI0_REG_BASE + QSPI_SMPR_OFFSET)
#define QSPI0_RBSR		(QSPI0_REG_BASE + QSPI_RBSR_OFFSET)
#define QSPI0_RBCT		(QSPI0_REG_BASE + QSPI_RBCT_OFFSET)
#define QSPI0_TBSR		(QSPI0_REG_BASE + QSPI_TBSR_OFFSET)
#define QSPI0_TBDR		(QSPI0_REG_BASE + QSPI_TBDR_OFFSET)
#define QSPI0_TBCT		(QSPI0_REG_BASE + QSPI_TBCT_OFFSET)
#define QSPI0_SR		(QSPI0_REG_BASE + QSPI_SR_OFFSET)
#define QSPI0_FR		(QSPI0_REG_BASE + QSPI_FR_OFFSET)
#define QSPI0_RSER		(QSPI0_REG_BASE + QSPI_RSER_OFFSET)
#define QSPI0_SPNDST		(QSPI0_REG_BASE + QSPI_SPNDST_OFFSET)
#define QSPI0_SPTRCLR		(QSPI0_REG_BASE + QSPI_SPTRCLR_OFFSET)
#define QSPI0_SFA1AD		(QSPI0_REG_BASE + QSPI_SFA1AD_OFFSET)
#define QSPI0_SFA2AD		(QSPI0_REG_BASE + QSPI_SFA2AD_OFFSET)
#define QSPI0_SFB1AD		(QSPI0_REG_BASE + QSPI_SFB1AD_OFFSET)
#define QSPI0_SFB2AD		(QSPI0_REG_BASE + QSPI_SFB2AD_OFFSET)
#define QSPI0_DLPV		(QSPI0_REG_BASE + QSPI_DLPV_OFFSET)
#define QSPI0_RBDR0		(QSPI0_REG_BASE + QSPI_RBDR0_OFFSET)
#define QSPI0_LUTKEY		(QSPI0_REG_BASE + QSPI_LUTKEY_OFFSET)
#define QSPI0_LCKCR		(QSPI0_REG_BASE + QSPI_LCKCR_OFFSET)
#define QSPI0_LUT0		(QSPI0_REG_BASE + QSPI_LUT0_OFFSET)
#define QSPI0_LUT1		(QSPI0_REG_BASE + QSPI_LUT1_OFFSET)
#define QSPI0_LUT2		(QSPI0_REG_BASE + QSPI_LUT2_OFFSET)
#define QSPI0_LUT3		(QSPI0_REG_BASE + QSPI_LUT3_OFFSET)

#define QSPI_SFACR_RESV			(0x7fff << 17 | 0xfff << 4)

#define QSPI_IPCR_SEQID_SHIFT		24
#define QSPI_IPCR_SEQID_MASK		(0xf << QSPI_IPCR_SEQID_SHIFT)
#define QSPI_IPCR_RESV			(0xf << 28 | 0x7f << 17)

#define QSPI_FLSHCR_TDH_SHIFT		16
#define QSPI_FLSHCR_TDH_MASK		(0x3 << QSPI_FLSHCR_TDH_SHIFT)
#define QSPI_FLSHCR_TDH_HALF_2X		(0x1 << QSPI_FLSHCR_TDH_SHIFT)
#define QSPI_FLSHCR_TDH_HALF_4X		(0x2 << QSPI_FLSHCR_TDH_SHIFT)

#define QSPI_MCR_END_CFD_SHIFT		2
#define QSPI_MCR_END_CFD_MASK		(3 << QSPI_MCR_END_CFD_SHIFT)
#define QSPI_MCR_END_CFD_LE		(3 << QSPI_MCR_END_CFD_SHIFT)
#define QSPI_MCR_DQS_EN			BIT6
#define QSPI_MCR_DDR_EN			BIT7
#define QSPI_MCR_CLR_RXF		BIT10
#define QSPI_MCR_CLR_TXF		BIT11
#define QSPI_MCR_MDIS			BIT14
#define QSPI_MCR_DQS_LP_EN		BIT25
#define QSPI_MCR_DQS_INV_EN		BIT26
#define QSPI_MCR_ISDX_SHIFT		16
#define QSPI_MCR_ISDX_MASK		(0xf << QSPI_MCR_ISDX_SHIFT)
#define QSPI_MCR_SWRSTHD		BIT1
#define QSPI_MCR_SWRSTSD		BIT0
#define QSPI_MCR_RESV			(0xf << 20 | 0x3 << 12 | 0x3 << 8 | 0x1 << 4)

#define QSPI_SMPR_HSENA			BIT0
#define QSPI_SMPR_FSPHS			BIT5
#define QSPI_SMPR_FSDLY			BIT6
#define QSPI_SMPR_DDRSMP_SHIFT		16
#define QSPI_SMPR_DDRSMP_MASK		(7 << QSPI_SMPR_DDRSMP_SHIFT)

#define QSPI_BUFXCR_INVALID_MSTRID	0xe
#define QSPI_BUF3CR_ALLMST		BIT31
#define QSPI_BUF3CR_ADATSZ_SHIFT	8
#define QSPI_BUF3CR_ADATSZ_MASK		(0xFF << QSPI_BUF3CR_ADATSZ_SHIFT)

#define QSPI_BFGENCR_SEQID_SHIFT	12
#define QSPI_BFGENCR_SEQID_MASK		(0xf << QSPI_BFGENCR_SEQID_SHIFT)
#define QSPI_BFGENCR_PAR_EN		BIT16

#define QSPI_SOCCR_DLINE_EN		BIT8
#define QSPI_DLACR_DLINE_CODE_SHIFT	0
#define QSPI_DLACR_DLINE_CODE_MASK	(0xFF << QSPI_DLACR_DLINE_CODE_SHIFT)
#define QSPI_DLACR_DLINE_STEP_SHIFT	8
#define QSPI_DLACR_DLINE_STEP_MASK	(0xFF << QSPI_DLACR_DLINE_STEP_SHIFT)

#define QSPI_RBSR_RDBFL_SHIFT		8
#define QSPI_RBSR_RDBFL_MASK		(0x3f << QSPI_RBSR_RDBFL_SHIFT)

#define QSPI_RBCT_RXBRD			BIT8
#define QSPI_RBCT_WMRK_SHITT		0
#define QSPI_RBCT_WMRK_MASK		(0x1f << QSPI_RBCT_WMRK_SHITT)
#define QSPI_RBCT_RESV			(0x7fffff << 9 | 0x7 << 5)

#define QSPI_TBCT_WMRK_SHITT		0
#define QSPI_TBCT_WMRK_MASK		(0x1f << QSPI_TBCT_WMRK_SHITT)
#define QSPI_TBCT_RESV			(~0x1f)

#define QSPI_SR_TXFULL			BIT27
#define QSPI_SR_TXDMA			BIT26
#define QSPI_SR_TXWA			BIT25
#define QSPI_SR_TXEDA			BIT24
#define QSPI_SR_RXDMA			BIT23
#define QSPI_SR_RXFULL			BIT19
#define QSPI_SR_RXWE			BIT16
#define QSPI_SR_AHB_ACC			BIT2
#define QSPI_SR_IP_ACC			BIT1
#define QSPI_SR_BUSY			BIT0

#define QSPI_FR_DLPFF			BIT31
#define QSPI_FR_TBFF			BIT27
#define QSPI_FR_TBUF			BIT26
#define QSPI_FR_ILLINE			BIT23
#define QSPI_FR_RBOF			BIT17
#define QSPI_FR_RBDF			BIT16
#define QSPI_FR_ABSEF			BIT15
#define QSPI_FR_AITEF			BIT14
#define QSPI_FR_AIBSEF			BIT13
#define QSPI_FR_ABOF			BIT12
#define QSPI_FR_IUEF			BIT11
#define QSPI_FR_IPAEF			BIT7
#define QSPI_FR_IPIEF			BIT6
#define QSPI_FR_IPGEF			BIT4
#define QSPI_FR_TFF			BIT0

#define QSPI_RSER_DLPFIE		BIT31
#define QSPI_RSER_TBFIE			BIT27
#define QSPI_RSER_TBUIE			BIT26
#define QSPI_RSER_TBFDE			BIT25
#define QSPI_RSER_ILLINIE		BIT23
#define QSPI_RSER_RBDDE			BIT21
#define QSPI_RSER_RBOIE			BIT17
#define QSPI_RSER_RBDIE			BIT16
#define QSPI_RSER_ABSEIE		BIT15
#define QSPI_RSER_AITIE			BIT14
#define QSPI_RSER_AIBSIE		BIT13
#define QSPI_RSER_ABOIE			BIT12
#define QSPI_RSER_IUEIE			BIT11
#define QSPI_RSER_IPIEIE		BIT6
#define QSPI_RSER_IPGEIE		BIT4
#define QSPI_RSER_TFIE			BIT0
#define QSPI_RSER_RESV			(0x7 << 28 | 0x1 << 24 | 0x1 << 22 | \
					 0x7 << 18 | 0x7 << 8 | 0x1 << 5 | \
					 0x7 << 1)

#define QSPI_SPTRCLR_IPPTRC		BIT8
#define QSPI_SPTRCLR_RESV		(0x7fffff << 9 | 0x7f << 1)

#define QSPI_LCKCR_LOCK			BIT0
#define QSPI_LCKCR_UNLOCK		BIT1

#define LUT_KEY_VALUE			0x5af05af0

// ---------------------------------------------------------------
// Enumeration & Structure
// ---------------------------------------------------------------
enum QSPI_INST_E {
	QSPI_INSTR_STOP		= 0x0,
	QSPI_INSTR_CMD		= 0x1,
	QSPI_INSTR_ADDR		= 0x2,
	QSPI_INSTR_DUMMY	= 0x3,
	QSPI_INSTR_MODE		= 0x4,
	QSPI_INSTR_MODE2	= 0x5,
	QSPI_INSTR_MODE4	= 0x6,
	QSPI_INSTR_READ		= 0x7,
	QSPI_INSTR_WRITE	= 0x8,
	QSPI_INSTR_JMP_ON_CS	= 0x9,
	QSPI_INSTR_ADDR_DDR	= 0xA,
	QSPI_INSTR_MODE_DDR	= 0xB,
	QSPI_INSTR_MODE2_DDR	= 0xC,
	QSPI_INSTR_MODE4_DDR	= 0xD,
	QSPI_INSTR_READ_DDR	= 0xE,
	QSPI_INSTR_WRITE_DDR	= 0xF,
	QSPI_INSTR_DATA_LEARN	= 0x10,
	QSPI_INSTR_CMD_DDR	= 0x11,
};

enum QSPI_PAD_E {
	QSPI_PAD_1X = 0x0,
	QSPI_PAD_2X = 0x1,
	QSPI_PAD_4X = 0x2,
	QSPI_PAD_RSVD = 0x3
};

#define	EIO		5	/* I/O error */
#define	EAGAIN		11	/* Try again */
#define	ENOMEM		12	/* Out of memory */
#define	ENODEV		19	/* No such device */
#define	EINVAL		22	/* Invalid argument */
#define	EBADMSG		74	/* Not a data message */
#define	ETIMEDOUT	110	/* Connection timed out */
#define	EUCLEAN		117	/* Chip needs cleaning */
#define ENOTSUPP	524	/* Operation is not supported */

#endif // QSPI_COMMON_H