| b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 1 | /****************************************************************************** |
| 2 | * |
| 3 | * (C)Copyright 2005 - 2012 Marvell. All Rights Reserved. |
| 4 | * |
| 5 | * THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MARVELL. |
| 6 | * The copyright notice above does not evidence any actual or intended |
| 7 | * publication of such source code. |
| 8 | * This Module contains Proprietary Information of Marvell and should be |
| 9 | * treated as Confidential. |
| 10 | * The information in this file is provided for the exclusive use of the |
| 11 | * licensees of Marvell. |
| 12 | * Such users have the right to use, modify, and incorporate this code into |
| 13 | * products for purposes authorized by the license agreement provided they |
| 14 | * include this notice and the associated copyright notice with any such |
| 15 | * product. |
| 16 | * The information in this file is provided "AS IS" without warranty. |
| 17 | * |
| 18 | ******************************************************************************/ |
| 19 | #ifndef __SPI_NOR_H__ |
| 20 | #define __SPI_NOR_H__ |
| 21 | |
| 22 | #include "Typedef.h" |
| 23 | #include "Flash.h" |
| 24 | #include "SSP.h" |
| 25 | #include "predefines.h" |
| 26 | |
| 27 | /* |
| 28 | * SPI Command Set |
| 29 | */ |
| 30 | #define SPI_CMD_JEDEC_ID 0x9F |
| 31 | #define SPI_CMD_RELEASE_POWER_DOWN 0xAB |
| 32 | #define SPI_CMD_READ_STATUS 0x05 |
| 33 | #define SPI_CMD_WRITE_ENABLE 0x06 |
| 34 | #define SPI_CMD_WRITE_STATUS_REG 0x01 |
| 35 | #define SPI_CMD_PROGRAM 0x02 |
| 36 | #define SPI_CMD_READ 0x03 |
| 37 | #define SPI_CMD_SECTOR_ERASE 0xd8 |
| 38 | #define SPI_CMD_CHIP_ERASE 0xc7 |
| 39 | |
| 40 | #define WRTIE_ENABLE_LATCH_BIT BIT1 |
| 41 | |
| 42 | typedef enum |
| 43 | { |
| 44 | SPINOR_4bytes_Status_Register = 0, |
| 45 | SPINOR_write_enable_Status_Register = 1 |
| 46 | }SPINOR_Register; |
| 47 | |
| 48 | |
| 49 | // Specific Manufactorer ID's |
| 50 | typedef enum { |
| 51 | MICRON_ID = 0x2C, |
| 52 | MACRONIX_ID = 0xC2, |
| 53 | GIGADEVICE_ID = 0xC8, |
| 54 | SPANSION_ID = 0x01, |
| 55 | FIDELIX_ID = 0xF8 |
| 56 | }SPINOR_MANUFACTURER_ID; |
| 57 | |
| 58 | |
| 59 | typedef struct{ |
| 60 | unsigned char large_capacity; // 32MB? |
| 61 | unsigned char enable_4bytes; // enable 4bytes mode for the second 16MB memory |
| 62 | unsigned char write_enable_4enable_4bytes; // send write enable cmd before enable 4bytes mode |
| 63 | unsigned char read_4bytes_cmd; // read cmd |
| 64 | unsigned char write_4bytes_cmd; // write cmd |
| 65 | unsigned char erase_4bytes_cmd; // erase cmd |
| 66 | unsigned char read_4bytes_status_cmd; // read status cmd for 4bytes enabled |
| 67 | unsigned char spi_4bytes_enabled_bit; // 4bytes mode enabled |
| 68 | } SPINOR_T, *P_SPINOR_T; |
| 69 | |
| 70 | |
| 71 | UINT_T InitializeSPIDevice(UINT8_T FlashNum, UINT8_T* P_DefaultPartitionNum); |
| 72 | UINT_T SPINOR_Read(UINT_T FlashOffset, UINT_T Buffer, UINT_T Size); |
| 73 | UINT_T SPINOR_Write(UINT_T Address, UINT_T Buffer, UINT_T Size); |
| 74 | UINT_T SPINOR_Erase(UINT_T Address, UINT_T Size); |
| 75 | UINT_T SPINOR_Wipe(void); |
| 76 | void SPINOR_Reset(void); |
| 77 | void SPINOR_ReadStatus(UINT_T Wait); |
| 78 | void SPINOR_WriteEnable(void); |
| 79 | void SPINOR_WriteStatus(unsigned char status); |
| 80 | void SPINOR_Enable4BytesMode(void); |
| 81 | void SPINOR_Disable4BytesMode(void); |
| 82 | void SPINOR_Protect_Blocks(void); |
| 83 | void SPINOR_UnProtectBlocks(void); |
| 84 | void SPINOR_ResetEnable(void); |
| 85 | void SPINOR_ResetMemory(void); |
| 86 | |
| 87 | #endif |
| 88 | |
| 89 | |