Gitiles
Code Review Sign In
192.168.1.100 / T108 / c2023d5d03be91dbb983606f0ec5e9e4ea36c8c2 / . / marvell / uboot / drivers / mtd / spi-flash / spi_nand.c
blob: 6bd5aa97bf936a45b6b16db0b0a260e57ea096e8 [file] [log] [blame]
b.liue9582032025-04-17 19:18:16 +0800[diff] [blame]1#include <common.h>
2#include <malloc.h>
3#include <linux/mtd/mtd.h>
4#include <asm-generic/errno.h>
5#include <mtd/pxa3xx_bbm.h>
6#include <linux/mtd/bbm.h>
7#include <linux/mtd/nand.h>
8#include <ubi_uboot.h>
9#include <spi_flash_chip.h>
10#include <spi_nand.h>
11
12#define OOB_REQ_ALIGN_TO_SPARE_LEN
13
14static void generic_spi_nand_ecc_status(struct spi_flash_chip *chip, u8 status,
15 u32 *corrected, u32 *ecc_error);
16static void mxic_spi_nand_ecc_status(struct spi_flash_chip *chip, u8 status,
17 u32 *corrected, u32 *ecc_error);
18static void mxic2_spi_nand_ecc_status(struct spi_flash_chip *chip, u8 status,
19 u32 *corrected, u32 *ecc_error);
20static void micron_spi_nand_ecc_status(struct spi_flash_chip *chip, u8 status,
21 u32 *corrected, u32 *ecc_error);
22static void gd_spi_nand_ecc_status(struct spi_flash_chip *chip, u8 status,
23 u32 *corrected, u32 *ecc_error);
24static void gd_spi_nand_ecc_status2(struct spi_flash_chip *chip, u8 status,
25 u32 *corrected, u32 *ecc_error);
26static void xtx_spi_nand_ecc_status(struct spi_flash_chip *chip, u8 status,
27 u32 *corrected, u32 *ecc_error);
28static void xtx2_spi_nand_ecc_status(struct spi_flash_chip *chip, u8 status,
29 u32 *corrected, u32 *ecc_error);
30static void yxsc_spi_nand_ecc_status(struct spi_flash_chip *chip, u8 status,
31 u32 *corrected, u32 *ecc_error);
32static void fm_spi_nand_ecc_status(struct spi_flash_chip *chip, u8 status,
33 u32 *corrected, u32 *ecc_error);
34static void wb_spi_nand_ecc_status(struct spi_flash_chip *chip, u8 status,
35 u32 *corrected, u32 *ecc_error);
36static void wb_spi_nand_ecc_status2(struct spi_flash_chip *chip, u8 status,
37 u32 *corrected, u32 *ecc_error);
38static int spi_nand_erase(struct mtd_info *mtd, struct erase_info *einfo);
39
40/**
41* Default OOB area specification layout
42*/
43static struct nand_ecclayout ecc_layout_64 = {
44 .eccbytes = 32,
45 .eccpos = {
46 8, 9, 10, 11, 12, 13, 14, 15,
47 24, 25, 26, 27, 28, 29, 30, 21,
48 40, 41, 42, 43, 44, 45, 46, 47,
49 56, 57, 58, 59, 60, 61, 62, 63},
50 .oobavail = 30,
51 .oobfree = {
52 {.offset = 2,
53 .length = 6},
54 {.offset = 16,
55 .length = 8},
56 {.offset = 32,
57 .length = 8},
58 {.offset = 48,
59 .length = 8}, }
60};
61
62static struct nand_ecclayout wb_ecc_layout_64 = {
63 .eccbytes = 0,
64 .oobavail = 62,
65 .oobfree = {
66 {.offset = 2,
67 .length = 62},}
68};
69
70static struct nand_ecclayout ecc_layout_128 = {
71 .eccbytes = 64,
72 .eccpos = {
73 64, 65, 66, 67, 68, 69, 70, 71,
74 72, 73, 74, 75, 76, 77, 78, 79,
75 80, 81, 82, 83, 84, 85, 86, 87,
76 88, 89, 90, 91, 92, 93, 94, 95,
77 96, 97, 98, 99, 100, 101, 102, 103,
78 104, 105, 106, 107, 108, 109, 110, 111,
79 112, 113, 114, 115, 116, 117, 118, 119,
80 120, 121, 122, 123, 124, 125, 126, 127},
81 .oobavail = 62,
82 .oobfree = {
83 {.offset = 2,
84 .length = 62}, }
85};
86
87static struct nand_ecclayout xtx_ecc_layout_128 = {
88 .eccbytes = 52,
89 .eccpos = {
90 6, 7, 8, 9, 10, 11, 12, 13,
91 14, 15, 16, 17, 18, 21, 22, 23,
92 24, 25, 26, 27, 28, 29, 30, 31,
93 32, 33, 36, 37, 38, 39, 40, 41,
94 42, 43, 44, 45, 46, 47, 48, 51,
95 52, 53, 54, 55, 56, 57, 58, 59,
96 60, 61, 62, 63},
97 .oobavail = 74,
98 .oobfree = {
99 {.offset = 2,
100 .length = 4},
101 {.offset = 19,
102 .length = 2},
103 {.offset = 34,
104 .length = 2},
105 {.offset = 49,
106 .length = 2},
107 {.offset = 64,
108 .length = 64}, }
109};
110
b.liub17525e2025-05-14 17:22:29 +0800[diff] [blame]111// Add by mbtk
112static struct nand_ecclayout xtx_ecc_layout_256 = {
113 .eccbytes = 52,
114 .eccpos = {
115 6, 7, 8, 9, 10, 11, 12, 13,
116 14, 15, 16, 17, 18, 21, 22, 23,
117 24, 25, 26, 27, 28, 29, 30, 31,
118 32, 33, 36, 37, 38, 39, 40, 41,
119 42, 43, 44, 45, 46, 47, 48, 51,
120 52, 53, 54, 55, 56, 57, 58, 59,
121 60, 61, 62, 63},
122 .oobavail = 74,
123 .oobfree = {
124 {.offset = 2,
125 .length = 4},
126 {.offset = 19,
127 .length = 2},
128 {.offset = 34,
129 .length = 2},
130 {.offset = 49,
131 .length = 2},
132 {.offset = 64,
133 .length = 64}, }
134};
135
136static struct nand_ecclayout esmt_ecc_layout_256 = {
137 .eccbytes = 128,
138 .eccpos = {
139 128, 129, 130, 131, 132, 133, 134, 135,
140 136, 137, 138, 139, 140, 141, 142, 143,
141 144, 145, 146, 147, 148, 149, 150, 151,
142 152, 153, 154, 155, 156, 157, 158, 159,
143 160, 161, 162, 163, 164, 165, 166, 167,
144 168, 169, 170, 171, 172, 173, 174, 175,
145 176, 177, 178, 179, 180, 181, 182, 183,
146 184, 185, 186, 187, 188, 189, 190, 191,
147 192, 193, 194, 195, 196, 197, 198, 199,
148 200, 201, 202, 203, 204, 205, 206, 207,
149 208, 209, 210, 211, 212, 213, 214, 215,
150 216, 217, 218, 219, 220, 221, 222, 223,
151 224, 225, 226, 227, 228, 229, 230, 231,
152 232, 233, 234, 235, 236, 237, 238, 239,
153 240, 241, 242, 243, 244, 245, 246, 247,
154 248, 249, 250, 251, 252, 253, 254, 255},
155 .oobavail = 124,
156 .oobfree = {
157 {.offset = 4,
158 .length = 124},
159 }
160};
161
b.liue9582032025-04-17 19:18:16 +0800[diff] [blame]162enum {
163 GET_FEATURE,
164 SET_FEATURE,
165 PAGE_READ,
166 READ_PAGE_CACHE_RDM,
167 READ_PAGE_CACHE_LAST,
168 READ_FROM_CACHE,
169 READ_FROM_CACHE_FAST,
170 READ_FROM_CACHE_X2,
171 READ_FROM_CACHE_DUAL,
172 READ_FROM_CACHE_X4,
173 READ_FROM_CACHE_QUAD,
174 READ_FROM_CACHE_DTR,
175 BLK_ERASE,
176 PROG_EXC,
177 PROG_LOAD,
178 PROG_LOAD_RDM_DATA,
179 PROG_LOAD_X4,
180 PROG_LOAD_RDM_DATA_X4,
181 WR_ENABLE,
182 WR_DISABLE,
183 READ_ID,
184 RESET,
185 READ_FROM_CACHE_QUAD_GD,
186 READ_FROM_CACHE_QUAD_GD2,
187 READ_ECCSR_MXIC,
188 MAX_CMD,
189};
190
191static struct spi_nand_info spi_nand_table[] = {
192 /* Macronix */
193 SPI_NAND_INFO("MX35UF1GE4AC", 0xC2, 0x92, 2048, 64, 64, 1024,
194 1, 4, SPINAND_NEED_SET_BFT, 3, 0,
195 READ_FROM_CACHE_QUAD,
196 &ecc_layout_64, mxic_spi_nand_ecc_status),
197 SPI_NAND_INFO("MX35UF2GE4AC", 0xC2, 0xA2, 2048, 64, 64, 2048,
198 1, 4, SPINAND_NEED_SET_BFT, 3, 0,
199 READ_FROM_CACHE_QUAD,
200 &ecc_layout_64, mxic_spi_nand_ecc_status),
201 SPI_NAND_INFO("MX35UF1GE4AD", 0xC2, 0x96, 2048, 128, 64, 1024,
202 1, 8, SPINAND_NEED_SET_BFT, 6, 0,
203 READ_FROM_CACHE_QUAD,
204 &ecc_layout_128, mxic2_spi_nand_ecc_status),
205 SPI_NAND_INFO("MX35UF2GE4AD", 0xC2, 0xA6, 2048, 128, 64, 2048,
206 1, 8, SPINAND_NEED_SET_BFT, 6, 0,
207 READ_FROM_CACHE_QUAD,
208 &ecc_layout_128, mxic2_spi_nand_ecc_status),
209
210 /* GigaDeivce 1.8V */
211 SPI_NAND_INFO("GD5F1GQ4RBxIG", 0xC8, 0xC1, 2048, 128, 64, 1024,
212 1, 8, 0, 6, 0, READ_FROM_CACHE_QUAD_GD,
213 &ecc_layout_128, gd_spi_nand_ecc_status),
214 SPI_NAND_INFO("GD5F2GQ4RBxIG", 0xC8, 0xC2, 2048, 128, 64, 2048,
215 1, 8, 0, 6, 0, READ_FROM_CACHE_QUAD_GD,
216 &ecc_layout_128, gd_spi_nand_ecc_status),
217 SPI_NAND_INFO("GD5F1GQ5RExxG", 0xC8, 0x41, 2048, 128, 64, 1024,
218 1, 4, 0, 3, 0, READ_FROM_CACHE_QUAD,
219 &ecc_layout_128, gd_spi_nand_ecc_status2),
220 SPI_NAND_INFO("GD5F2GQ5RExxG", 0xC8, 0x42, 2048, 128, 64, 2048,
221 1, 4, 0, 3, 0, READ_FROM_CACHE_QUAD_GD2,
222 &ecc_layout_128, gd_spi_nand_ecc_status2),
223#if 1
224 SPI_NAND_INFO_DTR("GD5F1GM7RE", 0xC8, 0x81, 2048, 128, 64, 1024,
225 1, 8, SPINAND_SUPPORT_DTR, 6, 9, 2, 2, 80,
226 READ_FROM_CACHE_QUAD, READ_FROM_CACHE_DTR,
227 &ecc_layout_128, gd_spi_nand_ecc_status),
228#else
229 SPI_NAND_INFO_TIMING("GD5F1GM7RE", 0xC8, 0x81, 2048, 128, 64, 1024,
230 1, 8, 0, 6, 9, 2, 2, 0, READ_FROM_CACHE_QUAD,
231 &ecc_layout_128, gd_spi_nand_ecc_status),
232#endif
233 SPI_NAND_INFO("GD5F2GM7RE", 0xC8, 0x82, 2048, 128, 64, 2048,
234 1, 8, 0, 6, 0, READ_FROM_CACHE_QUAD,
235 &ecc_layout_128, gd_spi_nand_ecc_status),
236 SPI_NAND_INFO_TIMING("GD5F4GQ6RExxG", 0xC8, 0x45, 2048, 128, 64, 2048,
237 2, 4, 0, 3, 11, 2, 2, 0, READ_FROM_CACHE_QUAD_GD2,
238 &ecc_layout_128, gd_spi_nand_ecc_status2),
239 SPI_NAND_INFO("GD5F4GM8RExxG", 0xC8, 0x85, 2048, 128, 64, 4096,
240 1, 8, 0, 6, 0, READ_FROM_CACHE_QUAD,
241 &ecc_layout_128, gd_spi_nand_ecc_status),
b.liub17525e2025-05-14 17:22:29 +0800[diff] [blame]242 /*add by mbtk_tanggaoyou for GD5F4GM8RExxG:DID=0x85,pgsz=2k,blksz=64*pgsz,lun=1,ecc_strength=8*/
243 SPI_NAND_INFO_TIMING("GD5F4GM8RExxG", 0xC8, 0x85, 2048, 128, 64, 4096,
244 1, 8, 0, 6, 9, 2, 2, 0,READ_FROM_CACHE_X4,
245 &ecc_layout_128,gd_spi_nand_ecc_status),
b.liue9582032025-04-17 19:18:16 +0800[diff] [blame]246 /* GigaDeivce 3.3V */
247 SPI_NAND_INFO("GD5F1GQ4UExxG", 0xC8, 0xD1, 2048, 128, 64, 1024,
248 1, 8, 0, 6, 0, READ_FROM_CACHE_QUAD_GD,
249 &ecc_layout_128, gd_spi_nand_ecc_status),
250
251 /* Winbond */
252 SPI_NAND_INFO("W25N512GWxxR/T", 0xEF, 0x20BA, 2048, 64, 64, 512,
253 1, 4, 0, 4, 0, READ_FROM_CACHE_QUAD,
254 &ecc_layout_64, generic_spi_nand_ecc_status),
255 SPI_NAND_INFO("W25N01GWxxIx", 0xEF, 0x21BA, 2048, 64, 64, 1024,
256 1, 4, 0, 4, 0, READ_FROM_CACHE_QUAD,
257 &ecc_layout_64, generic_spi_nand_ecc_status),
258 SPI_NAND_INFO("W25N01KW", 0xEF, 0x21BE, 2048, 64, 64, 1024,
259 1, 4, 0, 3, 0, READ_FROM_CACHE_QUAD,
260 &wb_ecc_layout_64, wb_spi_nand_ecc_status),
261 SPI_NAND_INFO("W25N02KW", 0xEF, 0x22BA, 2048, 64, 64, 2048,
262 1, 8, 0, 6, 0, READ_FROM_CACHE_QUAD,
263 &wb_ecc_layout_64, wb_spi_nand_ecc_status2),
264 SPI_NAND_INFO("W25M02GWxxIx", 0xEF, 0x21BB, 2048, 64, 64, 2048,
265 1, 4, 0, 4, 0, READ_FROM_CACHE_QUAD,
266 &ecc_layout_64, generic_spi_nand_ecc_status),
267 SPI_NAND_INFO("W25M01JW", 0xEF, 0x21BC, 2048, 64, 64, 1024,
268 1, 4, 0, 4, 0, READ_FROM_CACHE_QUAD,
269 &ecc_layout_64, generic_spi_nand_ecc_status),
270
271 /* Dosilicon */
272 SPI_NAND_INFO("DS35M1GAxx", 0xE5, 0x21, 2048, 64, 64, 1024,
273 1, 4, 0, 4, 0, READ_FROM_CACHE_X4,
274 &ecc_layout_64, generic_spi_nand_ecc_status),
275 SPI_NAND_INFO("DS35M2GAxx", 0xE5, 0x22, 2048, 64, 64, 2048,
276 1, 4, SPINAND_NEED_PLANE_SELECT, 4, 0,
277 READ_FROM_CACHE_X4,
278 &ecc_layout_64, generic_spi_nand_ecc_status),
279 SPI_NAND_INFO("DS35M2GBxx", 0xE5, 0xA2, 2048, 128, 64, 2048,
280 1, 8, SPINAND_NEED_PLANE_SELECT, 4, 83,
281 READ_FROM_CACHE_X4,
282 &ecc_layout_128, micron_spi_nand_ecc_status),
283 SPI_NAND_INFO("DS35M4GMxx", 0xE5, 0xA4, 2048, 128, 64, 4096,
284 1, 8, SPINAND_NEED_PLANE_SELECT, 4, 83,
285 READ_FROM_CACHE_X4,
286 &ecc_layout_128, micron_spi_nand_ecc_status),
287 SPI_NAND_INFO("DS35M4GMxx", 0xE5, 0xA4, 2048, 128, 64, 4096,
288 1, 8, SPINAND_NEED_PLANE_SELECT, 4, 83,
289 READ_FROM_CACHE_X4,
290 &ecc_layout_128, micron_spi_nand_ecc_status),
291
292 /* ZettaDevice */
293 SPI_NAND_INFO("ZD35M1GAxx", 0xBA, 0x21, 2048, 64, 64, 1024,
294 1, 4, 0, 4, 0, READ_FROM_CACHE_X4,
295 &ecc_layout_64, generic_spi_nand_ecc_status),
296
297 /* XTX */
298 SPI_NAND_INFO("PN26Q01AWSIUG", 0xA1, 0xC1, 2048, 128, 64, 1024,
299 1, 8, SPINAND_RDM_CMD_NEED_PAGE_READ | SPINAND_ECC_EN_ADDR_90H,
300 8, 52, READ_FROM_CACHE_X4,
301 &xtx_ecc_layout_128, xtx_spi_nand_ecc_status),
302 SPI_NAND_INFO("XT26Q01D-BE", 0x0B, 0x51, 2048, 128, 64, 1024,
303 1, 8, 0, 5, 0, READ_FROM_CACHE_QUAD_GD,
304 &xtx_ecc_layout_128, xtx2_spi_nand_ecc_status),
305 SPI_NAND_INFO("XT26Q02D", 0x0B, 0x52, 2048, 128, 64, 2048,
306 1, 8, 0, 5, 0, READ_FROM_CACHE_QUAD_GD,
307 &ecc_layout_128, xtx2_spi_nand_ecc_status),
308 SPI_NAND_INFO("XT26Q02E", 0x2C, 0x25, 2048, 128, 64, 2048,
309 1, 8, SPINAND_NEED_PLANE_SELECT, 4, 52,
310 READ_FROM_CACHE_QUAD,
311 &ecc_layout_128, micron_spi_nand_ecc_status),
312
313 /* YXSC */
314 SPI_NAND_INFO("TX25G01", 0xA1, 0xF1, 2048, 64, 64, 1024,
315 1, 4, SPINAND_RDM_CMD_NEED_PAGE_READ | SPINAND_ECC_EN_ADDR_90H,
316 2, 0, READ_FROM_CACHE_QUAD_GD,
317 &ecc_layout_64, yxsc_spi_nand_ecc_status),
318 /* ESMT */
319 SPI_NAND_INFO("F50D1G41LB", 0xC8, 0x11, 2048, 128, 64, 1024,
320 1, 7, 0, 4, 52, READ_FROM_CACHE_X4,
321 &ecc_layout_64, generic_spi_nand_ecc_status),
322
b.liub17525e2025-05-14 17:22:29 +0800[diff] [blame]323 /* ESMT 4Gb : Add by mbtk */
324 SPI_NAND_INFO("F50D4G41XB", 0x2C, 0x35, 4096, 256, 64, 2048,
325 1, 8, 0, 4, 52, READ_FROM_CACHE_X4,
326 &esmt_ecc_layout_256, micron_spi_nand_ecc_status),
327
b.liue9582032025-04-17 19:18:16 +0800[diff] [blame]328 /* Fudan Microelectronics */
329 SPI_NAND_INFO("FM25LS01", 0xA1, 0xA5, 2048, 128, 64, 1024,
330 1, 4, 0, 4, 0, READ_FROM_CACHE_X4,
331 &ecc_layout_128, generic_spi_nand_ecc_status),
332 SPI_NAND_INFO("FM25LG02B", 0xA1, 0xB2, 2048, 128, 64, 2048,
333 1, 8, 0, 4, 0, READ_FROM_CACHE_X4,
334 &ecc_layout_128, fm_spi_nand_ecc_status),
335 /* Micron */
336 SPI_NAND_INFO("MT29F1G01ABBFD", 0x2C, 0x15, 2048, 64, 64, 2048,
337 1, 8, SPINAND_NEED_PLANE_SELECT, 4, 0,
338 READ_FROM_CACHE_X4,
339 &ecc_layout_128, micron_spi_nand_ecc_status),
340
341 /* SiliconGo 3.3V */
342 SPI_NAND_INFO("SGM7000I-S24W1GH", 0xEA, 0xC1, 2048, 64, 64, 1024,
343 1, 4, 0, 4, 0, READ_FROM_CACHE_QUAD,
344 &ecc_layout_64, generic_spi_nand_ecc_status),
345
346 SPI_NAND_INFO("SGM7000I-S25W2GH", 0xEA, 0xC2, 2048, 64, 64, 2048,
347 1, 4, 0, 4, 0, READ_FROM_CACHE_QUAD,
348 &ecc_layout_64, generic_spi_nand_ecc_status),
349 SPI_NAND_INFO("SGM7000I-S25W4GH", 0xEA, 0xC4, 2048, 64, 64, 4096,
350 1, 4, 0, 4, 0, READ_FROM_CACHE_QUAD,
351 &ecc_layout_64, generic_spi_nand_ecc_status),
352
353 {.name = NULL},
354};
355
356/* Standard SPI-NAND flash commands */
357static struct spi_flash_cmd_cfg cmd_table[] = {
358 /*opcode addr_bytes addr_pins mode_bits mode_pins dummy_cycles
359 dummy_pins data_pins seq_id cmd_type */
360 [GET_FEATURE] = SPI_CMD(0x0f, 1, 1, 0, 0, 0, 0, 1, 2, 1),
361 [SET_FEATURE] = SPI_CMD(0x1f, 1, 1, 0, 0, 0, 0, 1, -1, 2),
362 [PAGE_READ] = SPI_CMD(0x13, 3, 1, 0, 0, 0, 0, 0, 3, 0),
363 [READ_PAGE_CACHE_RDM] = SPI_CMD(0x30, 3, 1, 0, 0, 0, 0, 0, -1, 0),
364 [READ_PAGE_CACHE_LAST] = SPI_CMD(0x3f, 0, 0, 0, 0, 0, 0, 0, -1, 0),
365 [READ_FROM_CACHE] = SPI_CMD(0x03, 2, 1, 0, 0, 8, 1, 1, -1, 1),
366 [READ_FROM_CACHE_FAST] = SPI_CMD(0x0b, 2, 1, 0, 0, 8, 1, 1, -1, 1),
367 [READ_FROM_CACHE_X2] = SPI_CMD(0x3b, 2, 1, 0, 0, 8, 1, 2, -1, 1),
368 [READ_FROM_CACHE_DUAL] = SPI_CMD(0xbb, 2, 2, 0, 0, 4, 2, 2, -1, 1),
369 [READ_FROM_CACHE_X4] = SPI_CMD(0x6b, 2, 1, 0, 0, 8, 1, 4, 4, 1),
370 [READ_FROM_CACHE_QUAD] = SPI_CMD(0xeb, 2, 4, 0, 0, 4, 4, 4, 5, 1),
371 [BLK_ERASE] = SPI_CMD(0xd8, 3, 1, 0, 0, 0, 0, 0, -1, 0),
372 [PROG_EXC] = SPI_CMD(0x10, 3, 1, 0, 0, 0, 0, 0, 6, 0),
373 [PROG_LOAD] = SPI_CMD(0x02, 2, 1, 0, 0, 0, 0, 1, 7, 2),
374 [PROG_LOAD_RDM_DATA] = SPI_CMD(0x84, 2, 1, 0, 0, 0, 0, 1, -1, 2),
375 [PROG_LOAD_X4] = SPI_CMD(0x32, 2, 1, 0, 0, 0, 0, 4, 8, 2),
376 [PROG_LOAD_RDM_DATA_X4] = SPI_CMD(0x34, 2, 1, 0, 0, 0, 0, 4, -1, 2),
377 [WR_ENABLE] = SPI_CMD(0x06, 0, 0, 0, 0, 0, 0, 0, -1, 0),
378 [WR_DISABLE] = SPI_CMD(0x04, 0, 0, 0, 0, 0, 0, 0, -1, 0),
379 [READ_ID] = SPI_CMD(0x9f, 0, 0, 0, 0, 0, 0, 1, -1, 1),
380 [RESET] = SPI_CMD(0xff, 0, 0, 0, 0, 0, 0, 0, -1, 0),
381
382 /* Vendor Specific command */
383 [READ_FROM_CACHE_QUAD_GD] = SPI_CMD(0xeb, 2, 4, 0, 0, 2, 4, 4, 9, 1),
384 [READ_FROM_CACHE_QUAD_GD2] = SPI_CMD(0xeb, 2, 4, 0, 0, 8, 4, 4, 10, 1),
385 [READ_ECCSR_MXIC] = SPI_CMD(0x7c, 0, 0, 0, 0, 8, 1, 1, -1, 1),
386 [READ_FROM_CACHE_DTR] = SPI_CMD_DTR(0xee, 0, 4, 4, 1, 0, 0, 0, 8, 4, 4, 1, 11, 1),
387
388 /* END Mark */
389 [MAX_CMD] = SPI_CMD(0x00, 0, 0, 0, 0, 0, 0, 0, -1, 0),
390};
391
392/**
393 * spi_nand_get_device - [GENERIC] Get chip for selected access
394 * @mtd: MTD device structure
395 * @new_state: the state which is requested
396 *
397 * Get the device and lock it for exclusive access
398 */
399static int spi_nand_get_device(struct mtd_info *mtd, int new_state)
400{
401 struct spi_flash_chip *this = mtd->priv;
402
403 this->state = new_state;
404 return 0;
405}
406
407/**
408 * spi_nand_release_device - [GENERIC] release chip
409 * @mtd: MTD device structure
410 *
411 * Deselect, release chip lock and wake up anyone waiting on the device
412 */
413static void spi_nand_release_device(struct mtd_info *mtd)
414{
415 return;
416}
417
418/**
419 * spi_nand_read_reg - send command 0Fh to read register
420 * @chip: SPI_FLASH device structure
421 * @reg; register to read
422 * @buf: buffer to store value
423 */
424static int spi_nand_read_reg(struct spi_flash_chip *chip,
425 u8 reg, u8 *buf)
426{
427 struct spi_flash_cmd cmd;
428 int ret;
429
430 memset(&cmd, 0, sizeof(struct spi_flash_cmd));
431 cmd.cmd_cfg = chip->table + GET_FEATURE;
432 cmd.n_addr = 1;
433 cmd.addr[0] = reg;
434 cmd.n_rx = 1;
435 cmd.rx_buf = buf;
436
437 ret = chip->issue_cmd(chip, &cmd);
438 if (ret < 0)
439 printf("err: %d read register %d\n", ret, reg);
440
441 return ret;
442}
443
444/**
445 * spi_nand_write_reg - send command 1Fh to write register
446 * @chip: SPI-NAND device structure
447 * @reg; register to write
448 * @buf: buffer stored value
449 */
450static int spi_nand_write_reg(struct spi_flash_chip *chip,
451 u8 reg, u8 *buf)
452{
453 struct spi_flash_cmd cmd;
454 int ret;
455
456 memset(&cmd, 0, sizeof(struct spi_flash_cmd));
457 cmd.cmd_cfg = chip->table + SET_FEATURE;
458 cmd.n_addr = 1;
459 cmd.addr[0] = reg;
460 cmd.n_tx = 1;
461 cmd.tx_buf = buf;
462
463 ret = chip->issue_cmd(chip, &cmd);
464 if (ret < 0)
465 printf("err: %d write register %d\n", ret, reg);
466
467 return ret;
468}
469
470/**
471 * spi_nand_read_status - get status register value
472 * @chip: SPI-NAND device structure
473 * @status: buffer to store value
474 * Description:
475 * After read, write, or erase, the Nand device is expected to set the
476 * busy status.
477 * This function is to allow reading the status of the command: read,
478 * write, and erase.
479 * Once the status turns to be ready, the other status bits also are
480 * valid status bits.
481 */
482static int spi_nand_read_status(struct spi_flash_chip *chip, u8 *status)
483{
484 return spi_nand_read_reg(chip, REG_STATUS, status);
485}
486
487/**
488 * spi_nand_get_cfg - get configuration register value
489 * @chip: SPI-NAND device structure
490 * @cfg: buffer to store value
491 * Description:
492 * Configuration register includes OTP config, Lock Tight enable/disable
493 * and Internal ECC enable/disable.
494 */
495static int spi_nand_get_cfg(struct spi_flash_chip *chip, u8 *cfg)
496{
497 return spi_nand_read_reg(chip, REG_CFG, cfg);
498}
499
500/**
501 * spi_nand_set_cfg - set value to configuration register
502 * @chip: SPI-NAND device structure
503 * @cfg: buffer stored value
504 * Description:
505 * Configuration register includes OTP config, Lock Tight enable/disable
506 * and Internal ECC enable/disable.
507 */
508static int spi_nand_set_cfg(struct spi_flash_chip *chip, u8 *cfg)
509{
510 return spi_nand_write_reg(chip, REG_CFG, cfg);
511}
512
513/**
514 * spi_nand_enable_ecc - enable internal ECC
515 * @chip: SPI-NAND device structure
516 * Description:
517 * There is one bit( bit 0x10 ) to set or to clear the internal ECC.
518 * Enable chip internal ECC, set the bit to 1
519 * Disable chip internal ECC, clear the bit to 0
520 */
521static int spi_nand_enable_ecc(struct spi_flash_chip *chip)
522{
523 u8 cfg = 0;
524
525 /* For XTX spi-nand, ECC_EN locate in 0x90 feature register */
526 if (chip->options & SPINAND_ECC_EN_ADDR_90H)
527 spi_nand_read_reg(chip, 0x90, &cfg);
528 else
529 spi_nand_get_cfg(chip, &cfg);
530
531 if ((cfg & CFG_ECC_MASK) == CFG_ECC_ENABLE)
532 return 0;
533
534 cfg |= CFG_ECC_ENABLE;
535
536 if (chip->options & SPINAND_ECC_EN_ADDR_90H)
537 return spi_nand_write_reg(chip, 0x90, &cfg);
538 else
539 return spi_nand_set_cfg(chip, &cfg);
540}
541
542/**
543 * spi_nand_disable_ecc - disable internal ECC
544 * @chip: SPI-NAND device structure
545 * Description:
546 * There is one bit( bit 0x10 ) to set or to clear the internal ECC.
547 * Enable chip internal ECC, set the bit to 1
548 * Disable chip internal ECC, clear the bit to 0
549 */
550static int spi_nand_disable_ecc(struct spi_flash_chip *chip)
551{
552 u8 cfg = 0;
553
554 /* For XTX spi-nand, ECC_EN locate in 0x90 feature register */
555 if (chip->options & SPINAND_ECC_EN_ADDR_90H)
556 spi_nand_read_reg(chip, 0x90, &cfg);
557 else
558 spi_nand_get_cfg(chip, &cfg);
559
560 if ((cfg & CFG_ECC_MASK) == CFG_ECC_ENABLE) {
561 cfg &= ~CFG_ECC_ENABLE;
562 if (chip->options & SPINAND_ECC_EN_ADDR_90H)
563 return spi_nand_write_reg(chip, 0x90, &cfg);
564 else
565 return spi_nand_set_cfg(chip, &cfg);
566 }
567 return 0;
568}
569
570static int spi_nand_enable_quad(struct spi_flash_chip *chip)
571{
572 u8 cfg = 0;
573
574 spi_nand_get_cfg(chip, &cfg);
575 if ((cfg & CFG_QE_MASK) == CFG_QE_ENABLE)
576 return 0;
577 cfg |= CFG_QE_ENABLE;
578 return spi_nand_set_cfg(chip, &cfg);
579}
580
581/**
582 * generic_spi_nand_ecc_status - decode status regisger to get ecc info
583 * @status: status register value to decode
584 * @corrected: bitflip count that ecc corrected
585 * @ecc_error: uncorrected bitflip happen or not
586 */
587static void generic_spi_nand_ecc_status(struct spi_flash_chip *chip, u8 status,
588 u32 *corrected, u32 *ecc_error)
589{
590 u8 ecc_status = (status & SPI_NAND_ECC_MASK) >> SPI_NAND_ECC_SHIFT;
591
592 *ecc_error = 0;
593 switch (ecc_status) {
594 case 0x0:
595 /* No bit error detected */
596 *corrected = 0;
597 break;
598 case 0x1:
599 /* 1~4 error bits detected and corrected */
600 *corrected = 4;
601 break;
602 case 0x2:
603 /* Error detected and can not corrected */
604 *ecc_error = 1;
605 break;
606 default:
607 printf("%s: unexpected status: %d\n", __func__, ecc_status);
608 *ecc_error = 1;
609 break;
610 }
611}
612
613static int mxic_spi_nand_set_bft(struct spi_flash_chip *chip, u8 threshold)
614{
615 u8 val, bft;
616 int ret;
617
618 ret = spi_nand_read_reg(chip, 0x10, &val);
619 if (ret)
620 return ret;
621
622 bft = (val & 0xf0) >> 4;
623 printf("%s: read BFT=0x%x threshold=%d\r\n", __func__, val, threshold);
624
625 if (bft != threshold) {
626 val = threshold << 4;
627 ret = spi_nand_write_reg(chip, 0x10, &val);
628 if (ret)
629 return ret;
630
631 printf("%s: update BFT=0x%x\r\n", __func__, val);
632 }
633
634 return 0;
635}
636
637static void mxic_spi_nand_ecc_status(struct spi_flash_chip *chip, u8 status,
638 u32 *corrected, u32 *ecc_error)
639{
640 uint8_t ecc_status = (status & SPI_NAND_ECC_MASK) >> SPI_NAND_ECC_SHIFT;
641
642 *ecc_error = 0;
643 switch (ecc_status) {
644 case 0x0:
645 /* No bit error detected */
646 *corrected = 0;
647 break;
648 case 0x1:
649 /* 1~4 error bits detected and corrected */
650 *corrected = 4;
651 break;
652 case 0x2:
653 /* Error detected and can not corrected */
654 *ecc_error = 1;
655 break;
656 default:
657 *corrected = 4;
658 break;
659 }
660}
661
662static int mxic_spi_nand_read_eccsr(struct spi_flash_chip *chip, u8 *eccsr)
663{
664 struct spi_flash_cmd cmd;
665 int ret;
666
667 memset(&cmd, 0, sizeof(struct spi_flash_cmd));
668 cmd.cmd_cfg = chip->table + READ_ECCSR_MXIC;
669 cmd.n_rx = 1;
670 cmd.rx_buf = eccsr;
671
672 ret = chip->issue_cmd(chip, &cmd);
673 if (ret < 0)
674 pr_info("err: %d read eccsr register\r\n", ret);
675
676 return ret;
677}
678
679static void mxic2_spi_nand_ecc_status(struct spi_flash_chip *chip, u8 status,
680 u32 *corrected, u32 *ecc_error)
681{
682 u8 ecc_status = (status & SPI_NAND_ECC_MASK) >> SPI_NAND_ECC_SHIFT;
683 u8 eccsr;
684
685 *ecc_error = 0;
686 switch (ecc_status) {
687 case 0x0:
688 /* No bit error detected */
689 *corrected = 0;
690 break;
691 case 0x2:
692 /* Error detected and can not corrected */
693 *ecc_error = 1;
694 break;
695 case 0x1:
696 /* 1~8 error bits detected and corrected */
697 *corrected = 4;
698 default:
699 mxic_spi_nand_read_eccsr(chip, &eccsr);
700 eccsr &= 0xf;
701 if (eccsr == 0xf)
702 *ecc_error = 1;
703 else
704 *corrected = eccsr;
705 break;
706 }
707}
708
709static void micron_spi_nand_ecc_status(struct spi_flash_chip *chip, u8 status,
710 u32 *corrected, u32 *ecc_error)
711{
712 u8 ecc_status = (status & 0x70) >> SPI_NAND_ECC_SHIFT;
713
714 *ecc_error = 0;
715 switch (ecc_status) {
716 case 0x0:
717 /* No bit error detected */
718 *corrected = 0;
719 break;
720 case 0x1:
721 /* 1~3 error bits detected and corrected */
722 *corrected = 3;
723 break;
724 case 0x2:
725 /* Error detected and can not corrected */
726 *ecc_error = 1;
727 break;
728 case 0x3:
729 /* 4~6 error bits detected and corrected */
730 *corrected = 6;
731 break;
732 case 0x5:
733 /* 7~8 error bits detected and corrected */
734 *corrected = 8;
735 break;
736 default:
737 printf("%s: unexpected status: %d\n", __func__, ecc_status);
738 *ecc_error = 1;
739 break;
740 }
741}
742
743static void fm_spi_nand_ecc_status(struct spi_flash_chip *chip, u8 status,
744 u32 *corrected, u32 *ecc_error)
745{
746 u8 ecc_status = (status & 0x70) >> SPI_NAND_ECC_SHIFT;
747
748 *ecc_error = 0;
749 switch (ecc_status) {
750 case 0x0:
751 /* No bit error detected */
752 *corrected = 0;
753 break;
754 case 0x1:
755 *corrected = 3;
756 break;
757 case 0x2:
758 *corrected = 4;
759 break;
760 case 0x3:
761 *corrected = 5;
762 break;
763 case 0x4:
764 *corrected = 6;
765 break;
766 case 0x5:
767 *corrected = 7;
768 break;
769 case 0x6:
770 *corrected = 8;
771 break;
772 case 0x7:
773 /* Error detected and can not corrected */
774 *ecc_error = 1;
775 break;
776 default:
777 obm_printf("%s: unexpected status: %d\r\n",
778 __func__, ecc_status);
779 *ecc_error = 1;
780 break;
781 }
782}
783
784static void xtx_spi_nand_ecc_status(struct spi_flash_chip *chip, u8 status,
785 u32 *corrected, u32 *ecc_error)
786{
787 u8 ecc_status = (status & SPI_NAND_ECC_MASK) >> SPI_NAND_ECC_SHIFT;
788
789 *ecc_error = 0;
790 switch (ecc_status) {
791 case 0x0:
792 /* No bit error detected */
793 *corrected = 0;
794 break;
795 case 0x1:
796 /* 1~7 error bits detected and corrected */
797 *corrected = 7;
798 break;
799 case 0x2:
800 /* Error detected and can not corrected */
801 *ecc_error = 1;
802 break;
803 case 0x3:
804 /* 8 error bits detected and corrected */
805 *corrected = 8;
806 break;
807 }
808}
809
810static void xtx2_spi_nand_ecc_status(struct spi_flash_chip *chip, u8 status,
811 u32 *corrected, u32 *ecc_error)
812{
813 u8 ecc_status = (status & SPI_NAND_ECC_MASK) >> SPI_NAND_ECC_SHIFT;
814 u8 ecc_status2 = (status & 0xf0) >> SPI_NAND_ECC_SHIFT;
815
816 *ecc_error = 0;
817 switch (ecc_status) {
818 case 0x0:
819 /* No bit error detected */
820 *corrected = 0;
821 break;
822 case 0x1:
823 switch (ecc_status2) {
824 case 1:
825 *corrected = 4;
826 break;
827 case 5:
828 *corrected = 5;
829 break;
830 case 9:
831 *corrected = 6;
832 break;
833 case 0xd:
834 *corrected = 7;
835 break;
836 }
837 break;
838 case 0x2:
839 /* Error detected and can not corrected */
840 *ecc_error = 1;
841 break;
842 case 0x3:
843 /* 8 error bits detected and corrected */
844 *corrected = 8;
845 break;
846 }
847}
848
849static void yxsc_spi_nand_ecc_status(struct spi_flash_chip *chip, u8 status,
850 u32 *corrected, u32 *ecc_error)
851{
852 u8 ecc_status = (status & 0x70) >> SPI_NAND_ECC_SHIFT;
853
854 *ecc_error = 0;
855 switch (ecc_status) {
856 case 0x0:
857 /* No bit error detected */
858 *corrected = 0;
859 break;
860 case 0x1:
861 /* 1~7 error bits detected and corrected */
862 *corrected = 1;
863 break;
864 case 0x2:
865 /* 2 error bits detected and corrected */
866 *ecc_error = 2;
867 break;
868 case 0x3:
869 /* 3 error bits detected and corrected */
870 *corrected = 3;
871 break;
872 case 0x4:
873 /* 4 error bits detected and corrected */
874 *corrected = 4;
875 break;
876 case 0x7:
877 /* Error detected and can not corrected */
878 *ecc_error = 1;
879 break;
880 default:
881 printf("%s: unexpected status: %d\r\n",
882 __func__, ecc_status);
883 *ecc_error = 1;
884 break;
885 }
886}
887
888static void gd_spi_nand_ecc_status(struct spi_flash_chip *chip, u8 status,
889 u32 *corrected, u32 *ecc_error)
890{
891 u8 ecc_status = (status & SPI_NAND_ECC_MASK) >> SPI_NAND_ECC_SHIFT;
892 u8 ext_status;
893 int ret;
894
895 *ecc_error = 0;
896 *corrected = 0;
897 if (ecc_status == 0x1) {
898 ret = spi_nand_read_reg(chip, 0xf0, &ext_status);
899 if (ret) {
900 printf("gd_spi_nand_ecc_status failed\n");
901 return;
902 }
903
904 ext_status = (ext_status & SPI_NAND_ECC_MASK) >>
905 SPI_NAND_ECC_SHIFT;
906 switch (ext_status) {
907 case 0x0:
908 /* 1~4 error bits detected and corrected */
909 *corrected = 4;
910 break;
911 case 0x1:
912 /* 5 error bits detected and corrected */
913 *corrected = 5;
914 break;
915 case 0x2:
916 /* 6 error bits detected and corrected */
917 *corrected = 6;
918 break;
919 case 0x3:
920 /* 7 error bits detected and corrected */
921 *corrected = 7;
922 break;
923 }
924 } else if (ecc_status == 0x2) {
925 /* Error detected and can not corrected */
926 *ecc_error = 1;
927 } else if (ecc_status == 0x3) {
928 /* 8 error bits detected and corrected */
929 *corrected = 8;
930 } else if (ecc_status == 0x0) {
931 /* No bit error detected */
932 *corrected = 0;
933 }
934}
935
936static void gd_spi_nand_ecc_status2(struct spi_flash_chip *chip, u8 status,
937 u32 *corrected, u32 *ecc_error)
938{
939 u8 ecc_status = (status & SPI_NAND_ECC_MASK) >> SPI_NAND_ECC_SHIFT;
940 u8 ext_status;
941 int ret;
942
943 *ecc_error = 0;
944 *corrected = 0;
945 if (ecc_status == 0x0) {
946 /* No bit error detected */
947 *corrected = 0;
948 } else if (ecc_status == 0x1) {
949 ret = spi_nand_read_reg(chip, 0xf0, &ext_status);
950 if (ret) {
951 printf("gd_spi_nand_ecc_status failed\n");
952 return;
953 }
954
955 ext_status = (ext_status & SPI_NAND_ECC_MASK) >>
956 SPI_NAND_ECC_SHIFT;
957
958 switch (ext_status) {
959 case 0x0:
960 *corrected = 1;
961 break;
962 case 0x1:
963 *corrected = 2;
964 break;
965 case 0x2:
966 *corrected = 3;
967 break;
968 case 0x3:
969 *corrected = 4;
970 break;
971 }
972 } else if (ecc_status == 0x2) {
973 /* Error bit > 4 detected and can not corrected */
974 *ecc_error = 1;
975 } else {
976 printf("%s: unexpected status: %d\r\n",
977 __func__, ecc_status);
978 *ecc_error = 1;
979 }
980}
981
982static void wb_spi_nand_ecc_status(struct spi_flash_chip *chip, u8 status,
983 u32 *corrected, u32 *ecc_error)
984{
985 u8 ecc_status = (status & SPI_NAND_ECC_MASK) >> SPI_NAND_ECC_SHIFT;
986 u8 ext_status;
987 int ret;
988
989 *ecc_error = 0;
990 *corrected = 0;
991 if (ecc_status == 0x1) {
992 ret = spi_nand_read_reg(chip, 0x30, &ext_status);
993 if (ret) {
994 printf("wb_spi_nand_ecc_status failed\n");
995 return;
996 }
997
998 ext_status = (ext_status & 0x70) >> 4;
999 if (ext_status == 7)
1000 *ecc_error = 1;
1001 else
1002 *corrected = ext_status;
1003 } else if (ecc_status == 0x2) {
1004 /* Error detected and can not corrected */
1005 *ecc_error = 1;
1006 } else if (ecc_status == 0x3) {
1007 /* 4 error bits detected and corrected */
1008 *corrected = 4;
1009 } else if (ecc_status == 0x0) {
1010 /* No bit error detected */
1011 *corrected = 0;
1012 }
1013}
1014
1015static void wb_spi_nand_ecc_status2(struct spi_flash_chip *chip, u8 status,
1016 u32 *corrected, u32 *ecc_error)
1017{
1018 u8 ecc_status = (status & SPI_NAND_ECC_MASK) >> SPI_NAND_ECC_SHIFT;
1019 u8 ext_status;
1020 int ret;
1021
1022 *ecc_error = 0;
1023 *corrected = 0;
1024 if (ecc_status == 0x1) {
1025 ret = spi_nand_read_reg(chip, 0x30, &ext_status);
1026 if (ret) {
1027 printf("wb_spi_nand_ecc_status2 failed\n");
1028 return;
1029 }
1030
1031 ext_status = (ext_status & 0xf0) >> 4;
1032 if (ext_status == 0xf)
1033 *ecc_error = 1;
1034 else
1035 *corrected = ext_status;
1036 } else if (ecc_status == 0x2) {
1037 /* Error detected and can not corrected */
1038 *ecc_error = 1;
1039 } else if (ecc_status == 0x3) {
1040 /* 4 error bits detected and corrected */
1041 *corrected = 4;
1042 } else if (ecc_status == 0x0) {
1043 /* No bit error detected */
1044 *corrected = 0;
1045 }
1046}
1047
1048/**
1049 * spi_nand_write_enable - send command 06h to enable write or erase the
1050 * Nand cells
1051 * @chip: SPI-NAND device structure
1052 * Description:
1053 * Before write and erase the Nand cells, the write enable has to be set.
1054 * After the write or erase, the write enable bit is automatically
1055 * cleared (status register bit 2)
1056 * Set the bit 2 of the status register has the same effect
1057 */
1058static int spi_nand_write_enable(struct spi_flash_chip *chip)
1059{
1060 struct spi_flash_cmd cmd;
1061
1062 memset(&cmd, 0, sizeof(struct spi_flash_cmd));
1063 cmd.cmd_cfg = chip->table + WR_ENABLE;
1064
1065 return chip->issue_cmd(chip, &cmd);
1066}
1067
1068/**
1069 * spi_nand_set_ds - set value to die select register
1070 * @chip: SPI-NAND device structure
1071 * @cfg: buffer stored value
1072 * Description:
1073 * Configuration register includes OTP config, Lock Tight enable/disable
1074 * and Internal ECC enable/disable.
1075 */
1076static int spi_nand_set_ds(struct spi_flash_chip *chip, u8 *ds)
1077{
1078 return spi_nand_write_reg(chip, REG_DIE_SELECT, ds);
1079}
1080
1081/**
1082 * spi_nand_lun_select - send die select command if needed
1083 * @chip: SPI-NAND device structure
1084 * @lun: lun need to access
1085 */
1086static int spi_nand_lun_select(struct spi_flash_chip *chip, u8 lun)
1087{
1088 u8 ds = 0;
1089 int ret = 0;
1090
1091 if (chip->lun != lun) {
1092 ds = (lun == 1) ? DIE_SELECT_DS1 : DIE_SELECT_DS0;
1093 ret = spi_nand_set_ds(chip, &ds);
1094 chip->lun = lun;
1095 }
1096
1097 return ret;
1098}
1099
1100/**
1101 * spi_nand_read_page_to_cache - send command 13h to read data from Nand to cache
1102 * @chip: SPI-NAND device structure
1103 * @page_addr: page to read
1104 */
1105static int spi_nand_read_page_to_cache(struct spi_flash_chip *chip,
1106 u32 page_addr)
1107{
1108 struct spi_flash_cmd cmd;
1109
1110 memset(&cmd, 0, sizeof(struct spi_flash_cmd));
1111 cmd.cmd_cfg = chip->table + PAGE_READ;
1112 cmd.n_addr = 3;
1113 cmd.addr[0] = (u8)(page_addr >> 16);
1114 cmd.addr[1] = (u8)(page_addr >> 8);
1115 cmd.addr[2] = (u8)page_addr;
1116 cmd.flag = RST_AHB_DOMAIN | AHB_MAP_SIZE_PAGE;
1117
1118 return chip->issue_cmd(chip, &cmd);
1119}
1120
1121/**
1122 * spi_nand_read_from_cache - read data out from cache register
1123 * @chip: SPI-NAND device structure
1124 * @page_addr: page to read
1125 * @column: the location to read from the cache
1126 * @len: number of bytes to read
1127 * @rbuf: buffer held @len bytes
1128 * Description:
1129 * Command can be 03h, 0Bh, 3Bh, 6Bh, BBh, EBh
1130 * The read can specify 1 to (page size + spare size) bytes of data read at
1131 * the corresponding locations.
1132 * No tRd delay.
1133 */
1134static int spi_nand_read_from_cache(struct spi_flash_chip *chip,
1135 u32 page_addr, u32 column,
1136 u32 len, u8 *rbuf)
1137{
1138 struct spi_flash_cmd cmd;
1139
1140 if (chip->options & SPINAND_NEED_PLANE_SELECT) {
1141 column |= (((page_addr >>
1142 (chip->block_shift - chip->page_shift)) & 0x1) << 12);
1143 }
1144
1145 if (chip->xip_read && chip->memmap_read) {
1146 chip->memmap_read(chip, rbuf, column, len);
1147 return 0;
1148 }
1149
1150 memset(&cmd, 0, sizeof(struct spi_flash_cmd));
1151 cmd.cmd_cfg = chip->table + chip->read_cache_op;
1152 cmd.n_addr = 2;
1153 cmd.addr[0] = (u8)(column >> 8);
1154 cmd.addr[1] = (u8)column;
1155 cmd.n_rx = len;
1156 cmd.rx_buf = rbuf;
1157
1158 return chip->issue_cmd(chip, &cmd);
1159}
1160
1161/**
1162 * spi_nand_program_data_to_cache - write data to cache register
1163 * @chip: SPI-NAND device structure
1164 * @page_addr: page to write
1165 * @column: the location to write to the cache
1166 * @len: number of bytes to write
1167 * @wrbuf: buffer held @len bytes
1168 * @clr_cache: clear cache register or not
1169 * Description:
1170 * Command can be 02h, 32h, 84h, 34h
1171 * 02h and 32h will clear the cache with 0xff value first
1172 * Since it is writing the data to cache, there is no tPROG time.
1173 */
1174static int spi_nand_program_data_to_cache(struct spi_flash_chip *chip,
1175 u32 page_addr, u32 column, u32 len,
1176 const u8 *wbuf, u8 clr_cache)
1177{
1178 struct spi_flash_cmd cmd;
1179
1180 if (chip->options & SPINAND_NEED_PLANE_SELECT) {
1181 column |= (((page_addr >>
1182 (chip->block_shift - chip->page_shift)) & 0x1) << 12);
1183 }
1184
1185 memset(&cmd, 0, sizeof(struct spi_flash_cmd));
1186 if (clr_cache)
1187 cmd.cmd_cfg = chip->table + chip->write_cache_op;
1188 else
1189 cmd.cmd_cfg = chip->table + chip->write_cache_rdm_op;
1190 cmd.n_addr = 2;
1191 cmd.addr[0] = (u8)(column >> 8);
1192 cmd.addr[1] = (u8)column;
1193 cmd.n_tx = len;
1194 cmd.tx_buf = wbuf;
1195 cmd.flag = RST_AHB_DOMAIN;
1196
1197 return chip->issue_cmd(chip, &cmd);
1198}
1199
1200/**
1201 * spi_nand_program_execute - send command 10h to write a page from
1202 * cache to the Nand array
1203 * @chip: SPI-NAND device structure
1204 * @page_addr: the physical page location to write the page.
1205 * Description:
1206 * Need to wait for tPROG time to finish the transaction.
1207 */
1208static int spi_nand_program_execute(struct spi_flash_chip *chip, u32 page_addr)
1209{
1210 struct spi_flash_cmd cmd;
1211
1212 memset(&cmd, 0, sizeof(struct spi_flash_cmd));
1213 cmd.cmd_cfg = chip->table + PROG_EXC;
1214 cmd.n_addr = 3;
1215 cmd.addr[0] = (u8)(page_addr >> 16);
1216 cmd.addr[1] = (u8)(page_addr >> 8);
1217 cmd.addr[2] = (u8)page_addr;
1218
1219 return chip->issue_cmd(chip, &cmd);
1220}
1221
1222/**
1223 * spi_nand_erase_block_erase - send command D8h to erase a block
1224 * @chip: SPI-NAND device structure
1225 * @page_addr: the page to erase.
1226 * Description:
1227 * Need to wait for tERS.
1228 */
1229static int spi_nand_erase_block(struct spi_flash_chip *chip,
1230 u32 page_addr)
1231{
1232 struct spi_flash_cmd cmd;
1233
1234 memset(&cmd, 0, sizeof(struct spi_flash_cmd));
1235 cmd.cmd_cfg = chip->table + BLK_ERASE;
1236 cmd.n_addr = 3;
1237 cmd.addr[0] = (u8)(page_addr >> 16);
1238 cmd.addr[1] = (u8)(page_addr >> 8);
1239 cmd.addr[2] = (u8)page_addr;
1240 cmd.flag = RST_AHB_DOMAIN | AHB_MAP_SIZE_PAGE;
1241
1242 return chip->issue_cmd(chip, &cmd);
1243}
1244
1245/**
1246 * spi_nand_wait - wait until the command is done
1247 * @chip: SPI-NAND device structure
1248 * @s: buffer to store status register(can be NULL)
1249 */
1250static int spi_nand_wait(struct spi_flash_chip *chip, u8 *s)
1251{
1252 u8 status;
1253 unsigned long ret = -ETIMEDOUT;
1254
1255 while (1) {
1256 spi_nand_read_status(chip, &status);
1257 if ((status & STATUS_OIP_MASK) == STATUS_READY) {
1258 ret = 0;
1259 goto out;
1260 }
1261 }
1262out:
1263 if (s)
1264 *s = status;
1265
1266 return ret;
1267}
1268
1269/**
1270 * spi_nand_read_id - send 9Fh command to get ID
1271 * @chip: SPI_FLASH device structure
1272 * @buf: buffer to store id
1273 */
1274static int spi_nand_read_id(struct spi_flash_chip *chip, u8 *buf)
1275{
1276 struct spi_flash_cmd cmd;
1277
1278 memset(&cmd, 0, sizeof(struct spi_flash_cmd));
1279 cmd.cmd_cfg = chip->table + READ_ID;
1280 cmd.n_rx = 4;
1281 cmd.rx_buf = buf;
1282
1283 return chip->issue_cmd(chip, &cmd);
1284}
1285
1286/**
1287 * spi_nand_reset - send command FFh to reset chip.
1288 * @chip: SPI_FLASH device structure
1289 */
1290static int spi_nand_reset(struct spi_flash_chip *chip)
1291{
1292 struct spi_flash_cmd cmd;
1293
1294 memset(&cmd, 0, sizeof(struct spi_flash_cmd));
1295 cmd.cmd_cfg = chip->table + RESET;
1296
1297 if (chip->issue_cmd(chip, &cmd))
1298 printf("spi_nand reset failed!\n");
1299
1300 /* elapse 2ms before issuing any other command */
1301 udelay(2000);
1302 return 0;
1303}
1304
1305/**
1306 * spi_nand_lock_block - [Interface] write block lock register to
1307 * lock/unlock device
1308 * @spi: spi device structure
1309 * @lock: value to set to block lock register
1310 * Description:
1311 * After power up, all the Nand blocks are locked. This function allows
1312 * one to unlock the blocks, and so it can be written or erased.
1313 *
1314 * Register Bit Address
1315 * | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1316 * |---------------------------------------------------------|
1317 * | BRWD2 | BP3 | BP2 | BP1 | BP0 | TB | WP | Reversed |
1318 *
1319 * Block Lock Register Block Protection Bits
1320 *
1321 * TB BP3 BP2 BP1 BP0 Protected Portion
1322 * 0 0 0 0 0 All unlocked
1323 * 0 0 0 0 1 Upper 1/1024 locked
1324 * 0 0 0 1 0 Upper 1/512 locked
1325 * 0 0 0 1 1 Upper 1/256 locked
1326 * 0 0 1 0 0 Upper 1/128 locked
1327 * 0 0 1 0 1 Upper 1/64 locked
1328 * 0 0 1 1 0 Upper 1/32 locked
1329 * 0 0 1 1 1 Upper 1/16 locked
1330 * 0 1 0 0 0 Upper 1/8 locked
1331 * 0 1 0 0 1 Upper 1/4 locked
1332 * 0 1 0 1 0 Upper 1/2 locked
1333 * 0 1 0 1 1 All Locked
1334 * 0 1 1 0 0 All Locked
1335 * 0 1 1 0 1 All Locked
1336 * 0 1 1 1 0 All Locked
1337 * 0 1 1 1 1 All Locked
1338 * 1 0 0 0 0 All unlocked
1339 * 1 0 0 0 1 Lower 1/1024 locked
1340 * 1 0 0 1 0 Lower 1/512 locked
1341 * 1 0 0 1 1 Lower 1/256 locked
1342 * 1 0 1 0 0 Lower 1/128 locked
1343 * 1 0 1 0 1 Lower 1/64 locked
1344 * 1 0 1 1 0 Lower 1/32 locked
1345 * 1 0 1 1 1 Lower 1/16 locked
1346 * 1 1 0 0 0 Lower 1/8 locked
1347 * 1 1 0 0 1 Lower 1/4 locked
1348 * 1 1 0 1 0 Lower 1/2 locked
1349 * 1 1 0 1 1 All Locked
1350 * 1 1 1 0 0 All Locked
1351 * 1 1 1 0 1 All Locked
1352 * 1 1 1 1 0 All Locked
1353 * 1 1 1 1 1 All Locked
1354
1355 */
1356int spi_nand_lock_block(struct spi_flash_chip *chip, u8 lock)
1357{
1358 return spi_nand_write_reg(chip, REG_BLOCK_LOCK, &lock);
1359}
1360
1361/**
1362 * spi_nand_change_mode - switch chip to OTP/OTP protect/Normal mode
1363 * @chip: SPI-NAND device structure
1364 * @mode: mode to enter
1365 */
1366static int spi_nand_change_mode(struct spi_flash_chip *chip, u8 mode)
1367{
1368 u8 cfg;
1369
1370 spi_nand_get_cfg(chip, &cfg);
1371 switch (mode) {
1372 case OTP_MODE:
1373 cfg = (cfg & ~CFG_OTP_MASK) | CFG_OTP_ENTER;
1374 break;
1375 case OTP_PROTECT_MODE:
1376 cfg = (cfg & ~CFG_OTP_MASK) | CFG_OTP_PROTECT;
1377 break;
1378 case SNOR_READ_ENABLE_MODE:
1379 cfg = (cfg & ~CFG_OTP_MASK) | CFG_SNOR_ENABLE;
1380 break;
1381 case NORMAL_MODE:
1382 cfg = (cfg & ~CFG_OTP_MASK) | CFG_OTP_EXIT;
1383 break;
1384 }
1385 spi_nand_set_cfg(chip, &cfg);
1386
1387 return 0;
1388}
1389
1390/**
1391 * spi_nand_scan_id_table - scan chip info in id table
1392 * @chip: SPI-NAND device structure
1393 * @id: point to manufacture id and device id
1394 * Description:
1395 * If found in id table, config chip with table information.
1396 */
1397static bool spi_nand_scan_id_table(struct spi_flash_chip *chip)
1398{
1399 struct spi_nand_info *type = spi_nand_table;
1400 int id;
1401
1402 for (; type->name; type++) {
1403 /* ignore high byte if not used */
1404 if (!(type->dev_id >> 8))
1405 id = (chip->dev_id & 0xff);
1406 else
1407 id = chip->dev_id;
1408 if (chip->mfr_id == type->mfr_id && id == type->dev_id) {
1409 //chip->name = type->name;
1410 chip->size = type->page_size * type->pages_per_blk
1411 * type->blks_per_lun * type->luns_per_chip;
1412 chip->block_size = type->page_size
1413 * type->pages_per_blk;
1414 chip->page_size = type->page_size;
1415 chip->oob_size = type->oob_size;
1416 chip->lun_shift =
1417 ilog2(chip->block_size * type->blks_per_lun);
1418 chip->ecc_strength = type->ecc_strength;
1419 chip->options |= type->options;
1420 chip->refresh_threshold = type->bitflip_threshold;
1421 chip->ecclayout = type->ecclayout;
1422 chip->get_ecc_status = type->get_ecc_status;
1423 chip->max_mhz = type->max_mhz;
1424 chip->tclqv = type->tclqv;
1425 chip->tset = type->tset;
1426 chip->thold = type->thold;
1427 chip->flash_info = type;
1428
1429 printf("SPI-NAND: %s is found.\n", type->name);
1430 return true;
1431 }
1432 }
1433
1434 chip->refresh_threshold = 1;
1435 return false;
1436}
1437
1438static u16 onfi_crc16(u16 crc, u8 const *p, u32 len)
1439{
1440 int i;
1441
1442 while (len--) {
1443 crc ^= *p++ << 8;
1444 for (i = 0; i < 8; i++)
1445 crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
1446 }
1447
1448 return crc;
1449}
1450
1451/* Sanitize ONFI strings so we can safely print them */
1452static void sanitize_string(char *s, u32 len)
1453{
1454 int i = len - 1;
1455 int j = 0;
1456
1457 /* Null terminate */
1458 s[i--] = 0;
1459
1460 /* Remove unnecessary space */
1461 while (i >= 0 && (s[i] <= ' ' || s[i] > 127)) {
1462 s[i--] = 0;
1463 }
1464 /* Remove non printable chars */
1465 for (j = 0; j <= i; j++) {
1466 if (s[j] < ' ' || s[j] > 127)
1467 s[j] = '?';
1468 }
1469}
1470
1471/**
1472 * spi_nand_detect_onfi - config chip with parameter page
1473 * @chip: SPI-NAND device structure
1474 * Description:
1475 * This function is called when we can not get info from id table.
1476 */
1477static int spi_nand_detect_onfi(struct spi_flash_chip *chip)
1478{
1479 struct spi_nand_onfi_params *p;
1480 u8 *buffer;
1481 int read_cache_op;
1482 int ret = true;
1483 int i;
1484
1485 buffer = malloc(256 * 3);
1486 printf("spi_nand_detect_onfi: buffer=0x%x\n", (unsigned int)buffer);
1487 memset(buffer, 0x0, 256*3);
1488
1489 spi_nand_change_mode(chip, OTP_MODE);
1490 spi_nand_read_page_to_cache(chip, 0x01);
1491 spi_nand_wait(chip, NULL);
1492 /*
1493 * read parameter page can only ues 1-1-1 mode
1494 */
1495 read_cache_op = chip->read_cache_op;
1496 chip->read_cache_op = READ_FROM_CACHE;
1497 spi_nand_read_from_cache(chip, 0x01, 0, 256 * 4, buffer);
1498 chip->read_cache_op = read_cache_op;
1499 spi_nand_change_mode(chip, NORMAL_MODE);
1500
1501 p = (struct spi_nand_onfi_params *)buffer;
1502 for (i = 0; i < 3; i++, p++) {
1503 if (p->sig[0] != 'O' || p->sig[1] != 'N' ||
1504 p->sig[2] != 'F' || p->sig[3] != 'I')
1505 continue;
1506 //if (onfi_crc16(ONFI_CRC_BASE, (u8 *)p, 254) ==
1507 // (p->crc))
1508 break;
1509 }
1510
1511 if (i == 3) {
1512 printf("Could not find valid ONFI, use default settings\n");
1513 ret = false;
1514 goto out;
1515 }
1516
1517 memcpy(&chip->onfi_params, p, sizeof(*p));
1518 p = &chip->onfi_params;
1519 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
1520 sanitize_string(p->model, sizeof(p->model));
1521
1522 //chip->name = p->model;
1523 chip->size = (p->byte_per_page) *
1524 (p->pages_per_block) *
1525 (p->blocks_per_lun) * p->lun_count;
1526 chip->block_size = (p->byte_per_page) *
1527 (p->pages_per_block);
1528 chip->page_size = (p->byte_per_page);
1529 chip->oob_size = (p->spare_bytes_per_page);
1530 chip->lun_shift = ilog2(chip->block_size * (p->blocks_per_lun));
1531
1532// if (chip->mfr_id == SPIFLASH_MFR_MICRON) {
1533// if (p->vendor.micron_sepcific.two_plane_page_read)
1534// chip->options |= SPINAND_NEED_PLANE_SELECT;
1535// if (p->vendor.micron_sepcific.die_selection)
1536// chip->options |= SPINAND_NEED_DIE_SELECT;
1537// }
1538 chip->ecc_strength = p->vendor.micron_sepcific.ecc_ability;
1539out:
1540 free(buffer);
1541 return ret;
1542}
1543
1544#define SPI_NAND_MAX_RETRY 3
1545/**
1546 * spi_nand_do_read_page - read page from flash to buffer
1547 * @chip: spi nand chip structure
1548 * @page_addr: page address/raw address
1549 * @column: column address
1550 * @ecc_off: without ecc or not
1551 * @corrected: how many bit error corrected
1552 * @buf: data buffer
1553 * @len: data length to read
1554 * Description:
1555 * Return -EBADMSG when internal ecc can not correct bitflips.
1556 * The command sequence to transfer data from NAND array to output is
1557 * follows:
1558 * 13h (PAGE READ to cache register)
1559 * 0Fh (GET FEATURES command to read the status)
1560 * 0Bh/03h/3Bh/6Bh (Read from Cache Xn); or BBh/EBh (Read From
1561 * Cache Dual/Quad IO)
1562 */
1563static int spi_nand_do_read_page(struct mtd_info *mtd, u32 page_addr,
1564 u32 column, bool ecc_off, u32 *corrected,
1565 u8 *buf, int size, bool oob_only)
1566{
1567 struct spi_flash_chip *chip = mtd->priv;
1568 u32 ecc_error;
1569 u8 status;
1570 int ret;
1571 int len = size;
1572 int rx_len, i;
1573
1574 if (!buf) {
1575 if (!oob_only) {
1576 len = chip->page_size + chip->oob_size;
1577 buf = chip->buf;
1578 column = 0;
1579 } else {
1580 len = chip->oob_size;
1581 buf = chip->oobbuf;
1582 column = chip->page_size;
1583 }
1584 }
1585
1586 spi_nand_read_page_to_cache(chip, page_addr);
1587 ret = spi_nand_wait(chip, &status);
1588 if (ret < 0) {
1589 printf("error %d waiting page 0x%x to cache\n",
1590 ret, page_addr);
1591 return ret;
1592 }
1593
1594 if (!ecc_off && chip->get_ecc_status) {
1595 chip->get_ecc_status(chip, status, corrected, &ecc_error);
1596 if (ecc_error) {
1597 printf("internal ECC error reading page 0x%x\n",
1598 page_addr);
1599 mtd->ecc_stats.failed++;
1600 } else if (*corrected) {
1601 if (*corrected < chip->refresh_threshold)
1602 /*
1603 * Do not report bit-flip to upper layer if
1604 * less than refresh_threshold, which may
1605 * make mtd->_read failure
1606 */
1607 *corrected = 0;
1608 else
1609 mtd->ecc_stats.corrected += *corrected;
1610 }
1611 }
1612
1613 rx_len = chip->rx_max_len ? chip->rx_max_len : len;
1614 do {
1615 int real_len;
1616
1617 i = 0;
1618retry:
1619 real_len = min(len, rx_len);
1620 ret = spi_nand_read_from_cache(chip, page_addr, column,
1621 real_len, buf);
1622 if (ret == -EAGAIN && ++i <= SPI_NAND_MAX_RETRY) {
1623 rx_len = rx_len / 2;
1624 goto retry;
1625 } else if (ret) {
1626 return -EIO;
1627 } else if (i) {
1628 printf("Pass after the %dth retry\n", i);
1629 }
1630
1631 column += real_len;
1632 buf += real_len;
1633 len -= real_len;
1634 } while (len);
1635
1636 return ret;
1637}
1638
1639/**
1640 * spi_nand_transfer_oob - transfer oob to client buffer
1641 * @chip: SPI-NAND device structure
1642 * @oob: oob destination address
1643 * @ops: oob ops structure
1644 * @len: size of oob to transfer
1645 */
1646static void spi_nand_transfer_oob(struct spi_flash_chip *chip, u8 *oob,
1647 struct mtd_oob_ops *ops, size_t len)
1648{
1649 switch (ops->mode) {
1650
1651 case MTD_OPS_PLACE_OOB:
1652 case MTD_OPS_RAW:
1653 memcpy(oob, chip->oobbuf + ops->ooboffs, len);
1654 return;
1655
1656 case MTD_OPS_AUTO_OOB: {
1657 struct nand_oobfree *free = chip->ecclayout->oobfree;
1658 u32 boffs = 0, roffs = ops->ooboffs;
1659 size_t bytes = 0;
1660
1661 for (; free->length && len; free++, len -= bytes) {
1662 /* Read request not from offset 0? */
1663 if (unlikely(roffs)) {
1664 if (roffs >= free->length) {
1665 roffs -= free->length;
1666 continue;
1667 }
1668 boffs = free->offset + roffs;
1669 bytes = min_t(size_t, len,
1670 (free->length - roffs));
1671 roffs = 0;
1672 } else {
1673 bytes = min_t(size_t, len, free->length);
1674 boffs = free->offset;
1675 }
1676 memcpy(oob, chip->oobbuf + boffs, bytes);
1677 oob += bytes;
1678 }
1679 return;
1680 }
1681 default:
1682 BUG();
1683 }
1684}
1685
1686/**
1687 * spi_nand_fill_oob - transfer client buffer to oob
1688 * @chip: SPI-NAND device structure
1689 * @oob: oob data buffer
1690 * @len: oob data write length
1691 * @ops: oob ops structure
1692 */
1693static void spi_nand_fill_oob(struct spi_flash_chip *chip, u8 *oob,
1694 size_t len, struct mtd_oob_ops *ops)
1695{
1696 memset(chip->oobbuf, 0xff, chip->oob_size);
1697 switch (ops->mode) {
1698
1699 case MTD_OPS_PLACE_OOB:
1700 case MTD_OPS_RAW:
1701 memcpy(chip->oobbuf + ops->ooboffs, oob, len);
1702 return;
1703
1704 case MTD_OPS_AUTO_OOB: {
1705 struct nand_oobfree *free = chip->ecclayout->oobfree;
1706 u32 boffs = 0, woffs = ops->ooboffs;
1707 size_t bytes = 0;
1708
1709 for (; free->length && len; free++, len -= bytes) {
1710 /* Write request not from offset 0? */
1711 if (unlikely(woffs)) {
1712 if (woffs >= free->length) {
1713 woffs -= free->length;
1714 continue;
1715 }
1716 boffs = free->offset + woffs;
1717 bytes = min_t(size_t, len,
1718 (free->length - woffs));
1719 woffs = 0;
1720 } else {
1721 bytes = min_t(size_t, len, free->length);
1722 boffs = free->offset;
1723 }
1724 memcpy(chip->oobbuf + boffs, oob, bytes);
1725 oob += bytes;
1726 }
1727 return;
1728 }
1729 default:
1730 BUG();
1731 }
1732}
1733
1734/**
1735 * spi_nand_read_pages - read data from flash to buffer
1736 * @mtd: MTD device structure
1737 * @from: offset to read from
1738 * @ops: oob operations description structure
1739 * @max_bitflips: maximum bitflip count
1740 * Description:
1741 * Normal read function, read one page to buffer before issue
1742 * another.
1743 */
1744static int spi_nand_read_pages(struct mtd_info *mtd, loff_t from,
1745 struct mtd_oob_ops *ops, unsigned int *max_bitflips)
1746{
1747 struct spi_flash_chip *chip = mtd->priv;
1748 struct mtd_ecc_stats stats;
1749 int page_addr, page_offset, page_blk_shift, size, ret;
1750 u32 corrected = 0;
1751 int readlen = ops->len;
1752 int oobreadlen = ops->ooblen;
1753 bool ecc_off = ops->mode == MTD_OPS_RAW;
1754#ifdef OOB_REQ_ALIGN_TO_SPARE_LEN
1755 int ooblen = mtd->oobsize;
1756#else
1757 int ooblen = ops->mode == MTD_OPS_AUTO_OOB ?
1758 mtd->oobavail : mtd->oobsize;
1759#endif
1760 int lun_num;
1761 int real_page;
1762 int blk_addr = -1;
1763 u8 *buf;
1764
1765 page_blk_shift = chip->block_shift - chip->page_shift;
1766 real_page = from >> chip->page_shift;
1767 page_offset = from & chip->page_mask;
1768 lun_num = from >> chip->lun_shift;
1769 ops->retlen = 0;
1770 *max_bitflips = 0;
1771 if (chip->options & SPINAND_NEED_DIE_SELECT)
1772 spi_nand_lun_select(chip, lun_num);
1773
1774 stats = mtd->ecc_stats;
1775 page_addr = real_page;
1776 while (1) {
1777 if (chip->search_bbm_table &&
1778 (blk_addr != real_page >> page_blk_shift)) {
1779 int addr;
1780
1781 blk_addr = real_page >> page_blk_shift;
1782 addr = real_page << chip->page_shift;
1783 addr = chip->search_bbm_table(chip, addr);
1784 page_addr = addr >> chip->page_shift;
1785 lun_num = addr >> chip->lun_shift;
1786 if (chip->options & SPINAND_NEED_DIE_SELECT)
1787 spi_nand_lun_select(chip, lun_num);
1788 }
1789
1790 size = min(readlen, chip->page_size - page_offset);
1791
1792 if (unlikely(ops->oobbuf) || page_offset ||
1793 (size < chip->page_size))
1794 buf = NULL;
1795 else {
1796 chip->cached_page = -1;
1797 buf = ops->datbuf + ops->retlen;
1798 }
1799
1800 if (page_addr != chip->cached_page
1801 || ecc_off != chip->cached_page_ecc_off) {
1802 ret = spi_nand_do_read_page(mtd, page_addr, page_offset,
1803 ecc_off, &corrected, buf,
1804 size, false);
1805 if (ret)
1806 break;
1807
1808 if (chip->low_level_scrub) {
1809 corrected = chip->low_level_scrub(chip,
1810 real_page, corrected);
1811 blk_addr = -1;
1812 }
1813
1814 chip->cached_page_bitflips = corrected;
1815 if (!buf && !(mtd->ecc_stats.failed - stats.failed)) {
1816 chip->cached_page = page_addr;
1817 chip->cached_page_ecc_off = ecc_off;
1818 }
1819 }
1820
1821 if (!buf)
1822 memcpy(ops->datbuf + ops->retlen,
1823 chip->buf + page_offset, size);
1824
1825 *max_bitflips = max(*max_bitflips, chip->cached_page_bitflips);
1826
1827 ops->retlen += size;
1828 readlen -= size;
1829 page_offset = 0;
1830
1831 if (unlikely(ops->oobbuf)) {
1832 size = min(oobreadlen, ooblen);
1833 spi_nand_transfer_oob(chip,
1834 ops->oobbuf + ops->oobretlen, ops, size);
1835 ops->oobretlen += size;
1836 oobreadlen -= size;
1837 }
1838 if (!readlen)
1839 break;
1840
1841 page_addr++;
1842 real_page++;
1843 /* Check, if we cross lun boundary */
1844 if (!(real_page &
1845 ((1 << (chip->lun_shift - chip->page_shift)) - 1))
1846 && (chip->options & SPINAND_NEED_DIE_SELECT)) {
1847 lun_num++;
1848 spi_nand_lun_select(chip, lun_num);
1849 }
1850 }
1851
1852 if (mtd->ecc_stats.failed - stats.failed)
1853 return -EBADMSG;
1854
1855 return ret;
1856}
1857
1858/**
1859 * spi_nand_do_read_ops - read data from flash to buffer
1860 * @mtd: MTD device structure
1861 * @from: offset to read from
1862 * @ops: oob ops structure
1863 * Description:
1864 * Disable internal ECC before reading when MTD_OPS_RAW set.
1865 */
1866static int spi_nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1867 struct mtd_oob_ops *ops)
1868{
1869 struct spi_flash_chip *chip = mtd->priv;
1870 int ret;
1871 unsigned int max_bitflips = 0;
1872 int oobreadlen = ops->ooblen;
1873 bool ecc_off = ops->mode == MTD_OPS_RAW;
1874#ifdef OOB_REQ_ALIGN_TO_SPARE_LEN
1875 int ooblen = mtd->oobsize;
1876#else
1877 int ooblen = ops->mode == MTD_OPS_AUTO_OOB ?
1878 mtd->oobavail : mtd->oobsize;
1879#endif
1880 /* Do not allow reads past end of device */
1881 if (unlikely(from >= mtd->size)) {
1882 pr_err("%s: attempt to read beyond end of device\n",
1883 __func__);
1884 return -EINVAL;
1885 }
1886
1887 /* for oob */
1888 if (oobreadlen > 0) {
1889 if (unlikely(ops->ooboffs >= ooblen)) {
1890 pr_err("%s: attempt to start read outside oob\n",
1891 __func__);
1892 return -EINVAL;
1893 }
1894
1895 if (unlikely(ops->ooboffs + oobreadlen >
1896 ((mtd->size >> chip->page_shift) - (from >> chip->page_shift))
1897 * ooblen)) {
1898 pr_err("%s: attempt to read beyond end of device\n",
1899 __func__);
1900 return -EINVAL;
1901 }
1902 ooblen -= ops->ooboffs;
1903 ops->oobretlen = 0;
1904 }
1905
1906 if (ecc_off)
1907 chip->disable_ecc(chip);
1908
1909 ret = spi_nand_read_pages(mtd, from, ops, &max_bitflips);
1910
1911 if (ecc_off)
1912 chip->enable_ecc(chip);
1913
1914 if (ret < 0)
1915 return ret;
1916
1917 return max_bitflips;
1918}
1919
1920static int spi_nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1921 size_t *retlen, u8 *buf)
1922{
1923 struct mtd_oob_ops ops;
1924 int ret;
1925
1926 spi_nand_get_device(mtd, FL_READING);
1927
1928 memset(&ops, 0, sizeof(ops));
1929 ops.len = len;
1930 ops.datbuf = buf;
1931 ops.mode = MTD_OPS_PLACE_OOB;
1932 ret = spi_nand_do_read_ops(mtd, from, &ops);
1933
1934 *retlen = ops.retlen;
1935
1936 spi_nand_release_device(mtd);
1937
1938 return ret;
1939}
1940
1941/**
1942 * spi_nand_do_read_oob - read out-of-band
1943 * @mtd: MTD device structure
1944 * @from: offset to read from
1945 * @ops: oob operations description structure
1946 * Description:
1947 * Disable internal ECC before reading when MTD_OPS_RAW set.
1948 */
1949static int spi_nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1950 struct mtd_oob_ops *ops)
1951{
1952 struct spi_flash_chip *chip = mtd->priv;
1953 int page_addr, page_blk_shift;
1954 u32 corrected = 0;
1955 struct mtd_ecc_stats stats;
1956 int readlen = ops->ooblen;
1957 int len;
1958 int ret = 0;
1959 bool ecc_off = ops->mode == MTD_OPS_RAW;
1960 int lun_num;
1961 int real_page;
1962 int blk_addr = -1;
1963
1964 pr_debug("%s: from = 0x%08Lx, len = %i\n",
1965 __func__, (unsigned long long)from, readlen);
1966
1967 stats = mtd->ecc_stats;
1968
1969#ifdef OOB_REQ_ALIGN_TO_SPARE_LEN
1970 len = mtd->oobsize;
1971#else
1972 len = ops->mode == MTD_OPS_AUTO_OOB ? mtd->oobavail : mtd->oobsize;
1973#endif
1974 if (unlikely(ops->ooboffs >= len)) {
1975 pr_err("%s: attempt to start read outside oob\n",
1976 __func__);
1977 return -EINVAL;
1978 }
1979
1980 /* Do not allow reads past end of device */
1981 if (unlikely(from >= mtd->size ||
1982 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1983 (from >> chip->page_shift)) * len)) {
1984 pr_err("%s: attempt to read beyond end of device\n",
1985 __func__);
1986 return -EINVAL;
1987 }
1988
1989 page_blk_shift = chip->block_shift - chip->page_shift;
1990 real_page = from >> chip->page_shift;
1991 lun_num = from >> chip->lun_shift;
1992 len -= ops->ooboffs;
1993 ops->oobretlen = 0;
1994 if (chip->options & SPINAND_NEED_DIE_SELECT)
1995 spi_nand_lun_select(chip, lun_num);
1996
1997 if (ecc_off)
1998 chip->disable_ecc(chip);
1999
2000 page_addr = real_page;
2001 while (1) {
2002 if (chip->search_bbm_table &&
2003 (blk_addr != real_page >> page_blk_shift)) {
2004 int addr;
2005
2006 blk_addr = real_page >> page_blk_shift;
2007 addr = real_page << chip->page_shift;
2008 addr = chip->search_bbm_table(chip, addr);
2009 page_addr = addr >> chip->page_shift;
2010 lun_num = addr >> chip->lun_shift;
2011 if (chip->options & SPINAND_NEED_DIE_SELECT)
2012 spi_nand_lun_select(chip, lun_num);
2013 }
2014
2015 /*read data from chip*/
2016 ret = spi_nand_do_read_page(mtd, page_addr, 0,
2017 ecc_off, &corrected, NULL,
2018 0, true);
2019 if (ret)
2020 goto out;
2021
2022 if (chip->low_level_scrub) {
2023 corrected = chip->low_level_scrub(chip,
2024 real_page, corrected);
2025 blk_addr = -1;
2026 }
2027
2028 len = min(len, readlen);
2029 spi_nand_transfer_oob(chip, ops->oobbuf + ops->oobretlen,
2030 ops, len);
2031 readlen -= len;
2032 ops->oobretlen += len;
2033 if (!readlen)
2034 break;
2035 page_addr++;
2036 real_page++;
2037 /* Check, if we cross lun boundary */
2038 if (!(real_page &
2039 ((1 << (chip->lun_shift - chip->page_shift)) - 1))
2040 && (chip->options & SPINAND_NEED_DIE_SELECT)) {
2041 lun_num++;
2042 spi_nand_lun_select(chip, lun_num);
2043 }
2044 }
2045out:
2046 if (ecc_off)
2047 chip->enable_ecc(chip);
2048
2049 if (ret < 0)
2050 return ret;
2051
2052 if (mtd->ecc_stats.failed - stats.failed)
2053 return -EBADMSG;
2054
2055 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
2056}
2057
2058/**
2059 * spi_nand_read_oob - [MTD Interface] read data and/or out-of-band
2060 * @mtd: MTD device structure
2061 * @from: offset to read from
2062 * @ops: oob operation description structure
2063 */
2064static int spi_nand_read_oob(struct mtd_info *mtd, loff_t from,
2065 struct mtd_oob_ops *ops)
2066{
2067 int ret = -ENOTSUPP;
2068
2069 ops->retlen = 0;
2070
2071 /* Do not allow reads past end of device */
2072 if (ops->datbuf && (from + ops->len) > mtd->size) {
2073 printf("%s: attempt to read beyond end of device\n",
2074 __func__);
2075 return -EINVAL;
2076 }
2077
2078 spi_nand_get_device(mtd, FL_READING);
2079
2080 switch (ops->mode) {
2081 case MTD_OPS_PLACE_OOB:
2082 case MTD_OPS_AUTO_OOB:
2083 case MTD_OPS_RAW:
2084 break;
2085
2086 default:
2087 goto out;
2088 }
2089
2090 if (!ops->datbuf)
2091 ret = spi_nand_do_read_oob(mtd, from, ops);
2092 else
2093 ret = spi_nand_do_read_ops(mtd, from, ops);
2094
2095out:
2096 spi_nand_release_device(mtd);
2097
2098 return ret;
2099}
2100
2101/**
2102 * spi_nand_do_write_page - write data from buffer to flash
2103 * @mtd: MTD device structure
2104 * @page_addr: page address/raw address
2105 * @column: column address
2106 * @buf: data buffer
2107 * @len: data length to write
2108 * @clr_cache: clear cache register with 0xFF or not
2109 */
2110static int spi_nand_do_write_page(struct mtd_info *mtd, u32 page_addr,
2111 u32 column, const u8 *buf,
2112 u32 size, u8 clr_cache, bool oob_only)
2113{
2114 struct spi_flash_chip *chip = mtd->priv;
2115 u32 column_save, len_save;
2116 u8 *buf_save;
2117 u8 status;
2118 int len = size, tx_len, i;
2119 int ret = 0;
2120 int cache_done = 0;
2121
2122 if (!buf) {
2123 if (!oob_only) {
2124 len = chip->page_size + chip->oob_size;
2125 buf = chip->buf;
2126 column = 0;
2127 } else {
2128 len = chip->oob_size;
2129 buf = chip->oobbuf;
2130 column = chip->page_size;
2131 }
2132 }
2133
2134 buf_save = buf;
2135 column_save = column;
2136 len_save = len;
2137
2138 tx_len = chip->tx_max_len;
2139load_cache:
2140 if (tx_len < len && (chip->options & SPINAND_RDM_CMD_NEED_PAGE_READ)) {
2141 /*
2142 * XTX spi-nand PROGRAM LOAD RANDOM DATA cmd only used for
2143 * Internal Data Move, need to send 13H (PAGE READ TO CACHE)
2144 * before use this command.
2145 *
2146 * If spi-nand from new vendor have same limitation as XTX, must
2147 * set SPINAND_RDM_CMD_NEED_PAGE_READ in options of spi_nand_table.
2148 */
2149 spi_nand_read_page_to_cache(chip, page_addr);
2150 ret = spi_nand_wait(chip, &status);
2151 if (ret < 0) {
2152 printf("error %d waiting page 0x%x to cache\n",
2153 ret, page_addr);
2154 return ret;
2155 }
2156
2157 cache_done = 1;
2158 clr_cache = 0;
2159 }
2160
2161 spi_nand_write_enable(chip);
2162 do {
2163 int real_len;
2164
2165 i = 0;
2166retry:
2167 real_len = min(len, tx_len);
2168 ret = spi_nand_program_data_to_cache(chip, page_addr, column,
2169 real_len, buf, clr_cache);
2170 if (ret == -EAGAIN && ++i <= SPI_NAND_MAX_RETRY) {
2171 tx_len = tx_len / 2;
2172 if (!cache_done &&
2173 (chip->options & SPINAND_RDM_CMD_NEED_PAGE_READ)) {
2174 buf = buf_save;
2175 column = column_save;
2176 len = len_save;
2177 goto load_cache;
2178 }
2179 goto retry;
2180 } else if (ret) {
2181 return -EIO;
2182 } else if (i) {
2183 printf("Write pass after the %dth retry\n", i);
2184 }
2185
2186 clr_cache = 0;
2187 column += real_len;
2188 buf += real_len;
2189 len -= real_len;
2190 } while (len);
2191
2192 spi_nand_program_execute(chip, page_addr);
2193 ret = spi_nand_wait(chip, &status);
2194 if (ret < 0) {
2195 pr_err("error %d reading page 0x%x from cache\n",
2196 ret, page_addr);
2197 return ret;
2198 }
2199 if ((status & STATUS_P_FAIL_MASK) == STATUS_P_FAIL) {
2200 pr_err("program page 0x%x failed\n", page_addr);
2201 ret = -EIO;
2202 }
2203 return ret;
2204}
2205
2206/**
2207 * spi_nand_do_write_ops - write data from buffer to flash
2208 * @mtd: MTD device structure
2209 * @to: offset to write to
2210 * @ops: oob operations description structure
2211 * Description:
2212 * Disable internal ECC before writing when MTD_OPS_RAW set.
2213 */
2214static int spi_nand_do_write_ops(struct mtd_info *mtd, loff_t to,
2215 struct mtd_oob_ops *ops)
2216{
2217 struct spi_flash_chip *chip = mtd->priv;
2218 int page_addr, page_offset, page_blk_shift, size;
2219 int writelen = ops->len;
2220 int oobwritelen = ops->ooblen;
2221 int ret = 0;
2222#ifdef OOB_REQ_ALIGN_TO_SPARE_LEN
2223 int ooblen = mtd->oobsize;
2224#else
2225 int ooblen = ops->mode == MTD_OPS_AUTO_OOB ?
2226 mtd->oobavail : mtd->oobsize;
2227#endif
2228 bool ecc_off = ops->mode == MTD_OPS_RAW;
2229 int lun_num;
2230 int real_page;
2231 int blk_addr = -1;
2232 u8 *buf;
2233
2234 /* Do not allow reads past end of device */
2235 if (unlikely(to >= mtd->size)) {
2236 pr_err("%s: attempt to write beyond end of device\n",
2237 __func__);
2238 return -EINVAL;
2239 }
2240
2241 page_blk_shift = chip->block_shift - chip->page_shift;
2242 real_page = to >> chip->page_shift;
2243 page_offset = to & chip->page_mask;
2244 lun_num = to >> chip->lun_shift;
2245 ops->retlen = 0;
2246
2247 /* for oob */
2248 if (oobwritelen > 0) {
2249 /* Do not allow write past end of page */
2250 if ((ops->ooboffs + oobwritelen) > ooblen) {
2251 pr_err("%s: attempt to write past end of page\n",
2252 __func__);
2253 return -EINVAL;
2254 }
2255
2256 if (unlikely(ops->ooboffs >= ooblen)) {
2257 pr_err("%s: attempt to start write outside oob\n",
2258 __func__);
2259 return -EINVAL;
2260 }
2261 if (unlikely(ops->ooboffs + oobwritelen >
2262 ((mtd->size >> chip->page_shift) - (to >> chip->page_shift))
2263 * ooblen)) {
2264 pr_err("%s: attempt to write beyond end of device\n",
2265 __func__);
2266 return -EINVAL;
2267 }
2268 ooblen -= ops->ooboffs;
2269 ops->oobretlen = 0;
2270 }
2271
2272 chip->cached_page = -1;
2273 if (chip->options & SPINAND_NEED_DIE_SELECT)
2274 spi_nand_lun_select(chip, lun_num);
2275
2276 if (ecc_off)
2277 chip->disable_ecc(chip);
2278
2279 page_addr = real_page;
2280 while (1) {
2281 if (chip->search_bbm_table &&
2282 (blk_addr != real_page >> page_blk_shift)) {
2283 int addr;
2284
2285 blk_addr = real_page >> page_blk_shift;
2286 addr = real_page << chip->page_shift;
2287 addr = chip->search_bbm_table(chip, addr);
2288 page_addr = addr >> chip->page_shift;
2289 lun_num = addr >> chip->lun_shift;
2290 if (chip->options & SPINAND_NEED_DIE_SELECT)
2291 spi_nand_lun_select(chip, lun_num);
2292 }
2293
2294 if (unlikely(ops->oobbuf)) {
2295 size = min(oobwritelen, ooblen);
2296 spi_nand_fill_oob(chip, ops->oobbuf + ops->oobretlen,
2297 size, ops);
2298 ops->oobretlen += size;
2299 oobwritelen -= size;
2300 buf = NULL;
2301 } else {
2302 buf = ops->datbuf + ops->retlen;
2303 memset(chip->oobbuf, 0xff, chip->oob_size);
2304 }
2305 size = min(writelen, chip->page_size - page_offset);
2306
2307 if (!buf) {
2308 memcpy(chip->buf + page_offset,
2309 ops->datbuf + ops->retlen, size);
2310 if (page_offset)
2311 memset(chip->buf, 0xff, page_offset);
2312 if (size < chip->page_size - page_offset)
2313 memset(chip->buf + page_offset + size, 0xff,
2314 chip->page_size - page_offset - size);
2315 }
2316
2317 ret = spi_nand_do_write_page(mtd, page_addr, page_offset,
2318 buf, size, 1, false);
2319 if (ret) {
2320 pr_err("error %d writing page 0x%x\n",
2321 ret, page_addr);
2322 goto out;
2323 }
2324
2325 ops->retlen += size;
2326 writelen -= size;
2327 page_offset = 0;
2328 if (!writelen)
2329 break;
2330
2331 page_addr++;
2332 real_page++;
2333 /* Check, if we cross lun boundary */
2334 if (!(real_page &
2335 ((1 << (chip->lun_shift - chip->page_shift)) - 1))
2336 && (chip->options & SPINAND_NEED_DIE_SELECT)) {
2337 lun_num++;
2338 spi_nand_lun_select(chip, lun_num);
2339 }
2340 }
2341out:
2342 if (ecc_off)
2343 chip->enable_ecc(chip);
2344
2345 return ret;
2346}
2347
2348static int spi_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2349 size_t *retlen, const u8 *buf)
2350{
2351 struct mtd_oob_ops ops;
2352 int ret;
2353
2354 spi_nand_get_device(mtd, FL_WRITING);
2355
2356 memset(&ops, 0, sizeof(ops));
2357 ops.len = len;
2358 ops.datbuf = (u8 *)buf;
2359 ops.mode = MTD_OPS_PLACE_OOB;
2360 ret = spi_nand_do_write_ops(mtd, to, &ops);
2361
2362 *retlen = ops.retlen;
2363
2364 spi_nand_release_device(mtd);
2365
2366 return ret;
2367}
2368
2369/**
2370 * spi_nand_do_write_oob - write out-of-band
2371 * @mtd: MTD device structure
2372 * @to: offset to write to
2373 * @ops: oob operation description structure
2374 * Description:
2375 * Disable internal ECC before writing when MTD_OPS_RAW set.
2376 */
2377static int spi_nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2378 struct mtd_oob_ops *ops)
2379{
2380 int page_addr, len, ret;
2381 struct spi_flash_chip *chip = mtd->priv;
2382 int writelen = ops->ooblen;
2383 bool ecc_off = ops->mode == MTD_OPS_RAW;
2384 int lun_num;
2385
2386 pr_debug("%s: to = 0x%08x, len = %i\n",
2387 __func__, (unsigned int)to, (int)writelen);
2388
2389#ifdef OOB_REQ_ALIGN_TO_SPARE_LEN
2390 len = mtd->oobsize;
2391#else
2392 len = ops->mode == MTD_OPS_AUTO_OOB ? mtd->oobavail : mtd->oobsize;
2393#endif
2394 /* Do not allow write past end of page */
2395 if ((ops->ooboffs + writelen) > len) {
2396 pr_err("%s: attempt to write past end of page\n",
2397 __func__);
2398 return -EINVAL;
2399 }
2400
2401 if (unlikely(ops->ooboffs >= len)) {
2402 pr_err("%s: attempt to start write outside oob\n",
2403 __func__);
2404 return -EINVAL;
2405 }
2406
2407 /* Do not allow write past end of device */
2408 if (unlikely(to >= mtd->size ||
2409 ops->ooboffs + writelen >
2410 ((mtd->size >> chip->page_shift) -
2411 (to >> chip->page_shift)) * len)) {
2412 pr_err("%s: attempt to write beyond end of device\n",
2413 __func__);
2414 return -EINVAL;
2415 }
2416
2417 if (chip->search_bbm_table)
2418 to = chip->search_bbm_table(chip, to);
2419
2420 /* Shift to get page */
2421 page_addr = to >> chip->page_shift;
2422 lun_num = to >> chip->lun_shift;
2423
2424 spi_nand_fill_oob(chip, ops->oobbuf, writelen, ops);
2425 if (chip->options & SPINAND_NEED_DIE_SELECT)
2426 spi_nand_lun_select(chip, lun_num);
2427
2428 if (ecc_off)
2429 chip->disable_ecc(chip);
2430
2431 //ret = spi_nand_do_write_page(mtd, page_addr, true);
2432 ret = spi_nand_do_write_page(mtd, page_addr, 0,
2433 NULL, 0, 1, true);
2434 if (ret) {
2435 pr_err("error %d writing page 0x%x\n",
2436 ret, page_addr);
2437 goto out;
2438 }
2439 ops->oobretlen = writelen;
2440
2441out:
2442 if (ecc_off)
2443 chip->enable_ecc(chip);
2444
2445 return ret;
2446}
2447
2448/**
2449 * spi_nand_write_oob - [MTD Interface] write data and/or out-of-band
2450 * @mtd: MTD device structure
2451 * @to: offset to write to
2452 * @ops: oob operation description structure
2453 */
2454static int spi_nand_write_oob(struct mtd_info *mtd, loff_t to,
2455 struct mtd_oob_ops *ops)
2456{
2457 int ret = -ENOTSUPP;
2458
2459 ops->retlen = 0;
2460
2461 /* Do not allow writes past end of device */
2462 if (ops->datbuf && (to + ops->len) > mtd->size) {
2463 pr_err("%s: attempt to write beyond end of device\n",
2464 __func__);
2465 return -EINVAL;
2466 }
2467
2468 spi_nand_get_device(mtd, FL_WRITING);
2469
2470 switch (ops->mode) {
2471 case MTD_OPS_PLACE_OOB:
2472 case MTD_OPS_AUTO_OOB:
2473 case MTD_OPS_RAW:
2474 break;
2475
2476 default:
2477 goto out;
2478 }
2479
2480 if (!ops->datbuf)
2481 ret = spi_nand_do_write_oob(mtd, to, ops);
2482 else
2483 ret = spi_nand_do_write_ops(mtd, to, ops);
2484
2485out:
2486 spi_nand_release_device(mtd);
2487
2488 return ret;
2489}
2490
2491/**
2492 * spi_nand_block_bad - Check if block at offset is bad
2493 * @mtd: MTD device structure
2494 * @offs: offset relative to mtd start
2495 * @getchip: 0, if the chip is already selected
2496 */
2497static int spi_nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
2498{
2499 struct spi_flash_chip *chip = mtd->priv;
2500 struct mtd_oob_ops ops = {0};
2501 u32 block_addr;
2502 u8 bad[2] = {0, 0};
2503 u8 ret = 0;
2504
2505 block_addr = ofs >> chip->block_shift;
2506 ops.mode = MTD_OPS_PLACE_OOB;
2507 ops.ooblen = 2;
2508 ops.oobbuf = bad;
2509
2510 if (getchip)
2511 spi_nand_get_device(mtd, FL_READING);
2512 spi_nand_do_read_oob(mtd, block_addr << chip->block_shift, &ops);
2513 if (getchip)
2514 spi_nand_release_device(mtd);
2515 if (bad[0] != 0xFF || bad[1] != 0xFF)
2516 ret = 1;
2517
2518 return ret;
2519}
2520
2521/**
2522 * spi_nand_block_checkbad - Check if a block is marked bad
2523 * @mtd: MTD device structure
2524 * @ofs: offset from device start
2525 * @getchip: 0, if the chip is already selected
2526 * @allowbbt: 1, if its allowed to access the bbt area
2527 *
2528 * Check, if the block is bad. Either by reading the bad block table or
2529 * calling of the scan function.
2530 */
2531static int spi_nand_block_checkbad(struct mtd_info *mtd, loff_t ofs,
2532 int getchip, int allowbbt)
2533{
2534 struct spi_flash_chip *chip = mtd->priv;
2535
2536 if (!chip->bbt)
2537 return chip->block_bad(mtd, ofs, getchip);
2538
2539 return 0;
2540}
2541
2542/**
2543 * spi_nand_block_isbad - [MTD Interface] Check if block at offset is bad
2544 * @mtd: MTD device structure
2545 * @offs: offset relative to mtd start
2546 */
2547static int spi_nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2548{
2549 return spi_nand_block_checkbad(mtd, offs, 1, 0);
2550}
2551
2552/**
2553 * spi_nand_is_bad_bbm - [BBT Interface] Check if block at offset is factory bad
2554 * @mtd: MTD device structure
2555 * @offs: offset relative to mtd start
2556 */
2557static int spi_nand_is_bad_bbm(struct mtd_info *mtd, loff_t ofs)
2558{
2559 return spi_nand_block_bad(mtd, ofs, 1);
2560}
2561
2562/**
2563 * spi_nand_block_markbad_lowlevel - mark a block bad
2564 * @mtd: MTD device structure
2565 * @ofs: offset from device start
2566 *
2567 * This function performs the generic bad block marking steps (i.e., bad
2568 * block table(s) and/or marker(s)). We only allow the hardware driver to
2569 * specify how to write bad block markers to OOB (chip->block_markbad).
2570 *
2571 * We try operations in the following order:
2572 * (1) erase the affected block, to allow OOB marker to be written cleanly
2573 * (2) write bad block marker to OOB area of affected block (unless flag
2574 * NAND_BBT_NO_OOB_BBM is present)
2575 * (3) update the BBT
2576 * Note that we retain the first error encountered in (2) or (3), finish the
2577 * procedures, and dump the error in the end.
2578*/
2579//static int spi_nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs)
2580//{
2581// struct spi_flash_chip *chip = mtd->priv;
2582// struct mtd_oob_ops ops = {0};
2583// struct erase_info einfo = {0};
2584// u32 block_addr;
2585// u8 buf[2] = {0, 0};
2586// int res, ret = 0;
2587//
2588// if (!chip->bbt || !(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) {
2589// /*erase bad block before mark bad block*/
2590// einfo.mtd = mtd;
2591// einfo.addr = ofs;
2592// einfo.len = 1UL << chip->block_shift;
2593// spi_nand_erase(mtd, &einfo);
2594//
2595// block_addr = ofs >> chip->block_shift;
2596// ops.mode = MTD_OPS_PLACE_OOB;
2597// ops.ooblen = 2;
2598// ops.oobbuf = buf;
2599// spi_nand_get_device(mtd, FL_WRITING);
2600// ret = spi_nand_do_write_oob(mtd,
2601// block_addr << chip->block_shift, &ops);
2602// spi_nand_release_device(mtd);
2603// }
2604//
2605// /* Mark block bad in BBT */
2606// if (chip->bbt) {
2607// res = nand_bbt_markbad(chip->bbt, ofs);
2608// if (!ret)
2609// ret = res;
2610// }
2611//
2612// if (!ret)
2613// mtd->ecc_stats.badblocks++;
2614//
2615// return ret;
2616//}
2617
2618/**
2619 * spi_nand_block_markbad - [MTD Interface] Mark block at the given offset
2620 * as bad
2621 * @mtd: MTD device structure
2622 * @ofs: offset relative to mtd start
2623 */
2624static int spi_nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
2625{
2626 struct spi_flash_chip *chip = mtd->priv;
2627 int ret;
2628
2629 ret = spi_nand_block_isbad(mtd, ofs);
2630 if (ret) {
2631 /* If it was bad already, return success and do nothing */
2632 if (ret > 0)
2633 return 0;
2634 return ret;
2635 }
2636
2637 return chip->block_markbad(mtd, ofs);
2638}
2639
2640/**
2641 * __spi_nand_erase - erase block(s)
2642 * @mtd: MTD device structure
2643 * @einfo: erase instruction
2644 * @allowbbt: allow to access bbt
2645 *
2646 * Erase one ore more blocks
2647 */
2648static int __spi_nand_erase(struct mtd_info *mtd, struct erase_info *einfo,
2649 int allowbbt)
2650{
2651 struct spi_flash_chip *chip = mtd->priv;
2652 int page_addr, pages_per_block;
2653 loff_t len;
2654 u8 status;
2655 int ret = 0;
2656 int lun_num;
2657 int real_page;
2658
2659
2660 /* check address align on block boundary */
2661 if (einfo->addr & (chip->block_size - 1)) {
2662 pr_err("%s: Unaligned address\n", __func__);
2663 return -EINVAL;
2664 }
2665
2666 if (einfo->len & (chip->block_size - 1)) {
2667 pr_err("%s: Length not block aligned\n", __func__);
2668 return -EINVAL;
2669 }
2670
2671 /* Do not allow erase past end of device */
2672 if ((einfo->len + einfo->addr) > chip->size) {
2673 pr_err("%s: Erase past end of device\n", __func__);
2674 return -EINVAL;
2675 }
2676
2677 einfo->fail_addr = MTD_FAIL_ADDR_UNKNOWN;
2678
2679 /* Grab the lock and see if the device is available */
2680 spi_nand_get_device(mtd, FL_ERASING);
2681
2682 pages_per_block = 1 << (chip->block_shift - chip->page_shift);
2683 real_page = einfo->addr >> chip->page_shift;
2684 len = einfo->len;
2685 lun_num = einfo->addr >> chip->lun_shift;
2686 chip->cached_page = -1;
2687
2688 einfo->state = MTD_ERASING;
2689 if (chip->options & SPINAND_NEED_DIE_SELECT)
2690 spi_nand_lun_select(chip, lun_num);
2691
2692 while (len) {
2693 if (chip->search_bbm_table) {
2694 int addr;
2695
2696 addr = real_page << chip->page_shift;
2697 addr = chip->search_bbm_table(chip, addr);
2698 page_addr = addr >> chip->page_shift;
2699 lun_num = addr >> chip->lun_shift;
2700 if (chip->options & SPINAND_NEED_DIE_SELECT)
2701 spi_nand_lun_select(chip, lun_num);
2702 } else {
2703 page_addr = real_page;
2704 }
2705
2706 /* Check if we have a bad block, we do not erase bad blocks! */
2707 if (spi_nand_block_checkbad(mtd, ((loff_t) page_addr) <<
2708 chip->page_shift, 0, allowbbt)) {
2709 pr_warn("%s: attempt to erase a bad block at 0x%012llx\n",
2710 __func__, ((loff_t) page_addr) << chip->page_shift);
2711 einfo->state = MTD_ERASE_FAILED;
2712 goto erase_exit;
2713 }
2714 spi_nand_write_enable(chip);
2715 spi_nand_erase_block(chip, page_addr);
2716 ret = spi_nand_wait(chip, &status);
2717 if (ret < 0) {
2718 pr_err("block erase command wait failed\n");
2719 einfo->state = MTD_ERASE_FAILED;
2720 goto erase_exit;
2721 }
2722 if ((status & STATUS_E_FAIL_MASK) == STATUS_E_FAIL) {
2723 pr_err("erase block 0x%012llx failed\n",
2724 ((loff_t) page_addr) << chip->page_shift);
2725 einfo->state = MTD_ERASE_FAILED;
2726 einfo->fail_addr = (loff_t)page_addr
2727 << chip->page_shift;
2728 goto erase_exit;
2729 }
2730
2731 /* Increment page address and decrement length */
2732 len -= (1ULL << chip->block_shift);
2733 real_page += pages_per_block;
2734 /* Check, if we cross lun boundary */
2735 if (len && !(real_page &
2736 ((1 << (chip->lun_shift - chip->page_shift)) - 1))
2737 && (chip->options & SPINAND_NEED_DIE_SELECT)) {
2738 lun_num++;
2739 spi_nand_lun_select(chip, lun_num);
2740 }
2741 }
2742
2743 einfo->state = MTD_ERASE_DONE;
2744
2745erase_exit:
2746
2747 ret = einfo->state == MTD_ERASE_DONE ? 0 : -EIO;
2748
2749 spi_nand_release_device(mtd);
2750
2751 /* Do call back function */
2752 if (!ret)
2753 mtd_erase_callback(einfo);
2754
2755 /* Return more or less happy */
2756 return ret;
2757}
2758
2759/**
2760 * spi_nand_erase - [MTD Interface] erase block(s)
2761 * @mtd: MTD device structure
2762 * @einfo: erase instruction
2763 *
2764 * Erase one ore more blocks
2765 */
2766static int spi_nand_erase(struct mtd_info *mtd, struct erase_info *einfo)
2767{
2768 struct spi_flash_chip *chip = mtd->priv;
2769 int ret, page, retries = 0;
2770 page = (int)(einfo->addr >> chip->page_shift);
2771
2772retry:
2773 ret = __spi_nand_erase(mtd, einfo, 0);
2774 if (ret) {
2775 if (chip->options & BBT_RELOCATION_IFBAD) {
2776 if (retries++ < 3)
2777 goto retry;
2778
2779 ret = chip->block_markbad(mtd,
2780 (loff_t)(page << chip->page_shift));
2781 }
2782 }
2783
2784 return ret;
2785}
2786
2787/**
2788 * spi_nand_set_rd_wr_op - Chose the best read write command
2789 * @chip: SPI-NAND device structure
2790 * Description:
2791 * Chose the fastest r/w command according to spi controller's ability.
2792 * Note:
2793 * If 03h/0Bh follows SPI NAND protocol, there is no difference,
2794 * while if follows SPI NOR protocol, 03h command is working under
2795 * <=20Mhz@3.3V,<=5MHz@1.8V; 0Bh command is working under
2796 * 133Mhz@3.3v, 83Mhz@1.8V.
2797 */
2798static void spi_nand_set_rd_wr_op(struct spi_flash_chip *chip)
2799{
2800 struct spi_nand_info *type = (struct spi_nand_info *)chip->flash_info;
2801 struct spi_flash_cmd_cfg *read_cmd;
2802
2803 if (chip->rx_mode & SPI_OPM_RX_QUAD) {
2804 if (type) {
2805 if (chip->options & SPINAND_SUPPORT_DTR)
2806 chip->read_cache_op = type->quad_cmd_dtr_index;
2807 else
2808 chip->read_cache_op = type->quad_cmd_index;
2809 } else {
2810 chip->read_cache_op = READ_FROM_CACHE_X4;
2811 }
2812 } else if (chip->rx_mode & SPI_OPM_RX_DUAL) {
2813 chip->read_cache_op = READ_FROM_CACHE_DUAL;
2814 } else {
2815 chip->read_cache_op = READ_FROM_CACHE_FAST;
2816 }
2817
2818 if (chip->tx_mode & SPI_OPM_TX_QUAD) {
2819 chip->write_cache_op = PROG_LOAD_X4;
2820 chip->write_cache_rdm_op = PROG_LOAD_RDM_DATA_X4;
2821 } else {
2822 chip->write_cache_op = PROG_LOAD;
2823 chip->write_cache_rdm_op = PROG_LOAD_RDM_DATA;
2824 }
2825
2826 read_cmd = chip->table + chip->read_cache_op;
2827 printf("Set rx_pins: %d, tx_pins: %d, Read_CMD:0x%x\r\n",
2828 chip->rx_mode, chip->tx_mode, read_cmd->opcode);
2829}
2830
2831/**
2832 * spi_nand_init - [Interface] Init SPI-NAND device driver
2833 * @spi: spi device structure
2834 * @chip_ptr: pointer point to spi nand device structure pointer
2835 */
2836struct spi_flash_chip *spi_nand_scan_ident(struct mtd_info *mtd)
2837{
2838 struct spi_flash_chip *chip = mtd->priv;
2839 u8 id[SPINAND_MAX_ID_LEN] = {0};
2840 int dev_in_tbl = 0;
2841
2842 chip->table = cmd_table;
2843 chip->page_size = 2048;
2844 chip->block_size = 64*2048;
2845 chip->size = 1024*64*2048;
2846
2847 spi_nand_reset(chip);
2848 spi_nand_read_id(chip, id);
2849
2850 chip->mfr_id = id[1];
2851 chip->dev_id = id[2] | id[3] << 8;
2852 if (spi_nand_scan_id_table(chip))
2853 dev_in_tbl = 1;
2854
2855 printf("SPI-NAND type mfr_id: %x, dev_id: %x\n",
2856 chip->mfr_id, chip->dev_id);
2857
2858 if (!chip->check_dtr || !chip->check_dtr(chip))
2859 chip->options &= ~SPINAND_SUPPORT_DTR;
2860
2861 spi_nand_set_rd_wr_op(chip);
2862
2863 /* Not every vendor show QE bit in CFG register */
2864 if (chip->mfr_id != SPIFLASH_MFR_MICRON &&
2865 chip->mfr_id != SPIFLASH_MFR_WINBOND)
2866 spi_nand_enable_quad(chip);
2867
2868 if (chip->setup_memmap_read) {
2869 if (chip->setup_memmap_read(chip,
2870 chip->table + chip->read_cache_op) < 0) {
2871 pr_info("preinit_lookup_tbl failed, check cmd table\n");
2872 return NULL;
2873 }
2874 }
2875
2876 if (chip->options & SPINAND_NEED_SET_BFT)
2877 mxic_spi_nand_set_bft(chip, chip->refresh_threshold);
2878
2879 spi_nand_disable_ecc(chip);
2880 if(!dev_in_tbl) {
2881 /*
2882 * Since Program Load Random Data cmd only valid for some vendor's
2883 * device, set below flag for new device unknown in table for safe.
2884 */
2885 chip->options |= SPINAND_RDM_CMD_NEED_PAGE_READ;
2886 printf("unknown device, set SPINAND_RDM_CMD_NEED_PAGE_READ\r\n");
2887 if (spi_nand_detect_onfi(chip))
2888 printf("nand support onfi\r\n");
2889
2890 if (chip->oob_size == 128)
2891 chip->ecclayout = &ecc_layout_128;
2892 else
2893 chip->ecclayout = &ecc_layout_64;
2894 chip->get_ecc_status = generic_spi_nand_ecc_status;
2895 }
2896
2897 spi_nand_lock_block(chip, BL_ALL_UNLOCKED);
2898 spi_nand_enable_ecc(chip);
2899
2900 chip->block_shift = ilog2(chip->block_size);
2901 chip->page_shift = ilog2(chip->page_size);
2902 chip->page_mask = chip->page_size - 1;
2903 chip->lun = 0;
2904 chip->page_mask = chip->page_size - 1;
2905 if (!chip->enable_ecc)
2906 chip->enable_ecc = spi_nand_enable_ecc;
2907 if (!chip->disable_ecc)
2908 chip->disable_ecc = spi_nand_disable_ecc;
2909
2910 chip->buf = kzalloc(chip->page_size + chip->oob_size, GFP_KERNEL);
2911 if (!chip->buf)
2912 return NULL;
2913
2914 chip->oobbuf = chip->buf + chip->page_size;
2915 printf("block_size=0x%x page_size=0x%x bitflip_threshold=%d\n",
2916 chip->block_size, chip->page_size,
2917 chip->refresh_threshold);
2918
2919 return chip;
2920}
2921
2922/**
2923 * spi_nand_scan_tail - [SPI-NAND Interface] Scan for the SPI-NAND device
2924 * @mtd: MTD device structure
2925 * Description:
2926 * This is the second phase of the initiazation. It fills out all the
2927 * uninitialized fields of spi_flash_chip and mtd fields.
2928 */
2929int spi_nand_scan_tail(struct mtd_info *mtd)
2930{
2931 struct spi_flash_chip *chip = mtd->priv;
2932 int ret;
2933
2934 if (chip->options & SPINAND_ECC_TYPE_HRADWARE)
2935 spi_nand_disable_ecc(chip);
2936
2937 mtd->name = chip->name;
2938 mtd->size = chip->size;
2939 mtd->erasesize = chip->block_size;
2940 mtd->writesize = chip->page_size;
2941 mtd->owner = THIS_MODULE;
2942 mtd->type = MTD_NANDFLASH;
2943 mtd->flags = MTD_CAP_NANDFLASH;
2944 if (!mtd->ecc_strength)
2945 mtd->ecc_strength = chip->ecc_strength ?
2946 chip->ecc_strength : 1;
2947
2948 mtd->ecclayout = chip->ecclayout;
2949 mtd->oobsize = chip->oob_size;
2950 mtd->oobavail = chip->ecclayout->oobavail;
2951 mtd->_erase = spi_nand_erase;
2952 mtd->_point = NULL;
2953 mtd->_unpoint = NULL;
2954 mtd->_read = spi_nand_read;
2955 mtd->_write = spi_nand_write;
2956 mtd->_read_oob = spi_nand_read_oob;
2957 mtd->_write_oob = spi_nand_write_oob;
2958 mtd->_lock = NULL;
2959 mtd->_unlock = NULL;
2960 mtd->_block_isbad = spi_nand_block_isbad;
2961 mtd->_block_markbad = spi_nand_block_markbad;
2962
2963 if (!mtd->bitflip_threshold)
2964 mtd->bitflip_threshold = DIV_ROUND_UP(mtd->ecc_strength * 3, 4);
2965
2966 ret = spi_flash_register(chip);
2967 if (ret)
2968 return ret;
2969
2970 /* Check, if we should skip the bad block table scan */
2971 if (chip->options & NAND_SKIP_BBTSCAN)
2972 return 0;
2973
2974 /* Build bad block table */
2975 return chip->scan_bbt(mtd);
2976}