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192.168.1.100 / T108 / c2023d5d03be91dbb983606f0ec5e9e4ea36c8c2 / . / marvell / uboot / drivers / power / pxa988_freq.c
blob: 4490c53f3fd982735ef7d8fa618360a52d661d57 [file] [log] [blame]
b.liue9582032025-04-17 19:18:16 +0800[diff] [blame]1/*
2 * (C) Copyright 2012
3 * Marvell Semiconductor <www.marvell.com>
4 * Written-by: Jane Li <jiel@marvell.com>
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9#include <errno.h>
10#include <common.h>
11#include <power/pxa_ddr.h>
12#include <asm/gpio.h>
13#include <asm/arch/features.h>
14#include <linux/list.h>
15#include <i2c.h>
16#include <power/pmic.h>
17#include <power/marvell88pm_pmic.h>
18
19#ifdef CONFIG_TZ_HYPERVISOR
20#include <pxa_tzlc.h>
21#endif
22
23DECLARE_GLOBAL_DATA_PTR;
24
25#define APMU_BASE 0xD4282800
26#define APMU_REG(x) (APMU_BASE + x)
27#define MPMU_BASE 0xD4050000
28#define MPMU_REG(x) (MPMU_BASE + x)
29#define APB_SPARE_BASE 0xD4090000
30#define APB_SPARE_REG(x) (APB_SPARE_BASE + x)
31#define CIU_BASE 0xD4282C00
32#define CIU_REG(x) (CIU_BASE + x)
33#define AXI_PHYS_BASE 0xd4200000
34/* PLL */
35#define MPMU_PLL2CR MPMU_REG(0x0034)
36#define MPMU_PLL3CR MPMU_REG(0x001c)
37#define APB_SPARE_PLL2CR APB_SPARE_REG(0x104)
38#define APB_SPARE_PLL3CR APB_SPARE_REG(0x108)
39
40#define APB_PLL2_PI_CTRL APB_SPARE_REG(0x118)
41#define APB_PLL2_SSC_CTRL APB_SPARE_REG(0x11C)
42#define APB_PLL2_FREQOFFSET_CTRL APB_SPARE_REG(0x120)
43#define APB_PLL3_PI_CTRL APB_SPARE_REG(0x124)
44#define APB_PLL3_SSC_CTRL APB_SPARE_REG(0x128)
45#define APB_PLL3_FREQOFFSET_CTRL APB_SPARE_REG(0x12C)
46#define MPMU_POSR MPMU_REG(0x0010)
47
48/* FC */
49#define APMU_CP_CCR APMU_REG(0x0000)
50#define APMU_CCR APMU_REG(0x0004)
51#define APMU_CCSR APMU_REG(0x000c)
52
53#define APMU_IMR APMU_REG(0x0098)
54#define APMU_ISR APMU_REG(0x00a0)
55#define APMU_PLL_SEL_STATUS APMU_REG(0x00c4)
56#define APMU_MC_HW_SLP_TYPE APMU_REG(0x00b0)
57
58#define APMU_CC2R APMU_REG(0x0100)
59#define APMU_CC2SR APMU_REG(0x0104)
60
61#define MPMU_FCCR MPMU_REG(0x0008)
62
63/* clock gating */
64#define MC_CONF CIU_REG(0x40)
65#define APMU_MCK4_CTRL APMU_REG(0x0e8)
66
67/* core WTC/RTC */
68#define CIU_CA9_CPU_CONF_SRAM_0 CIU_REG(0x00c8)
69#define CIU_CA9_CPU_CONF_SRAM_1 CIU_REG(0x00cc)
70
71/* FUSE */
72#define UIMAINFUSE_95_64 (AXI_PHYS_BASE + 0x1418)
73#define BLOCK0_224_255 (AXI_PHYS_BASE + 0x1420)
74
75/*
76 * for ana_grp PU_CLK contro. Must be enabled if
77 * PLL2 or PLL3 or USB are used
78 */
79#define UTMI_CTRL 0xD4207104
80
81#define AP_SRC_SEL_MASK 0x7
82#define UNDEF_OP -1
83#define MHZ (1000 * 1000)
84#define MHZ_TO_KHZ (1000)
85
86#ifdef CONFIG_FINE_TUNED_SVC
87#define PROFILE_NUM 11
88#else
89#define PROFILE_NUM 8
90#endif
91
92#define PLL3_VCO_MIN (1200)
93#define PLL3_VCO_MAX (2500)
94
95enum {
96 CORE_1P18G = 1183,
97 CORE_1P25G = 1248,
98 CORE_1P5G = 1482,
99};
100
101union pmum_pll2cr {
102 struct {
103 unsigned int reserved0:6;
104 unsigned int reserved1:2;
105 unsigned int en:1;
106 unsigned int ctrl:1;
107 unsigned int pll2fbd:9;
108 unsigned int pll2refd:5;
109 unsigned int reserved2:8;
110 } b;
111 unsigned int v;
112};
113
114union pmum_pll3cr {
115 struct {
116 unsigned int pll3refd:5;
117 unsigned int pll3fbd:9;
118 unsigned int reserved0:4;
119 unsigned int pclk_1248_sel:1;
120 unsigned int pll3_pu:1;
121 unsigned int reserved1:12;
122 } b;
123 unsigned int v;
124};
125
126union apb_spare_pllswcr {
127 struct {
128 unsigned int lineupen:1;
129 unsigned int gatectl:1;
130 unsigned int bypassen:1;
131 unsigned int diffclken:1;
132 unsigned int divselse:4;
133 unsigned int divseldiff:4;
134 unsigned int ctune:2;
135 unsigned int vcovnrg:3;
136 unsigned int kvco:4;
137 unsigned int icp:3;
138 unsigned int vreg_ivreg:2;
139 unsigned int vddl:4;
140 unsigned int vddm:2;
141 } b;
142 unsigned int v;
143};
144
145union pmum_posr {
146 struct {
147 unsigned int pll1fbd:9;
148 unsigned int pll1refd:5;
149 unsigned int pll2fbd:9;
150 unsigned int pll2refd:5;
151 unsigned int reserved:4;
152 } b;
153 unsigned int v;
154};
155
156union pmum_fccr {
157 struct {
158 unsigned int pll1fbd:9;
159 unsigned int pll1refd:5;
160 unsigned int pll1cen:1;
161 unsigned int mfc:1;
162 unsigned int reserved0:3;
163 unsigned int axiclksel0:1;
164 unsigned int reserved1:3;
165 unsigned int ddrclksel:2;
166 unsigned int axiclksel1:1;
167 unsigned int seaclksel:2;
168 unsigned int i2sclksel:1;
169 unsigned int mohclksel:3;
170 } b;
171 unsigned int v;
172};
173
174union pmua_pllsel {
175 struct {
176 unsigned int cpclksel:2;
177 unsigned int apclksel:2;
178 unsigned int ddrclksel:2;
179 unsigned int axiclksel:2;
180 unsigned int reserved0:24;
181 } b;
182 unsigned int v;
183};
184
185union pmua_cc {
186 struct {
187 unsigned int core_clk_div:3;
188 unsigned int bus_mc_clk_div:3;
189 unsigned int biu_clk_div:3;
190 unsigned int l2_clk_div:3;
191 unsigned int ddr_clk_div:3;
192 unsigned int bus_clk_div:3;
193 unsigned int async1:1;
194 unsigned int async2:1;
195 unsigned int async3:1;
196 unsigned int async3_1:1;
197 unsigned int async4:1;
198 unsigned int async5:1;
199 unsigned int core_freq_chg_req:1;
200 unsigned int ddr_freq_chg_req:1;
201 unsigned int bus_freq_chg_req:1;
202 unsigned int core_allow_spd_chg:1;
203 unsigned int core_dyn_fc:1;
204 unsigned int dclk_dyn_fc:1;
205 unsigned int aclk_dyn_fc:1;
206 unsigned int core_rd_st_clear:1;
207 } b;
208 unsigned int v;
209};
210
211union pmua_cc2 {
212 struct {
213 unsigned int peri_clk_div:3;
214 unsigned int peri_clk_dis:1;
215 unsigned int reserved0:12;
216 unsigned int cpu0_core_rst:1;
217 unsigned int reserved1:1;
218 unsigned int cpu0_dbg_rst:1;
219 unsigned int cpu0_wdt_rst:1;
220 unsigned int cpu1_core_rst:1;
221 unsigned int reserved2:1;
222 unsigned int cpu1_dbg_rst:1;
223 unsigned int cpu1_wdt_rst:1;
224 unsigned int reserved3:8;
225 } b;
226 unsigned int v;
227};
228
229union pmua_dm_cc {
230 struct {
231 unsigned int core_clk_div:3;
232 unsigned int bus_mc_clk_div:3;
233 unsigned int biu_clk_div:3;
234 unsigned int l2_clk_div:3;
235 unsigned int ddr_clk_div:3;
236 unsigned int bus_clk_div:3;
237 unsigned int async1:1;
238 unsigned int async2:1;
239 unsigned int async3:1;
240 unsigned int async3_1:1;
241 unsigned int async4:1;
242 unsigned int async5:1;
243 unsigned int cp_rd_status:1;
244 unsigned int ap_rd_status:1;
245 unsigned int cp_fc_done:1;
246 unsigned int ap_fc_done:1;
247 unsigned int dclk_fc_done:1;
248 unsigned int aclk_fc_done:1;
249 unsigned int reserved:2;
250 } b;
251 unsigned int v;
252};
253
254union pmua_dm_cc2 {
255 struct {
256 unsigned int peri_clk_div:3;
257 unsigned int reserved:29;
258 } b;
259 unsigned int v;
260};
261
262union apb_pllx_pi_ctrl {
263 struct {
264 unsigned int pi_en:1;
265 unsigned int ssc_clk_en:1;
266 unsigned int clk_det_en:1;
267 unsigned int reset_ext:1;
268 unsigned int intpi:4;
269 unsigned int sel_vco_se:1;
270 unsigned int sel_vco_diff:1;
271 unsigned int reserved:22;
272 } b;
273 unsigned int v;
274};
275
276union apb_pllx_ssc_ctrl {
277 struct {
278 unsigned int ssc_en:1;
279 unsigned int ssc_mode:1;
280 unsigned int ssc_reset_ext:1;
281 unsigned int ssc_rnge:11;
282 unsigned int reserved:2;
283 unsigned int ssc_freq_div:16;
284 } b;
285 unsigned int v;
286};
287
288union apb_pllx_freqoffset_ctrl {
289 struct {
290 unsigned int freq_offset_en:1;
291 unsigned int freq_offset_valid:1;
292 unsigned int freq_offset:17;
293 unsigned int reserve_in:4;
294 unsigned int reserved:9;
295 } b;
296 unsigned int v;
297};
298
299/*
300 * AP clock source:
301 * 0x0 = PLL1 624 MHz
302 * 0x1 = PLL1 1248 MHz or PLL3_CLKOUT
303 * (depending on PLL3_CR[18])
304 * 0x2 = PLL2_CLKOUT
305 * 0x3 = PLL2_CLKOUTP
306 */
307enum ap_clk_sel {
308 AP_CLK_SRC_PLL1_624 = 0x0,
309 AP_CLK_SRC_PLL1_1248 = 0x1,
310 AP_CLK_SRC_PLL2 = 0x2,
311 AP_CLK_SRC_PLL2P = 0x3,
312 AP_CLK_SRC_PLL3P = 0x11,
313};
314
315/*
316 * DDR/AXI clock source:
317 * 0x0 = PLL1 416 MHz
318 * 0x1 = PLL1 624 MHz
319 * 0x2 = PLL2_CLKOUT
320 * 0x3 = PLL2_CLKOUTP
321 */
322enum ddr_axi_clk_sel {
323 DDR_AXI_CLK_SRC_PLL1_416 = 0x0,
324 DDR_AXI_CLK_SRC_PLL1_624 = 0x1,
325 DDR_AXI_CLK_SRC_PLL2 = 0x2,
326 DDR_AXI_CLK_SRC_PLL2P = 0x3,
327};
328
329enum ddr_type {
330 LPDDR2_400M = 0,
331 LPDDR2_533M,
332 DDR3_533M,
333};
334
335enum ssc_mode {
336 CENTER_SPREAD = 0x0,
337 DOWN_SPREAD = 0x1,
338};
339
340struct pll_post_div {
341 unsigned int div; /* PLL divider value */
342 unsigned int divselval; /* PLL corresonding reg setting */
343};
344
345/* RTC/WTC table used for solution change rtc/wtc on the fly */
346struct cpu_rtcwtc {
347 /* max rate could be used by this rtc/wtc */
348 unsigned int max_pclk;
349 unsigned int l1_rtc;
350 unsigned int l2_rtc;
351};
352
353
354struct pxa988_cpu_opt {
355 unsigned int pclk; /* core clock */
356 unsigned int l2clk; /* L2 cache interface clock */
357 unsigned int pdclk; /* DDR interface clock */
358 unsigned int baclk; /* bus interface clock */
359 unsigned int periphclk; /* PERIPHCLK */
360 enum ap_clk_sel ap_clk_sel; /* core src sel val */
361 unsigned int ap_clk_src; /* core src rate */
362 unsigned int pclk_div; /* core clk divider*/
363 unsigned int l2clk_div; /* L2 clock divider */
364 unsigned int pdclk_div; /* DDR interface clock divider */
365 unsigned int baclk_div; /* bus interface clock divider */
366 unsigned int periphclk_div; /* PERIPHCLK divider */
367 unsigned int l1_rtc; /* L1 cache RTC/WTC */
368 unsigned int l2_rtc; /* L2 cache RTC/WTC */
369 struct list_head node;
370};
371
372struct pxa988_ddr_axi_opt {
373 unsigned int dclk; /* ddr clock */
374 unsigned int ddr_tbl_index; /* ddr FC table index */
375 unsigned int aclk; /* axi clock */
376 enum ddr_axi_clk_sel ddr_clk_sel;/* ddr src sel val */
377 enum ddr_axi_clk_sel axi_clk_sel;/* axi src sel val */
378 unsigned int ddr_clk_src; /* ddr src rate */
379 unsigned int axi_clk_src; /* axi src rate */
380 unsigned int dclk_div; /* ddr clk divider */
381 unsigned int aclk_div; /* axi clk divider */
382};
383
384/*
385 * used to show the bind relationship of cpu,ddr,axi
386 * only used when core,ddr,axi FC bind together
387 */
388struct operating_point {
389 u32 pclk;
390 u32 dclk;
391 u32 aclk;
392 u32 vcore;
393};
394
395struct platform_opt {
396 unsigned int cpuid;
397 unsigned int chipid;
398 enum ddr_type ddrtype;
399 char *cpu_name;
400 struct operating_point *op_array;
401 unsigned int com_op_size;
402 struct pxa988_cpu_opt *cpu_opt;
403 unsigned int cpu_opt_size;
404 struct pxa988_ddr_axi_opt *ddr_axi_opt;
405 unsigned int ddr_axi_opt_size;
406 /* pll2 & pll3 freq used on this platform */
407 unsigned int pll2vcofreq;
408 unsigned int pll2freq;
409 unsigned int pll2pfreq;
410 unsigned int pll3vcofreq;
411 unsigned int pll3freq;
412 unsigned int pll3pfreq;
413 /* the default max cpu rate could be supported */
414 unsigned int df_max_cpurate;
415 /* the plat rule for filter core ops */
416 unsigned int (*is_cpuop_invalid_plt)(struct pxa988_cpu_opt *cop);
417};
418
419#define OP(p, d, a) \
420 { \
421 .pclk = p, \
422 .dclk = d, \
423 .aclk = a, \
424 .vcore = 0, \
425 }
426
427
428#define debug_wt_reg(val, reg) __raw_writel(val, reg)
429
430/* current platform OP struct */
431static struct platform_opt *cur_platform_opt;
432
433static LIST_HEAD(core_op_list);
434
435/* current core OP */
436static struct pxa988_cpu_opt *cur_cpu_op;
437
438/* current DDR/AXI OP */
439static struct pxa988_ddr_axi_opt *cur_ddr_op;
440static struct pxa988_ddr_axi_opt *cur_axi_op;
441
442static unsigned int cpu_sel2_srcrate(enum ap_clk_sel ap_sel);
443static unsigned int ddr_axi_sel2_srcrate(enum ddr_axi_clk_sel ddr_axi_sel);
444
445static int set_volt(u32 vol);
446static int get_volt(void);
447
448static int is_1p5G_chip(void);
449
450static unsigned int core_selected_max;
451
452/*
453 * used to record dummy boot up PP, define it here
454 * as the default src and div value read from register
455 * is NOT the real core and ddr,axi rate.
456 * This default boot OP is from PP table.
457 */
458static struct pxa988_cpu_opt pxa988_cpu_bootop = {
459 .pclk = 312,
460 .pdclk = 78,
461 .baclk = 78,
462 .ap_clk_src = 624,
463};
464
465static struct pxa988_ddr_axi_opt pxa988_ddraxi_bootop = {
466 .dclk = 104,
467 .aclk = 104,
468 .ddr_clk_src = 416,
469 .axi_clk_src = 416,
470};
471
472static struct pxa988_cpu_opt pxa1088_op_array[] = {
473 {
474 .pclk = 156,
475 .pdclk = 78,
476 .baclk = 78,
477 .ap_clk_sel = AP_CLK_SRC_PLL1_624,
478 },
479 {
480 .pclk = 312,
481 .pdclk = 156,
482 .baclk = 156,
483 .ap_clk_sel = AP_CLK_SRC_PLL1_624,
484 },
485 {
486 .pclk = 624,
487 .pdclk = 312,
488 .baclk = 156,
489 .ap_clk_sel = AP_CLK_SRC_PLL1_624,
490 },
491 {
492 .pclk = 800,
493 .pdclk = 400,
494 .baclk = 200,
495 .ap_clk_sel = AP_CLK_SRC_PLL2P,
496 },
497 {
498 .pclk = 1066,
499 .pdclk = 533,
500 .baclk = 266,
501 .ap_clk_sel = AP_CLK_SRC_PLL2P,
502 },
503 {
504 .pclk = 1101,
505 .pdclk = 550,
506 .baclk = 275,
507 .ap_clk_sel = AP_CLK_SRC_PLL3P,
508 },
509 {
510 .pclk = 1183,
511 .pdclk = 591,
512 .baclk = 295,
513 .ap_clk_sel = AP_CLK_SRC_PLL3P,
514 },
515#ifdef CONFIG_CORE_1248
516 {
517 .pclk = 1248,
518 .pdclk = 624,
519 .baclk = 312,
520 .ap_clk_sel = AP_CLK_SRC_PLL1_1248,
521 },
522#endif
523 {
524 .pclk = 1283,
525 .pdclk = 641,
526 .baclk = 320,
527 .ap_clk_sel = AP_CLK_SRC_PLL3P,
528 },
529 {
530 .pclk = 1482,
531 .pdclk = 741,
532 .baclk = 370,
533 .ap_clk_sel = AP_CLK_SRC_PLL3P,
534 },
535};
536
537/*
538 * 1) Please don't select ddr from pll1 but axi from pll2
539 * 2) FIXME: high ddr request means high axi is NOT
540 * very reasonable
541 */
542static struct pxa988_ddr_axi_opt lpddr400_axi_oparray_1088[] = {
543 {
544 .dclk = 156,
545 .ddr_tbl_index = 1,
546 .aclk = 78,
547 .ddr_clk_sel = DDR_AXI_CLK_SRC_PLL1_624,
548 .axi_clk_sel = DDR_AXI_CLK_SRC_PLL1_624,
549 },
550 {
551 .dclk = 312,
552 .ddr_tbl_index = 3,
553 .aclk = 156,
554 .ddr_clk_sel = DDR_AXI_CLK_SRC_PLL1_624,
555 .axi_clk_sel = DDR_AXI_CLK_SRC_PLL1_624,
556 },
557 {
558 .dclk = 400,
559 .ddr_tbl_index = 5,
560 .aclk = 200,
561 .ddr_clk_sel = DDR_AXI_CLK_SRC_PLL2P,
562 .axi_clk_sel = DDR_AXI_CLK_SRC_PLL2P,
563 },
564};
565
566static struct pxa988_ddr_axi_opt lpddr533_axi_oparray_1088[] = {
567 {
568 .dclk = 156,
569 .ddr_tbl_index = 1,
570 .aclk = 78,
571 .ddr_clk_sel = DDR_AXI_CLK_SRC_PLL1_624,
572 .axi_clk_sel = DDR_AXI_CLK_SRC_PLL1_624,
573 },
574 {
575 .dclk = 312,
576 .ddr_tbl_index = 3,
577 .aclk = 156,
578 .ddr_clk_sel = DDR_AXI_CLK_SRC_PLL1_624,
579 .axi_clk_sel = DDR_AXI_CLK_SRC_PLL1_624,
580 },
581 {
582 .dclk = 533,
583 .ddr_tbl_index = 5,
584 .aclk = 266,
585 .ddr_clk_sel = DDR_AXI_CLK_SRC_PLL2P,
586 .axi_clk_sel = DDR_AXI_CLK_SRC_PLL2P,
587 },
588};
589
590static struct pxa988_ddr_axi_opt lpddr400_axi_oparray_1920[] = {
591 {
592 .dclk = 156,
593 .ddr_tbl_index = 2,
594 .aclk = 78,
595 .ddr_clk_sel = DDR_AXI_CLK_SRC_PLL1_624,
596 .axi_clk_sel = DDR_AXI_CLK_SRC_PLL1_624,
597 },
598 {
599 .dclk = 312,
600 .ddr_tbl_index = 3,
601 .aclk = 156,
602 .ddr_clk_sel = DDR_AXI_CLK_SRC_PLL1_624,
603 .axi_clk_sel = DDR_AXI_CLK_SRC_PLL1_624,
604 },
605 {
606 .dclk = 400,
607 .ddr_tbl_index = 4,
608 .aclk = 200,
609 .ddr_clk_sel = DDR_AXI_CLK_SRC_PLL2P,
610 .axi_clk_sel = DDR_AXI_CLK_SRC_PLL2P,
611 },
612};
613
614static struct pxa988_ddr_axi_opt lpddr533_axi_oparray_1920[] = {
615 {
616 .dclk = 156,
617 .ddr_tbl_index = 2,
618 .aclk = 78,
619 .ddr_clk_sel = DDR_AXI_CLK_SRC_PLL1_624,
620 .axi_clk_sel = DDR_AXI_CLK_SRC_PLL1_624,
621 },
622 {
623 .dclk = 312,
624 .ddr_tbl_index = 3,
625 .aclk = 156,
626 .ddr_clk_sel = DDR_AXI_CLK_SRC_PLL1_624,
627 .axi_clk_sel = DDR_AXI_CLK_SRC_PLL1_624,
628 },
629 {
630 .dclk = 533,
631 .ddr_tbl_index = 4,
632 .aclk = 266,
633 .ddr_clk_sel = DDR_AXI_CLK_SRC_PLL2P,
634 .axi_clk_sel = DDR_AXI_CLK_SRC_PLL2P,
635 },
636};
637/*
638 * bind relationship bewteen core and ddr&axi
639 * all possible combination can be showed here
640 * op 0~4 formal safe op
641 * From op5 test op
642 */
643struct operating_point op_array_1088_lpddr400[] = {
644 /* pclk dclk aclk vcc_core */
645 OP(156, 156, 78), /* op0 */
646 OP(312, 156, 78), /* op1 */
647 OP(624, 312, 156), /* op2 */
648 OP(800, 400, 200), /* op3 */
649#ifdef CONFIG_CORE_1248
650 OP(1248, 400, 200), /* op4 */
651#else
652 OP(1101, 400, 200), /* op4 */
653 OP(1183, 400, 200), /* op5 */
654 OP(1283, 400, 200), /* op6 */
655 OP(1482, 400, 200), /* op7 */
656 /* Add PP for testing here */
657 OP(624, 400, 200), /* op4 */
658 OP(800, 312, 156), /* op5 */
659 OP(1101, 312, 156), /* op6 */
660 OP(1183, 312, 156), /* op7 */
661 OP(1283, 312, 156), /* op8 */
662 OP(1482, 312, 156), /* op9 */
663#endif
664};
665
666struct operating_point op_array_1088_lpddr533[] = {
667 /* pclk dclk aclk vcc_core */
668 OP(156, 156, 78), /* op0 */
669 OP(312, 156, 78), /* op1 */
670 OP(624, 312, 156), /* op2 */
671 OP(1066, 533, 266), /* op3 */
672#ifdef CONFIG_CORE_1248
673 OP(1248, 533, 266), /* op4 */
674#else
675 OP(1101, 533, 266), /* op4 */
676 OP(1183, 533, 266), /* op5 */
677 OP(1283, 533, 266), /* op6 */
678 OP(1482, 533, 266), /* op7 */
679 /* Add PP for testing here */
680 OP(624, 533, 266), /* op4 */
681 OP(1066, 312, 156), /* op5 */
682 OP(1101, 312, 156), /* op6 */
683 OP(1183, 312, 156), /* op7 */
684 OP(1283, 312, 156), /* op8 */
685 OP(1482, 312, 156), /* op9 */
686#endif
687};
688
689/*
690 * core and ddr opt combination vary from platform to platform
691 * LPDDR400, pll2vco 1600M, pll2 800M(ddr,core), pll2p 533M(peripheral)
692 * LPDDR533 pll2vco 2132M, pll2 1066M(ddr,core), pll2p 1066M(peripheral)
693 * pll3vco 2000M, pll3 500M(dsi), pll3p 1000M(cpu)
694 */
695static struct platform_opt platform_op_arrays[] = {
696 {
697 .cpuid = 0x8000,
698 .chipid = 0xa01088,
699 .ddrtype = LPDDR2_400M,
700 .cpu_name = "PXA1088",
701 .op_array = op_array_1088_lpddr400,
702 .com_op_size = ARRAY_SIZE(op_array_1088_lpddr400),
703 .cpu_opt = pxa1088_op_array,
704 .cpu_opt_size = ARRAY_SIZE(pxa1088_op_array),
705 .ddr_axi_opt = lpddr400_axi_oparray_1088,
706 .ddr_axi_opt_size = ARRAY_SIZE(lpddr400_axi_oparray_1088),
707 .pll2vcofreq = 1600,
708 .pll2freq = 800,
709 .pll2pfreq = 800,
710 .pll3vcofreq = 2366,
711 .pll3freq = 1183,
712 .pll3pfreq = 1183,
713 .df_max_cpurate = 1183,
714 },
715 {
716 .cpuid = 0x8000,
717 .chipid = 0xa01088,
718 .ddrtype = LPDDR2_533M,
719 .cpu_name = "PXA1088",
720 .op_array = op_array_1088_lpddr533,
721 .com_op_size = ARRAY_SIZE(op_array_1088_lpddr533),
722 .cpu_opt = pxa1088_op_array,
723 .cpu_opt_size = ARRAY_SIZE(pxa1088_op_array),
724 .ddr_axi_opt = lpddr533_axi_oparray_1088,
725 .ddr_axi_opt_size = ARRAY_SIZE(lpddr533_axi_oparray_1088),
726 .pll2vcofreq = 2132,
727 .pll2freq = 1066,
728 .pll2pfreq = 1066,
729 .pll3vcofreq = 2366,
730 .pll3freq = 1183,
731 .pll3pfreq = 1183,
732 .df_max_cpurate = 1183,
733 },
734 {
735 .cpuid = 0x8000,
736 .chipid = 0xf01188,
737 .ddrtype = LPDDR2_400M,
738 .cpu_name = "PXA1L88",
739 .op_array = op_array_1088_lpddr400,
740 .com_op_size = ARRAY_SIZE(op_array_1088_lpddr400),
741 .cpu_opt = pxa1088_op_array,
742 .cpu_opt_size = ARRAY_SIZE(pxa1088_op_array),
743 .ddr_axi_opt = lpddr400_axi_oparray_1920,
744 .ddr_axi_opt_size = ARRAY_SIZE(lpddr400_axi_oparray_1920),
745 .pll2vcofreq = 1600,
746 .pll2freq = 800,
747 .pll2pfreq = 800,
748 .pll3vcofreq = 2366,
749 .pll3freq = 1183,
750 .pll3pfreq = 1183,
751 .df_max_cpurate = 1183,
752 },
753 {
754 .cpuid = 0x8000,
755 .chipid = 0xf01188,
756 .ddrtype = LPDDR2_533M,
757 .cpu_name = "PXA1L88",
758 .op_array = op_array_1088_lpddr533,
759 .com_op_size = ARRAY_SIZE(op_array_1088_lpddr533),
760 .cpu_opt = pxa1088_op_array,
761 .cpu_opt_size = ARRAY_SIZE(pxa1088_op_array),
762 .ddr_axi_opt = lpddr533_axi_oparray_1920,
763 .ddr_axi_opt_size = ARRAY_SIZE(lpddr533_axi_oparray_1920),
764 .pll2vcofreq = 2132,
765 .pll2freq = 710,
766 .pll2pfreq = 1066,
767 .pll3vcofreq = 2366,
768 .pll3freq = 1183,
769 .pll3pfreq = 1183,
770 .df_max_cpurate = 1183,
771 },
772};
773
774enum {
775 VL0 = 0,
776 VL1,
777 VL2,
778 VL3,
779 VL4,
780 VL_MAX,
781};
782
783enum {
784 CORE = 0,
785 DDR_AXI,
786 VM_RAIL_MAX,
787};
788
789/* uboot vmin must support CP/MSA requirement */
790static int vm_mv_1088a0_svc_1p2G[][VL_MAX] = {
791 {1000, 1075, 1300, 1375}, /* profile 0 */
792 {1000, 1075, 1088, 1200}, /* profile 1 */
793 {1000, 1075, 1088, 1200}, /* profile 2 */
794 {1000, 1075, 1125, 1238}, /* profile 3 */
795 {1000, 1075, 1163, 1288}, /* profile 4 */
796 {1000, 1075, 1200, 1325}, /* profile 5 */
797 {1000, 1075, 1238, 1363}, /* profile 6 */
798 {1000, 1075, 1275, 1375}, /* profile 7 */
799 {1000, 1075, 1300, 1375}, /* profile 8 */
800};
801
802static int vm_mv_1088a1_svc_1p2G[][VL_MAX] = {
803 {1000, 1075, 1250, 1375}, /* profile 0 */
804 {1000, 1075, 1088, 1200}, /* profile 1 */
805 {1000, 1075, 1088, 1200}, /* profile 2 */
806 {1000, 1075, 1088, 1238}, /* profile 3 */
807 {1000, 1075, 1125, 1288}, /* profile 4 */
808 {1000, 1075, 1150, 1325}, /* profile 5 */
809 {1000, 1075, 1188, 1363}, /* profile 6 */
810 {1000, 1075, 1225, 1375}, /* profile 7 */
811 {1000, 1075, 1250, 1375}, /* profile 8 */
812};
813
814static int vm_mv_1088a1_svc_1p25G[][VL_MAX] = {
815 {1000, 1075, 1250, 1375}, /* profile 0 */
816 {1000, 1075, 1088, 1225}, /* profile 1 */
817 {1000, 1075, 1088, 1225}, /* profile 2 */
818 {1000, 1075, 1088, 1263}, /* profile 3 */
819 {1000, 1075, 1125, 1313}, /* profile 4 */
820 {1000, 1075, 1150, 1350}, /* profile 5 */
821 {1000, 1075, 1188, 1375}, /* profile 6 */
822 {1000, 1075, 1225, 1375}, /* profile 7 */
823 {1000, 1075, 1250, 1375}, /* profile 8 */
824};
825
826static int vm_mv_1L88a0_svc[][VL_MAX] = {
827 {1113, 1225, 1300, 1375}, /* profile 0 */
828 {1050, 1100, 1175, 1175}, /* profile 1 */
829 {1050, 1100, 1175, 1175}, /* profile 2 */
830 {1050, 1100, 1175, 1175}, /* profile 3 */
831 {1050, 1100, 1175, 1175}, /* profile 4 */
832 {1050, 1100, 1175, 1213}, /* profile 5 */
833 {1050, 1100, 1175, 1250}, /* profile 6 */
834 {1100, 1125, 1200, 1288}, /* profile 7 */
835 {1100, 1150, 1225, 1325}, /* profile 8 */
836 {1100, 1175, 1250, 1350}, /* profile 9 */
837 {1100, 1200, 1275, 1375}, /* profile 10 */
838 {1113, 1225, 1300, 1375}, /* profile 11 */
839};
840
841static int vm_mv_1L88a0_svc_1p25G[][VL_MAX] = {
842 {1113, 1225, 1300, 1375}, /* profile 0 */
843 {1050, 1100, 1175, 1200}, /* profile 1 */
844 {1050, 1100, 1175, 1200}, /* profile 2 */
845 {1050, 1100, 1175, 1200}, /* profile 3 */
846 {1050, 1100, 1175, 1200}, /* profile 4 */
847 {1050, 1100, 1175, 1238}, /* profile 5 */
848 {1050, 1100, 1175, 1275}, /* profile 6 */
849 {1100, 1125, 1200, 1313}, /* profile 7 */
850 {1100, 1150, 1225, 1350}, /* profile 8 */
851 {1100, 1175, 1250, 1375}, /* profile 9 */
852 {1100, 1200, 1275, 1375}, /* profile 10 */
853 {1113, 1225, 1300, 1375}, /* profile 11 */
854};
855
856static int vm_mv_1L88a0c_svc_1p2G[][VL_MAX] = {
857 {1113, 1225, 1275, 1375}, /* profile 0 */
858 {1050, 1100, 1175, 1175}, /* profile 1 */
859 {1050, 1100, 1175, 1175}, /* profile 2 */
860 {1050, 1100, 1175, 1175}, /* profile 3 */
861 {1050, 1100, 1175, 1188}, /* profile 4 */
862 {1050, 1100, 1175, 1200}, /* profile 5 */
863 {1100, 1113, 1175, 1238}, /* profile 6 */
864 {1100, 1138, 1188, 1275}, /* profile 7 */
865 {1100, 1150, 1213, 1313}, /* profile 8 */
866 {1100, 1175, 1225, 1350}, /* profile 9 */
867 {1100, 1200, 1250, 1375}, /* profile 10 */
868 {1113, 1225, 1275, 1375}, /* profile 11 */
869};
870
871static int vm_mv_1L88a0c_umc_svc_1p2G[][VL_MAX] = {
872 {1025, 1225, 1275, 1375}, /* profile 0 */
873 {1025, 1100, 1175, 1175}, /* profile 1 */
874 {1025, 1100, 1175, 1175}, /* profile 2 */
875 {1025, 1100, 1175, 1175}, /* profile 3 */
876 {1025, 1100, 1175, 1188}, /* profile 4 */
877 {1025, 1100, 1175, 1213}, /* profile 5 */
878 {1025, 1100, 1175, 1250}, /* profile 6 */
879 {1025, 1138, 1188, 1275}, /* profile 7 */
880 {1025, 1150, 1213, 1313}, /* profile 8 */
881 {1025, 1175, 1225, 1350}, /* profile 9 */
882 {1025, 1200, 1250, 1375}, /* profile 10 */
883 {1025, 1225, 1275, 1375}, /* profile 11 */
884};
885
886static int vm_mv_1L88a0c_svc_1p25G[][VL_MAX] = {
887 {1113, 1225, 1275, 1375}, /* profile 0 */
888 {1050, 1100, 1175, 1188}, /* profile 1 */
889 {1050, 1100, 1175, 1188}, /* profile 2 */
890 {1050, 1100, 1175, 1188}, /* profile 3 */
891 {1050, 1100, 1175, 1213}, /* profile 4 */
892 {1050, 1100, 1175, 1225}, /* profile 5 */
893 {1100, 1113, 1175, 1263}, /* profile 6 */
894 {1100, 1138, 1188, 1300}, /* profile 7 */
895 {1100, 1150, 1213, 1338}, /* profile 8 */
896 {1100, 1175, 1225, 1363}, /* profile 9 */
897 {1100, 1200, 1250, 1375}, /* profile 10 */
898 {1113, 1225, 1275, 1375}, /* profile 11 */
899};
900
901static int vm_mv_1L88a0c_umc_svc_1p25G[][VL_MAX] = {
902 {1025, 1225, 1275, 1375}, /* profile 0 */
903 {1025, 1100, 1175, 1188}, /* profile 1 */
904 {1025, 1100, 1175, 1188}, /* profile 2 */
905 {1025, 1100, 1175, 1188}, /* profile 3 */
906 {1025, 1100, 1175, 1213}, /* profile 4 */
907 {1025, 1100, 1175, 1225}, /* profile 5 */
908 {1025, 1100, 1175, 1263}, /* profile 6 */
909 {1025, 1138, 1188, 1300}, /* profile 7 */
910 {1025, 1150, 1213, 1338}, /* profile 8 */
911 {1025, 1175, 1225, 1363}, /* profile 9 */
912 {1025, 1200, 1250, 1375}, /* profile 10 */
913 {1025, 1225, 1275, 1375}, /* profile 11 */
914};
915
916static int vm_mv_1L88a0c_svc_1p5G[][VL_MAX] = {
917 {1113, 1225, 1275, 1375}, /* profile 0 */
918 {1050, 1100, 1175, 1275}, /* profile 1 */
919 {1050, 1100, 1175, 1275}, /* profile 2 */
920 {1050, 1100, 1175, 1300}, /* profile 3 */
921 {1050, 1100, 1175, 1325}, /* profile 4 */
922 {1050, 1100, 1175, 1350}, /* profile 5 */
923 {1100, 1113, 1175, 1375}, /* profile 6 */
924 {1100, 1138, 1188, 1375}, /* profile 7 */
925 {1100, 1150, 1213, 1375}, /* profile 8 */
926 {1100, 1175, 1225, 1375}, /* profile 9 */
927 {1100, 1200, 1250, 1375}, /* profile 10 */
928 {1113, 1225, 1275, 1375}, /* profile 11 */
929};
930
931static int vm_mv_1L88a0c_umc_svc_1p5G[][VL_MAX] = {
932 {1025, 1225, 1275, 1375}, /* profile 0 */
933 {1025, 1100, 1175, 1275}, /* profile 1 */
934 {1025, 1100, 1175, 1300}, /* profile 2 */
935 {1025, 1100, 1175, 1325}, /* profile 3 */
936 {1025, 1100, 1175, 1350}, /* profile 4 */
937 {1025, 1100, 1175, 1375}, /* profile 5 */
938 {1025, 1100, 1175, 1375}, /* profile 6 */
939 {1025, 1138, 1188, 1375}, /* profile 7 */
940 {1025, 1150, 1213, 1375}, /* profile 8 */
941 {1025, 1175, 1225, 1375}, /* profile 9 */
942 {1025, 1200, 1250, 1375}, /* profile 10 */
943 {1025, 1225, 1275, 1375}, /* profile 11 */
944};
945
946static unsigned int freqs_cmb_1088a0[VM_RAIL_MAX][VL_MAX] = {
947 { 312, 312, 800, 1300 }, /* CORE */
948 { 156, 156, 312, 533 }, /* DDR/AXI */
949};
950
951static unsigned int freqs_cmb_1088a1[VM_RAIL_MAX][VL_MAX] = {
952 { 312, 312, 800, 1482 }, /* CORE */
953 { 312, 312, 312, 533 }, /* DDR/AXI */
954};
955
956static unsigned int freqs_cmb_1L88[VM_RAIL_MAX][VL_MAX] = {
957 { 312, 624, 800, 1482 }, /* CORE */
958 { 312, 312, 312, 533 }, /* DDR/AXI */
959};
960
961
962/* PLL post divider table */
963static struct pll_post_div pll_post_div_tbl[] = {
964 /* divider, reg vaule */
965 {1, 0},
966 {2, 2},
967 {3, 4},
968 {4, 5},
969 {6, 7},
970 {8, 8},
971};
972
973static unsigned int __clk_pll_vco2intpi(unsigned long vco)
974{
975 unsigned int intpi;
976
977 if (vco >= 2400 && vco <= 2500)
978 intpi = 6;
979 else if (vco >= 2100)
980 intpi = 5;
981 else if (vco >= 1800)
982 intpi = 4;
983 else if (vco >= 1500)
984 intpi = 3;
985 else if (vco >= 1200)
986 intpi = 2;
987 else
988 BUG_ON("Unsupported vco frequency for INTPI!\n");
989
990 return intpi;
991}
992
993/*
994 * Real amplitude percentage = amplitude / base
995*/
996static void __clk_pll_get_divrng(enum ssc_mode mode, unsigned long rate,
997 unsigned int amplitude, unsigned int base,
998 unsigned long vco, unsigned int *div,
999 unsigned int *rng)
1000{
1001 if (amplitude > (25 * base / 1000))
1002 BUG_ON("Amplitude can't exceed 2.5\%\n");
1003 switch (mode) {
1004 case CENTER_SPREAD:
1005 *div = (vco / rate) >> 2;
1006 break;
1007 case DOWN_SPREAD:
1008 *div = (vco / rate) >> 1;
1009 break;
1010 default:
1011 printf("Unsupported SSC MODE!\n");
1012 return;
1013 }
1014 if (*div == 0)
1015 *div = 1;
1016 *rng = (1 << 29) / (*div * base / amplitude);
1017}
1018
1019static void enable_pll2_ssc(enum ssc_mode mode, unsigned int div,
1020 unsigned int rng)
1021{
1022 union apb_pllx_pi_ctrl pll2_pi_ctrl;
1023 union apb_pllx_ssc_ctrl pll2_ssc_ctrl;
1024 unsigned int intpi = __clk_pll_vco2intpi(cur_platform_opt->pll2vcofreq);
1025 pll2_pi_ctrl.v = __raw_readl(APB_PLL2_PI_CTRL);
1026 pll2_pi_ctrl.b.pi_en = 1;
1027 pll2_pi_ctrl.b.ssc_clk_en = 1;
1028 pll2_pi_ctrl.b.clk_det_en = 1;
1029 pll2_pi_ctrl.b.reset_ext = 1;
1030 pll2_pi_ctrl.b.intpi = intpi;
1031 pll2_pi_ctrl.b.sel_vco_diff = 0;
1032 pll2_pi_ctrl.b.sel_vco_se = 0;
1033 __raw_writel(pll2_pi_ctrl.v, APB_PLL2_PI_CTRL);
1034 udelay(1);
1035 pll2_pi_ctrl.b.reset_ext = 0;
1036 __raw_writel(pll2_pi_ctrl.v, APB_PLL2_PI_CTRL);
1037
1038 pll2_ssc_ctrl.v = __raw_readl(APB_PLL2_SSC_CTRL);
1039 pll2_ssc_ctrl.b.ssc_en = 1;
1040 pll2_ssc_ctrl.b.ssc_mode = mode;
1041 pll2_ssc_ctrl.b.ssc_freq_div = div;
1042 pll2_ssc_ctrl.b.ssc_rnge = rng;
1043 __raw_writel(pll2_ssc_ctrl.v, APB_PLL2_SSC_CTRL);
1044}
1045
1046static void disable_pll2_ssc(void)
1047{
1048 union apb_pllx_pi_ctrl pll2_pi_ctrl;
1049 union apb_pllx_ssc_ctrl pll2_ssc_ctrl;
1050 pll2_pi_ctrl.v = __raw_readl(APB_PLL2_PI_CTRL);
1051 pll2_pi_ctrl.b.pi_en = 0;
1052 pll2_pi_ctrl.b.ssc_clk_en = 0;
1053 pll2_pi_ctrl.b.clk_det_en = 0;
1054 pll2_pi_ctrl.b.sel_vco_diff = 1;
1055 pll2_pi_ctrl.b.sel_vco_se = 1;
1056 __raw_writel(pll2_pi_ctrl.v, APB_PLL2_PI_CTRL);
1057 pll2_ssc_ctrl.v = __raw_readl(APB_PLL2_SSC_CTRL);
1058 pll2_ssc_ctrl.b.ssc_en = 0;
1059 __raw_writel(pll2_ssc_ctrl.v, APB_PLL2_SSC_CTRL);
1060}
1061
1062static void enable_pll3_ssc(enum ssc_mode mode, unsigned int div,
1063 unsigned int rng)
1064{
1065 union apb_pllx_pi_ctrl pll3_pi_ctrl;
1066 union apb_pllx_ssc_ctrl pll3_ssc_ctrl;
1067 unsigned int intpi = __clk_pll_vco2intpi(cur_platform_opt->pll3vcofreq);
1068
1069 pll3_pi_ctrl.v = __raw_readl(APB_PLL3_PI_CTRL);
1070 pll3_pi_ctrl.b.pi_en = 1;
1071 pll3_pi_ctrl.b.ssc_clk_en = 1;
1072 pll3_pi_ctrl.b.clk_det_en = 1;
1073 pll3_pi_ctrl.b.reset_ext = 1;
1074 pll3_pi_ctrl.b.intpi = intpi;
1075 pll3_pi_ctrl.b.sel_vco_diff = 0;
1076 pll3_pi_ctrl.b.sel_vco_se = 0;
1077 __raw_writel(pll3_pi_ctrl.v, APB_PLL3_PI_CTRL);
1078 udelay(1);
1079 pll3_pi_ctrl.b.reset_ext = 0;
1080 __raw_writel(pll3_pi_ctrl.v, APB_PLL3_PI_CTRL);
1081
1082 pll3_ssc_ctrl.v = __raw_readl(APB_PLL3_SSC_CTRL);
1083 pll3_ssc_ctrl.b.ssc_en = 1;
1084 pll3_ssc_ctrl.b.ssc_mode = mode;
1085 pll3_ssc_ctrl.b.ssc_freq_div = div;
1086 pll3_ssc_ctrl.b.ssc_rnge = rng;
1087 __raw_writel(pll3_ssc_ctrl.v, APB_PLL3_SSC_CTRL);
1088}
1089
1090static void disable_pll3_ssc(void)
1091{
1092 union apb_pllx_pi_ctrl pll3_pi_ctrl;
1093 union apb_pllx_ssc_ctrl pll3_ssc_ctrl;
1094 pll3_pi_ctrl.v = __raw_readl(APB_PLL3_PI_CTRL);
1095 pll3_pi_ctrl.b.pi_en = 0;
1096 pll3_pi_ctrl.b.ssc_clk_en = 0;
1097 pll3_pi_ctrl.b.clk_det_en = 0;
1098 pll3_pi_ctrl.b.sel_vco_diff = 1;
1099 pll3_pi_ctrl.b.sel_vco_se = 1;
1100 __raw_writel(pll3_pi_ctrl.v, APB_PLL3_PI_CTRL);
1101 pll3_ssc_ctrl.v = __raw_readl(APB_PLL3_SSC_CTRL);
1102 pll3_ssc_ctrl.b.ssc_en = 0;
1103 __raw_writel(pll3_ssc_ctrl.v, APB_PLL3_SSC_CTRL);
1104}
1105
1106#ifdef CONFIG_FINE_TUNED_SVC
1107static unsigned int convert_fuses2profile(unsigned int ui_fuses)
1108{
1109 unsigned int ui_profile = 0;
1110 unsigned int ui_temp = 3, ui_temp2 = 1;
1111 unsigned int i;
1112
1113 for (i = 0; i < PROFILE_NUM; i++) {
1114 ui_temp |= ui_temp2 << (i + 1);
1115 if (ui_temp == ui_fuses)
1116 ui_profile = i + 1;
1117 }
1118
1119 return ui_profile;
1120}
1121#else
1122static unsigned int convert_fuses2profile(unsigned int ui_fuses)
1123{
1124 unsigned int ui_profile = 0;
1125 unsigned int ui_temp = 3, ui_temp2 = 3;
1126 unsigned int i;
1127
1128 for (i = 0; i < PROFILE_NUM; i++) {
1129 ui_temp |= ui_temp2 << (i * 2);
1130 if (ui_temp == ui_fuses)
1131 ui_profile = i + 1;
1132 }
1133
1134 return ui_profile;
1135}
1136#endif
1137
1138#ifdef CONFIG_TZ_HYPERVISOR
1139static int chip_profile;
1140static unsigned int chip_foundry;
1141static int cpu_version;
1142static int chip_support_1p5g;
1143void read_fuse_info(void)
1144{
1145 int ret = -1;
1146 unsigned int ui_fuses;
1147 tzlc_cmd_desc cmd_desc;
1148 tzlc_handle tzlc_hdl;
1149 unsigned int ui_main_fuse_95_64 = 0;
1150
1151 /*
1152 * with TrustZone enabled, fuse related info should be read in
1153 * secure world.
1154 */
1155 tzlc_hdl = pxa_tzlc_create_handle();
1156
1157 memset(&cmd_desc, 0, sizeof(tzlc_cmd_desc));
1158 cmd_desc.op = TZLC_CMD_READ_MANUFACTURING_BITS;
1159 ret = pxa_tzlc_cmd_op(tzlc_hdl, &cmd_desc);
1160
1161 if (ret == 0) {
1162 ui_fuses = cmd_desc.args[0];
1163 ui_main_fuse_95_64 = cmd_desc.args[1];
1164 } else {
1165 printf("error: fail to read fuse - manu. bits\n");
1166 return;
1167 }
1168
1169 pxa_tzlc_destroy_handle(tzlc_hdl);
1170
1171 /* bit 237 ~ 239 for foundry information */
1172 chip_foundry = (ui_fuses >> (237 - 224)) & 0x7;
1173 ui_fuses = (ui_fuses >> 16) & 0x0000FFFF;
1174 if (ui_fuses)
1175 chip_profile =
1176 convert_fuses2profile(ui_fuses);
1177 printf("ui_chip_profile = %d\n", chip_profile);
1178 printf("ui_chip_foundry = %d\n", chip_foundry);
1179
1180 ui_fuses = cmd_desc.args[0];
1181 cpu_version = ((ui_fuses >> 14) & 0x3) ? 1 : 0;
1182 if (cpu_version && (ui_main_fuse_95_64 & (0x1 << 3)))
1183 cpu_version = 2;
1184
1185 if (cpu_is_pxa1L88() && ((ui_main_fuse_95_64 >> 26) & 0x3))
1186 chip_support_1p5g = 1;
1187}
1188
1189/* read cpu profile from FUSE */
1190static int get_profile(void)
1191{
1192 return chip_profile;
1193}
1194
1195/* read cpu foundry from FUSE */
1196static unsigned int get_foundry(void)
1197{
1198 return chip_foundry;
1199}
1200
1201/* read cpu version from FUSE. 0: A0a, 1: A0b, 2: A0c */
1202int get_cpu_version(void)
1203{
1204 return cpu_version;
1205}
1206
1207/* check 1.5G chip from FUSE. 0: 1.2G, 1: 1.5G */
1208static int is_1p5G_chip(void)
1209{
1210 return chip_support_1p5g;
1211}
1212#else
1213/* read cpu profile from FUSE */
1214static int get_profile(void)
1215{
1216 unsigned int ui_dro_avg, ui_chip_profile = 0;
1217 unsigned int ui_main_fuse_95_64 = 0;
1218 unsigned int ui_fuses = 0;
1219 ui_main_fuse_95_64 = __raw_readl(UIMAINFUSE_95_64);
1220 ui_dro_avg = (ui_main_fuse_95_64 >> 4) & 0x3ff;
1221 ui_fuses = __raw_readl(BLOCK0_224_255);
1222 /* bit 240 ~ 255 for Profile information */
1223 ui_fuses = (ui_fuses >> 16) & 0x0000FFFF;
1224 if (ui_fuses)
1225 ui_chip_profile =
1226 convert_fuses2profile(ui_fuses);
1227 printf("ui_dro_avg = %u\n", ui_dro_avg);
1228 printf("ui_chip_profile = %d\n", ui_chip_profile);
1229 return ui_chip_profile;
1230}
1231
1232/* read cpu foundry from FUSE */
1233static unsigned int get_foundry(void)
1234{
1235 unsigned int ui_fuses = 0, ui_chip_foundry = 0;
1236
1237 ui_fuses = __raw_readl(BLOCK0_224_255);
1238 /* bit 237 ~ 239 for foundry information */
1239 ui_chip_foundry = (ui_fuses >> (237 - 224)) & 0x7;
1240 return ui_chip_foundry;
1241}
1242
1243/* read cpu version from FUSE. 0: A0a, 1: A0b, 2: A0c */
1244int get_cpu_version(void)
1245{
1246 unsigned int ui_main_fuse_95_64 = 0;
1247 unsigned int ui_fuses = 0;
1248 int cpu_version;
1249 ui_main_fuse_95_64 = __raw_readl(UIMAINFUSE_95_64);
1250 ui_fuses = __raw_readl(BLOCK0_224_255);
1251 cpu_version = ((ui_fuses >> 14) & 0x3) ? 1 : 0;
1252 if (cpu_version && (ui_main_fuse_95_64 & (0x1 << 3)))
1253 cpu_version = 2;
1254 return cpu_version;
1255}
1256
1257/* check 1.5G chip from FUSE. 0: 1.2G, 1: 1.5G */
1258static int is_1p5G_chip(void)
1259{
1260 unsigned int ui_main_fuse_95_64 = 0;
1261 ui_main_fuse_95_64 = __raw_readl(UIMAINFUSE_95_64);
1262 if (cpu_is_pxa1L88() && ((ui_main_fuse_95_64 >> 26) & 0x3))
1263 return 1;
1264 return 0;
1265}
1266#endif
1267
1268/* convert post div reg setting to divider val */
1269 static unsigned int
1270__attribute__ ((unused)) __pll_divsel2div(unsigned int divselval)
1271{
1272 unsigned int i;
1273
1274 for (i = 0; i < ARRAY_SIZE(pll_post_div_tbl); i++) {
1275 if (divselval == pll_post_div_tbl[i].divselval)
1276 return pll_post_div_tbl[i].div;
1277 }
1278 BUG_ON(i == ARRAY_SIZE(pll_post_div_tbl));
1279 return 0;
1280}
1281
1282/* PLL range 1.2G~2.5G, vco_vrng = kvco */
1283static void __clk_pll_rate2rng(unsigned long rate, unsigned int *kvco,
1284 unsigned int *vco_rng)
1285{
1286 if (rate >= 2400 && rate <= 2500)
1287 *kvco = 7;
1288 else if (rate >= 2150)
1289 *kvco = 6;
1290 else if (rate >= 1950)
1291 *kvco = 5;
1292 else if (rate >= 1750)
1293 *kvco = 4;
1294 else if (rate >= 1550)
1295 *kvco = 3;
1296 else if (rate >= 1350)
1297 *kvco = 2;
1298 else if (rate >= 1200)
1299 *kvco = 1;
1300 else
1301 printf("%s rate %lu out of range!\n", __func__, rate);
1302
1303 *vco_rng = *kvco;
1304}
1305
1306/* rate unit Mhz */
1307static unsigned int __clk_pll_calc_div(unsigned long rate,
1308 unsigned long parent_rate, unsigned int *div)
1309{
1310 unsigned int i;
1311 *div = 0;
1312
1313 for (i = 0; i < ARRAY_SIZE(pll_post_div_tbl); i++) {
1314 if (rate == (parent_rate / pll_post_div_tbl[i].div)) {
1315 *div = pll_post_div_tbl[i].div;
1316 return pll_post_div_tbl[i].divselval;
1317 }
1318 }
1319 BUG_ON(i == ARRAY_SIZE(pll_post_div_tbl));
1320 return 0;
1321}
1322
1323static u32 pll2_is_enabled(void)
1324{
1325 union pmum_pll2cr pll2cr;
1326 pll2cr.v = __raw_readl(MPMU_PLL2CR);
1327
1328 /* ctrl = 0(hw enable) or ctrl = 1&&en = 1(sw enable) */
1329 /* ctrl = 1&&en = 0(sw disable) */
1330 if (pll2cr.b.ctrl && (!pll2cr.b.en))
1331 return 0;
1332 else
1333 return 1;
1334}
1335
1336/*
1337 * Pll2 has two frequency output, pll2 and pll2p
1338 * pll2 and pll2p is divided from pll2 vco
1339 * frequency unit Mhz
1340 */
1341static void set_pll2_freq(u32 pll2vco_freq, u32 pll2_freq, u32 pll2p_freq)
1342{
1343 union pmum_pll2cr pll2cr;
1344 union apb_spare_pllswcr pll2_sw_ctrl;
1345 union pmum_posr pll2posr;
1346 u32 kvco, vcovnrg;
1347 u32 divselse, divseldiff, pll2_div, pll2p_div;
1348
1349 /* do nothing if pll2 is enabled */
1350 if (pll2_is_enabled()) {
1351 printf("Disable Pll2 before change its rate\n");
1352 return;
1353 }
1354
1355 /* calc vco rate range */
1356 __clk_pll_rate2rng(pll2vco_freq, &kvco, &vcovnrg);
1357
1358 /* calc pll2 and pll2p divider */
1359 divselse = __clk_pll_calc_div(pll2_freq, pll2vco_freq, &pll2_div);
1360 divseldiff = __clk_pll_calc_div(pll2p_freq, pll2vco_freq, &pll2p_div);
1361
1362 /* pll2 SW ctrl setting */
1363 pll2_sw_ctrl.v = __raw_readl(APB_SPARE_PLL2CR);
1364 pll2_sw_ctrl.b.vddm = 1;
1365 pll2_sw_ctrl.b.vddl = 9;
1366 pll2_sw_ctrl.b.vreg_ivreg = 2;
1367 pll2_sw_ctrl.b.icp = 4;
1368 pll2_sw_ctrl.b.ctune = 1;
1369 pll2_sw_ctrl.b.bypassen = 0;
1370 pll2_sw_ctrl.b.gatectl = 0;
1371 pll2_sw_ctrl.b.lineupen = 0;
1372 pll2_sw_ctrl.b.diffclken = 1;
1373 pll2_sw_ctrl.b.kvco = kvco;
1374 pll2_sw_ctrl.b.vcovnrg = vcovnrg;
1375 pll2_sw_ctrl.b.divselse = divselse;
1376 pll2_sw_ctrl.b.divseldiff = divseldiff;
1377 debug_wt_reg(pll2_sw_ctrl.v, APB_SPARE_PLL2CR);
1378
1379 /* Refclk/Refdiv = pll2freq/Fbdiv, Refclk = 26M */
1380 pll2cr.v = 0;
1381 pll2cr.b.pll2refd = 3;
1382 pll2cr.b.pll2fbd = pll2vco_freq * pll2cr.b.pll2refd / 26;
1383 /* we must lock refd/fbd first before enabling PLL2 */
1384 pll2cr.b.ctrl = 1;
1385 debug_wt_reg(pll2cr.v, MPMU_PLL2CR);
1386 pll2cr.b.ctrl = 0; /* Let HW control PLL2 */
1387 debug_wt_reg(pll2cr.v, MPMU_PLL2CR);
1388
1389 udelay(100);
1390 pll2posr.v = __raw_readl(MPMU_POSR);
1391 printf("PLL2_VCO enable@%dMhz, PLL2@%dMhz, PLL2P@%dMhz\nSWCR[w%x,r%x] PLLCR[w%x,r%x] PLL2 shadow refd%d, fbd%d\n",
1392 pll2vco_freq, pll2vco_freq / pll2_div,
1393 pll2vco_freq / pll2p_div,
1394 pll2_sw_ctrl.v, __raw_readl(APB_SPARE_PLL2CR),
1395 pll2cr.v, __raw_readl(MPMU_PLL2CR),
1396 pll2posr.b.pll2refd, pll2posr.b.pll2fbd);
1397
1398 return;
1399}
1400
1401/* frequency unit Mhz, return pll2 vco freq */
1402static u32 __attribute__ ((unused)) get_pll2_freq(u32 *pll2_freq,
1403 u32 *pll2p_freq)
1404{
1405 union pmum_pll2cr pll2cr;
1406 union apb_spare_pllswcr pll2_sw_ctl;
1407 u32 pll2_vco, pll2_div, pll2p_div, pll2refd;
1408
1409 /* return 0 if pll2 is disabled(ctrl = 1, en = 0) */
1410 if (!pll2_is_enabled()) {
1411 printf("%s PLL2 is not enabled!\n", __func__);
1412 *pll2_freq = 0;
1413 *pll2p_freq = 0;
1414 return 0;
1415 }
1416
1417 pll2cr.v = __raw_readl(MPMU_PLL2CR);
1418 pll2refd = pll2cr.b.pll2refd;
1419 BUG_ON(pll2refd == 1);
1420
1421 if (pll2refd == 0)
1422 pll2refd = 1;
1423 pll2_vco = 26 * pll2cr.b.pll2fbd / pll2refd;
1424
1425 pll2_sw_ctl.v = __raw_readl(APB_SPARE_PLL2CR);
1426 pll2_div = __pll_divsel2div(pll2_sw_ctl.b.divselse);
1427 pll2p_div = __pll_divsel2div(pll2_sw_ctl.b.divseldiff);
1428 *pll2_freq = pll2_vco / pll2_div;
1429 *pll2p_freq = pll2_vco / pll2p_div;
1430
1431 return pll2_vco;
1432}
1433
1434/*
1435 * 1. Whenever PLL2 is enabled, ensure it's set as HW activation.
1436 * 2. When PLL2 is disabled (no one uses PLL2 as source),
1437 * set it as SW activation.
1438 */
1439static int pll2_refcnt;
1440void turn_off_pll2(void)
1441{
1442 union pmum_pll2cr pll2cr;
1443
1444 pll2_refcnt--;
1445 if (pll2_refcnt < 0)
1446 printf("unmatched pll2_refcnt\n");
1447 if (pll2_refcnt == 0) {
1448 pll2cr.v = __raw_readl(MPMU_PLL2CR);
1449 pll2cr.b.ctrl = 1; /* Let SW control PLL2 */
1450 pll2cr.b.en = 0; /* disable PLL2 by en bit */
1451 __raw_writel(pll2cr.v, MPMU_PLL2CR);
1452 printf("Disable pll2 as it is not used!\n");
1453 if (has_feat_ssc())
1454 disable_pll2_ssc();
1455 }
1456}
1457
1458/* must be called after __init_platform_opt */
1459void turn_on_pll2(void)
1460{
1461 u32 pll2vco, pll2, pll2p;
1462 unsigned int div, rng;
1463
1464 BUG_ON(!cur_platform_opt ||
1465 !cur_platform_opt->pll2vcofreq);
1466
1467 pll2_refcnt++;
1468 if (pll2_refcnt == 1) {
1469 pll2vco = cur_platform_opt->pll2vcofreq;
1470 pll2 = cur_platform_opt->pll2freq;
1471 pll2p = cur_platform_opt->pll2pfreq;
1472 set_pll2_freq(pll2vco, pll2, pll2p);
1473 if (has_feat_ssc()) {
1474 __clk_pll_get_divrng(DOWN_SPREAD, 30000, 25, 1000,
1475 pll2vco * MHZ, &div, &rng);
1476 enable_pll2_ssc(DOWN_SPREAD, div, rng);
1477 }
1478 }
1479}
1480
1481static u32 pll3_is_enabled(void)
1482{
1483 union pmum_pll3cr pll3cr;
1484 pll3cr.v = __raw_readl(MPMU_PLL3CR);
1485
1486 /*
1487 * PLL3CR[19:18] = 0x1, 0x2, 0x3 means PLL3 is enabled.
1488 * PLL3CR[19:18] = 0x0 means PLL3 is disabled
1489 */
1490 if ((!pll3cr.b.pll3_pu) && (!pll3cr.b.pclk_1248_sel))
1491 return 0;
1492 else
1493 return 1;
1494}
1495
1496/*
1497 * 1. Pll3 has two frequency output, pll3 and pll3p
1498 * 2. pll3 and pll3p is divided from pll3 vco, frequency unit Mhz
1499 * 3. SW always sets PLL3CR[19:18] = 0x3 to enable PLL3,
1500 * PLL3CR[19:18] = 0x0 to disable PLL3
1501 * 4. frequency unit Mhz
1502 */
1503void set_pll3_freq(u32 pll3vco_freq, u32 pll3_freq, u32 pll3p_freq)
1504{
1505 union pmum_pll3cr pll3cr;
1506 union apb_spare_pllswcr pll3_sw_ctrl;
1507 u32 kvco, vcovnrg;
1508 u32 divselse, divseldiff, pll3_div, pll3p_div;
1509
1510 /* do nothing if pll3 is enabled */
1511 if (pll3_is_enabled()) {
1512 printf("Disable Pll3 before change its rate\n");
1513 return;
1514 }
1515
1516 /* calc vco rate range */
1517 __clk_pll_rate2rng(pll3vco_freq, &kvco, &vcovnrg);
1518
1519 /* calc pll3 and pll3p divider */
1520 divselse = __clk_pll_calc_div(pll3_freq, pll3vco_freq, &pll3_div);
1521 divseldiff = __clk_pll_calc_div(pll3p_freq, pll3vco_freq, &pll3p_div);
1522
1523 /* pll3 SW ctrl setting */
1524 pll3_sw_ctrl.v = __raw_readl(APB_SPARE_PLL3CR);
1525 pll3_sw_ctrl.b.vddm = 1;
1526 pll3_sw_ctrl.b.vddl = 9;
1527 pll3_sw_ctrl.b.vreg_ivreg = 2;
1528 pll3_sw_ctrl.b.icp = 4;
1529 pll3_sw_ctrl.b.ctune = 1;
1530 pll3_sw_ctrl.b.bypassen = 0;
1531 pll3_sw_ctrl.b.gatectl = 0;
1532 pll3_sw_ctrl.b.lineupen = 0;
1533 pll3_sw_ctrl.b.diffclken = 1;
1534 pll3_sw_ctrl.b.kvco = kvco;
1535 pll3_sw_ctrl.b.vcovnrg = vcovnrg;
1536 pll3_sw_ctrl.b.divselse = divselse;
1537 pll3_sw_ctrl.b.divseldiff = divseldiff;
1538 __raw_writel(pll3_sw_ctrl.v, APB_SPARE_PLL3CR);
1539
1540 /* Refclk/Refdiv = pllvcofreq/Fbdiv, Refclk = 26M */
1541 pll3cr.v = __raw_readl(MPMU_PLL3CR);
1542 pll3cr.b.pll3refd = 3;
1543 pll3cr.b.pll3fbd = pll3vco_freq * pll3cr.b.pll3refd / 26;
1544 pll3cr.b.pll3_pu = 1;
1545 __raw_writel(pll3cr.v, MPMU_PLL3CR);
1546
1547 udelay(100);
1548 printf("PLL3_VCO enable@%dMhz, PLL3@%dMhz, PLL3P@%dMhz\n"
1549 "SWCR[w%x,r%x] PLLCR[w%x,r%x]\n",
1550 pll3vco_freq, pll3vco_freq / pll3_div,
1551 pll3vco_freq / pll3p_div,
1552 pll3_sw_ctrl.v, __raw_readl(APB_SPARE_PLL3CR),
1553 pll3cr.v, __raw_readl(MPMU_PLL3CR));
1554}
1555
1556/* frequency unit Mhz, return pll3 vco freq */
1557static u32 __attribute__ ((unused)) get_pll3_freq(u32 *pll3_freq,
1558 u32 *pll3p_freq)
1559{
1560 union pmum_pll3cr pll3cr;
1561 union apb_spare_pllswcr pll3_sw_ctl;
1562 u32 pll3_vco, pll3_div, pll3p_div, pll3refd;
1563
1564 /* return 0 if pll3 is disabled */
1565 if (!pll3_is_enabled()) {
1566 printf("%s PLL3 is not enabled!\n", __func__);
1567 *pll3_freq = 0;
1568 *pll3p_freq = 0;
1569 return 0;
1570 }
1571
1572 pll3cr.v = __raw_readl(MPMU_PLL3CR);
1573 pll3refd = pll3cr.b.pll3refd;
1574 BUG_ON(pll3refd == 1);
1575 if (pll3refd == 0)
1576 pll3refd = 1;
1577 pll3_vco = 26 * pll3cr.b.pll3fbd / pll3refd;
1578
1579 pll3_sw_ctl.v = __raw_readl(APB_SPARE_PLL3CR);
1580 pll3_div = __pll_divsel2div(pll3_sw_ctl.b.divselse);
1581 pll3p_div = __pll_divsel2div(pll3_sw_ctl.b.divseldiff);
1582 *pll3_freq = pll3_vco / pll3_div;
1583 *pll3p_freq = pll3_vco / pll3p_div;
1584
1585 return pll3_vco;
1586}
1587
1588/* PLL3CR[19:18] = 0 shutdown */
1589static int pll3_refcnt;
1590void turn_off_pll3(void)
1591{
1592 union pmum_pll3cr pll3cr;
1593
1594 pll3_refcnt--;
1595 if (pll3_refcnt < 0)
1596 printf("unmatched pll3_refcnt\n");
1597 if (pll3_refcnt == 0) {
1598 pll3cr.v = __raw_readl(MPMU_PLL3CR);
1599 pll3cr.b.pll3_pu = 0;
1600 pll3cr.b.pclk_1248_sel = 0;
1601 __raw_writel(pll3cr.v, MPMU_PLL3CR);
1602 printf("Disable pll3 as it is not used!\n");
1603 if (has_feat_ssc())
1604 disable_pll3_ssc();
1605 }
1606}
1607
1608/* must be called after __init_platform_opt */
1609void turn_on_pll3(void)
1610{
1611 u32 pll3vco, pll3, pll3p;
1612 unsigned int div, rng;
1613
1614 BUG_ON(!cur_platform_opt ||
1615 !cur_platform_opt->pll3vcofreq);
1616
1617 pll3_refcnt++;
1618 if (pll3_refcnt == 1) {
1619 pll3vco = cur_platform_opt->pll3vcofreq;
1620 pll3 = cur_platform_opt->pll3freq;
1621 pll3p = cur_platform_opt->pll3pfreq;
1622 set_pll3_freq(pll3vco, pll3, pll3p);
1623 if (has_feat_ssc()) {
1624 __clk_pll_get_divrng(CENTER_SPREAD, 30000, 25, 1000,
1625 pll3vco * MHZ, &div, &rng);
1626 enable_pll3_ssc(CENTER_SPREAD, div, rng);
1627 }
1628 }
1629}
1630
1631/* unit MHZ */
1632void set_plat_max_corefreq(u32 max_freq)
1633{
1634 core_selected_max = max_freq;
1635}
1636
1637static void __init_platform_opt(int ddr_mode)
1638{
1639 unsigned int i, chipid = 0;
1640 enum ddr_type ddrtype = LPDDR2_400M;
1641 struct platform_opt *proc;
1642 if (cpu_is_pxa1088())
1643 chipid = 0xa01088;
1644 else if (cpu_is_pxa1L88())
1645 chipid = 0xf01188;
1646 /*
1647 * ddr type is passed from OBM, FC code use this info
1648 * to identify DDR OPs.
1649 */
1650 if (ddr_mode == 0)
1651 ddrtype = LPDDR2_400M;
1652 else if (ddr_mode == 1)
1653 ddrtype = LPDDR2_533M;
1654
1655 for (i = 0; i < ARRAY_SIZE(platform_op_arrays); i++) {
1656 proc = platform_op_arrays + i;
1657 if ((proc->chipid == chipid) && (proc->ddrtype == ddrtype))
1658 break;
1659 }
1660 BUG_ON(i == ARRAY_SIZE(platform_op_arrays));
1661 cur_platform_opt = proc;
1662
1663 if (cpu_is_pxa1088() || cpu_is_pxa1L88()) {
1664 if (!is_1p5G_chip())
1665#ifndef CONFIG_CORE_1248
1666 cur_platform_opt->df_max_cpurate = CORE_1P18G;
1667#else
1668 cur_platform_opt->df_max_cpurate = CORE_1P25G;
1669#endif
1670 else {
1671 if (core_selected_max >
1672 cur_platform_opt->df_max_cpurate)
1673 cur_platform_opt->df_max_cpurate =
1674 core_selected_max;
1675 }
1676 }
1677
1678 /*
1679 * pll3p dedicate for core, and its rate is determined
1680 * by df_max_cpurate
1681 */
1682 if ((cur_platform_opt->df_max_cpurate >
1683 cur_platform_opt->pll3pfreq) &&
1684 (cur_platform_opt->df_max_cpurate != 1248)) {
1685 if (cur_platform_opt->df_max_cpurate <
1686 PLL3_VCO_MIN) {
1687 cur_platform_opt->pll3pfreq =
1688 cur_platform_opt->df_max_cpurate;
1689 cur_platform_opt->pll3freq =
1690 cur_platform_opt->df_max_cpurate;
1691 cur_platform_opt->pll3vcofreq =
1692 2 * cur_platform_opt->df_max_cpurate;
1693 } else {
1694 cur_platform_opt->pll3pfreq =
1695 cur_platform_opt->df_max_cpurate;
1696 cur_platform_opt->pll3freq =
1697 cur_platform_opt->df_max_cpurate;
1698 cur_platform_opt->pll3vcofreq =
1699 cur_platform_opt->df_max_cpurate;
1700 }
1701 BUG_ON((cur_platform_opt->pll3vcofreq < PLL3_VCO_MIN) ||
1702 (cur_platform_opt->pll3vcofreq > PLL3_VCO_MAX));
1703 printf("Platform default max frequency: %dMHZ\n",
1704 cur_platform_opt->df_max_cpurate);
1705 }
1706}
1707
1708static struct cpu_rtcwtc cpu_rtcwtc_1088[] = {
1709 {.max_pclk = 312, .l1_rtc = 0x02222222, .l2_rtc = 0x00002221,},
1710 {.max_pclk = 800, .l1_rtc = 0x02666666, .l2_rtc = 0x00006265,},
1711 {.max_pclk = 1183, .l1_rtc = 0x2AAAAAA, .l2_rtc = 0x0000A2A9,},
1712 {.max_pclk = 1482, .l1_rtc = 0x02EEEEEE, .l2_rtc = 0x0000E2ED,},
1713};
1714
1715static struct cpu_rtcwtc cpu_rtcwtc_tsmc_1L88[] = {
1716 {.max_pclk = 624, .l1_rtc = 0x02222222, .l2_rtc = 0x00002221,},
1717 {.max_pclk = 1066, .l1_rtc = 0x02666666, .l2_rtc = 0x00006265,},
1718 {.max_pclk = 1283, .l1_rtc = 0x2AAAAAA, .l2_rtc = 0x0000A2A9,},
1719 {.max_pclk = 1482, .l1_rtc = 0x02EEEEEE, .l2_rtc = 0x0000E2ED,},
1720};
1721
1722static struct cpu_rtcwtc cpu_rtcwtc_umc_1L88_a0c[] = {
1723 {.max_pclk = 312, .l1_rtc = 0x02222222, .l2_rtc = 0x00002221,},
1724 {.max_pclk = 800, .l1_rtc = 0x02666666, .l2_rtc = 0x00006265,},
1725 {.max_pclk = 1066, .l1_rtc = 0x02AAAAAA, .l2_rtc = 0x0000A2A9,},
1726 {.max_pclk = 1482, .l1_rtc = 0x02EEEEEE, .l2_rtc = 0x0000E2ED,},
1727};
1728
1729static void __init_cpu_rtcwtc(struct pxa988_cpu_opt *cpu_opt)
1730{
1731 struct cpu_rtcwtc *cpu_rtcwtc;
1732 unsigned int size, index, ui_foundry;
1733
1734 if (cpu_is_pxa1088()) {
1735 cpu_rtcwtc = cpu_rtcwtc_1088;
1736 size = ARRAY_SIZE(cpu_rtcwtc_1088);
1737 } else if (cpu_is_pxa1L88()) {
1738 ui_foundry = get_foundry();
1739 if (cpu_is_pxa1L88_a0c() && (ui_foundry == 2)) {
1740 cpu_rtcwtc = cpu_rtcwtc_umc_1L88_a0c;
1741 size = ARRAY_SIZE(cpu_rtcwtc_umc_1L88_a0c);
1742 } else {
1743 cpu_rtcwtc = cpu_rtcwtc_tsmc_1L88;
1744 size = ARRAY_SIZE(cpu_rtcwtc_tsmc_1L88);
1745 }
1746 } else {
1747 panic("Non-Supported cpu type, No rtcwtc is set!\n");
1748 }
1749
1750 for (index = 0; index < size; index++)
1751 if (cpu_opt->pclk <= cpu_rtcwtc[index].max_pclk)
1752 break;
1753 if (index == size)
1754 index = size - 1;
1755
1756 cpu_opt->l1_rtc = cpu_rtcwtc[index].l1_rtc;
1757 cpu_opt->l2_rtc = cpu_rtcwtc[index].l2_rtc;
1758};
1759
1760/* Common condition here if you want to filter the core ops */
1761static unsigned int __is_cpu_op_invalid_com(struct pxa988_cpu_opt *cop)
1762{
1763 unsigned int df_max_cpurate =
1764 cur_platform_opt->df_max_cpurate;
1765
1766 /* If pclk could not drive from src, invalid it */
1767 if (cop->ap_clk_src % cop->pclk)
1768 return 1;
1769 /*
1770 * If pclk > default support max core frequency, invalid it
1771 */
1772 if (df_max_cpurate && (cop->pclk > df_max_cpurate))
1773 return 1;
1774
1775 return 0;
1776};
1777
1778/* plat extra condition here if you want to filter the core ops */
1779static unsigned int __is_cpu_op_invalid_plt(struct pxa988_cpu_opt *cop)
1780{
1781 if (cur_platform_opt->is_cpuop_invalid_plt)
1782 return cur_platform_opt->is_cpuop_invalid_plt(cop);
1783
1784 /* no rule no filter */
1785 return 0;
1786}
1787
1788static void __init_cpu_opt(void)
1789{
1790 struct pxa988_cpu_opt *cpu_opt, *cop;
1791 unsigned int cpu_opt_size = 0, i;
1792
1793 cpu_opt = cur_platform_opt->cpu_opt;
1794 cpu_opt_size = cur_platform_opt->cpu_opt_size;
1795
1796 debug("pclk(src:sel,div) l2clk(src,div)\tpdclk(src,div)\tbaclk(src,div)\tperiphclk(src,div)\n");
1797
1798 printf("ui_chip_foundry = %u\n", get_foundry());
1799
1800 for (i = 0; i < cpu_opt_size; i++) {
1801 cop = &cpu_opt[i];
1802 if (!cop->ap_clk_src)
1803 cop->ap_clk_src =
1804 cpu_sel2_srcrate(cop->ap_clk_sel);
1805 BUG_ON(cop->ap_clk_src < 0);
1806 /* check the invalid condition of this op */
1807 if (__is_cpu_op_invalid_com(cop))
1808 continue;
1809 if (__is_cpu_op_invalid_plt(cop))
1810 continue;
1811 /* add it into core op list */
1812 list_add_tail(&cop->node, &core_op_list);
1813 /* fill the opt related setting */
1814 __init_cpu_rtcwtc(cop);
1815 cop->pclk_div =
1816 cop->ap_clk_src / cop->pclk - 1;
1817 if (cop->l2clk) {
1818 cop->l2clk_div =
1819 cop->pclk / cop->l2clk - 1;
1820 cop->pdclk_div =
1821 cop->l2clk / cop->pdclk - 1;
1822 cop->baclk_div =
1823 cop->l2clk / cop->baclk - 1;
1824 } else {
1825 cop->pdclk_div =
1826 cop->pclk / cop->pdclk - 1;
1827 cop->baclk_div =
1828 cop->pclk / cop->baclk - 1;
1829 }
1830 if (cop->periphclk) {
1831 if (has_feat_periclk_mult2())
1832 cop->periphclk_div =
1833 cop->pclk / (2 * cop->periphclk) - 1;
1834 else
1835 cop->periphclk_div =
1836 cop->pclk / (4 * cop->periphclk) - 1;
1837 }
1838
1839
1840 debug("%d(%d:%d,%d)\t%d([%s],%d)\t%d([%s],%d)\t%d([%s],%d)\t%d([%s],%d)\n",
1841 cop->pclk, cop->ap_clk_src,
1842 cop->ap_clk_sel & AP_SRC_SEL_MASK,
1843 cop->pclk_div,
1844 cop->l2clk, cop->l2clk ? "pclk" : "NULL",
1845 cop->l2clk_div,
1846 cop->pdclk, cop->l2clk ? "l2clk" : "pclk",
1847 cop->pdclk_div,
1848 cop->baclk, cop->l2clk ? "l2clk" : "pclk",
1849 cop->baclk_div,
1850 cop->periphclk,
1851 cop->periphclk ? "pclk" : "NULL",
1852 cop->periphclk_div);
1853 }
1854}
1855
1856static void __init_ddr_axi_opt(void)
1857{
1858 struct pxa988_ddr_axi_opt *ddr_axi_opt, *cop;
1859 unsigned int ddr_axi_opt_size = 0, i;
1860
1861 ddr_axi_opt = cur_platform_opt->ddr_axi_opt;
1862 ddr_axi_opt_size = cur_platform_opt->ddr_axi_opt_size;
1863
1864 debug("dclk(src:sel,div) aclk(src:sel,div)\n");
1865 for (i = 0; i < ddr_axi_opt_size; i++) {
1866 cop = &ddr_axi_opt[i];
1867 cop->ddr_clk_src = ddr_axi_sel2_srcrate(cop->ddr_clk_sel);
1868 cop->axi_clk_src = ddr_axi_sel2_srcrate(cop->axi_clk_sel);
1869 BUG_ON((cop->ddr_clk_src < 0) || (cop->axi_clk_src < 0));
1870 cop->dclk_div =
1871 cop->ddr_clk_src / (2 * cop->dclk) - 1;
1872 cop->aclk_div =
1873 cop->axi_clk_src / cop->aclk - 1;
1874
1875 debug("%d(%d:%d,%d)\t%d(%d:%d,%d)\n",
1876 cop->dclk, cop->ddr_clk_src,
1877 cop->ddr_clk_sel, cop->dclk_div,
1878 cop->aclk, cop->axi_clk_src,
1879 cop->axi_clk_sel, cop->aclk_div);
1880 }
1881}
1882
1883static void __init_fc_setting(void)
1884{
1885 unsigned int regval;
1886 union pmua_cc cc_ap, cc_cp;
1887 /*
1888 * enable AP FC done interrupt for one step,
1889 * while not use three interrupts by three steps
1890 */
1891 __raw_writel((1 << 1), APMU_IMR);
1892
1893 /* always vote for CP allow AP FC */
1894 cc_cp.v = __raw_readl(APMU_CP_CCR);
1895 cc_cp.b.core_allow_spd_chg = 1;
1896 __raw_writel(cc_cp.v, APMU_CP_CCR);
1897
1898 /* CA9 doesn't support halt acknowledge, mask it */
1899 regval = __raw_readl(APMU_DEBUG);
1900 regval |= (1 << 1);
1901 /*
1902 * Always set AP_WFI_FC and CP_WFI_FC, then PMU will
1903 * automaticlly send out clk-off ack when core is WFI
1904 */
1905 regval |= (1 << 21) | (1 << 22);
1906 /*
1907 * mask CP clk-off ack and cp halt ack for DDR/AXI FC
1908 * this bits should be unmasked after cp is released
1909 */
1910 regval |= (1 << 0) | (1 << 3);
1911 __raw_writel(regval, APMU_DEBUG);
1912
1913 /* always use async for DDR, AXI interface */
1914 cc_ap.v = __raw_readl(APMU_CCR);
1915 cc_ap.b.async5 = 1;
1916 cc_ap.b.async4 = 1;
1917 cc_ap.b.async3_1 = 1;
1918 cc_ap.b.async3 = 1;
1919 cc_ap.b.async2 = 1;
1920 cc_ap.b.async1 = 1;
1921 __raw_writel(cc_ap.v, APMU_CCR);
1922
1923 /* use to enable PU_CLK shared by USB, PLL2 and PLL3 */
1924 __raw_writel(__raw_readl(UTMI_CTRL) | (1 << 23), UTMI_CTRL);
1925}
1926
1927static struct pxa988_cpu_opt *cpu_rate2_op_ptr
1928 (unsigned int rate, unsigned int *index)
1929{
1930 unsigned int idx = 0;
1931 struct pxa988_cpu_opt *cop;
1932
1933 list_for_each_entry(cop, &core_op_list, node) {
1934 if ((cop->pclk >= rate) ||
1935 list_is_last(&cop->node, &core_op_list))
1936 break;
1937 idx++;
1938 }
1939
1940 *index = idx;
1941 return cop;
1942}
1943
1944static unsigned int ddr_rate2_op_index(unsigned int rate)
1945{
1946 unsigned int index;
1947 struct pxa988_ddr_axi_opt *op_array =
1948 cur_platform_opt->ddr_axi_opt;
1949 unsigned int op_array_size =
1950 cur_platform_opt->ddr_axi_opt_size;
1951
1952 if (unlikely(rate > op_array[op_array_size - 1].dclk))
1953 return op_array_size - 1;
1954
1955 for (index = 0; index < op_array_size; index++)
1956 if (op_array[index].dclk >= rate)
1957 break;
1958
1959 return index;
1960}
1961
1962static unsigned int axi_rate2_op_index(unsigned int rate)
1963{
1964 unsigned int index;
1965 struct pxa988_ddr_axi_opt *op_array =
1966 cur_platform_opt->ddr_axi_opt;
1967 unsigned int op_array_size =
1968 cur_platform_opt->ddr_axi_opt_size;
1969
1970 if (unlikely(rate > op_array[op_array_size - 1].aclk))
1971 return op_array_size - 1;
1972
1973 for (index = 0; index < op_array_size; index++)
1974 if (op_array[index].aclk >= rate)
1975 break;
1976
1977 return index;
1978}
1979
1980static unsigned int cpu_sel2_srcrate(enum ap_clk_sel ap_sel)
1981{
1982 if (ap_sel == AP_CLK_SRC_PLL1_624)
1983 return 624;
1984 else if (ap_sel == AP_CLK_SRC_PLL1_1248)
1985 return 1248;
1986 else if (ap_sel == AP_CLK_SRC_PLL2)
1987 return cur_platform_opt->pll2freq;
1988 else if (ap_sel == AP_CLK_SRC_PLL2P)
1989 return cur_platform_opt->pll2pfreq;
1990 else if (ap_sel == AP_CLK_SRC_PLL3P)
1991 return cur_platform_opt->pll3pfreq;
1992 printf("%s bad ap_clk_sel %d\n", __func__, ap_sel);
1993 return -ENOENT;
1994}
1995
1996static unsigned int ddr_axi_sel2_srcrate(enum ddr_axi_clk_sel ddr_axi_sel)
1997{
1998 if (ddr_axi_sel == DDR_AXI_CLK_SRC_PLL1_416)
1999 return 416;
2000 else if (ddr_axi_sel == DDR_AXI_CLK_SRC_PLL1_624)
2001 return 624;
2002 else if (ddr_axi_sel == DDR_AXI_CLK_SRC_PLL2)
2003 return cur_platform_opt->pll2freq;
2004 else if (ddr_axi_sel == DDR_AXI_CLK_SRC_PLL2P)
2005 return cur_platform_opt->pll2pfreq;
2006 printf("%s bad ddr_axi_sel %d\n", __func__, ddr_axi_sel);
2007 return -ENOENT;
2008}
2009
2010static unsigned int clk_enable(unsigned int src)
2011{
2012 /*
2013 * The value is the same at case:
2014 * DDR_AXI_CLK_SRC_PLL2 & AP_CLK_SRC_PLL2
2015 * DDR_AXI_CLK_SRC_PLL2P& AP_CLK_SRC_PLL2P
2016 */
2017 switch (src) {
2018 case AP_CLK_SRC_PLL2:
2019 case AP_CLK_SRC_PLL2P:
2020 turn_on_pll2();
2021 break;
2022 case AP_CLK_SRC_PLL3P:
2023 turn_on_pll3();
2024 break;
2025 default:
2026 break;
2027 }
2028 return 0;
2029}
2030
2031static unsigned int clk_disable(unsigned int src)
2032{
2033 switch (src) {
2034 case AP_CLK_SRC_PLL2:
2035 case AP_CLK_SRC_PLL2P:
2036 turn_off_pll2();
2037 break;
2038 case AP_CLK_SRC_PLL3P:
2039 turn_off_pll3();
2040 break;
2041 default:
2042 break;
2043 }
2044 return 0;
2045}
2046
2047static int fc_lock_ref_cnt;
2048static void get_fc_lock(void)
2049{
2050 union pmua_dm_cc dm_cc_ap;
2051
2052 fc_lock_ref_cnt++;
2053
2054 if (fc_lock_ref_cnt == 1) {
2055 int timeout = 100000;
2056
2057 /* AP-CP FC mutual exclusion */
2058 dm_cc_ap.v = __raw_readl(APMU_CCSR);
2059 while (dm_cc_ap.b.cp_rd_status && timeout) {
2060 dm_cc_ap.v = __raw_readl(APMU_CCSR);
2061 timeout--;
2062 }
2063 if (timeout <= 0) {
2064 printf("cp does not release its fc lock\n");
2065 BUG();
2066 }
2067 }
2068}
2069
2070static void put_fc_lock(void)
2071{
2072 union pmua_cc cc_ap;
2073
2074 fc_lock_ref_cnt--;
2075
2076 if (fc_lock_ref_cnt < 0)
2077 printf("unmatched put_fc_lock\n");
2078
2079 if (fc_lock_ref_cnt == 0) {
2080 /* write 1 to MOH_RD_ST_CLEAR to clear MOH_RD_STATUS */
2081 cc_ap.v = __raw_readl(APMU_CCR);
2082 cc_ap.b.core_rd_st_clear = 1;
2083 __raw_writel(cc_ap.v, APMU_CCR);
2084 cc_ap.b.core_rd_st_clear = 0;
2085 __raw_writel(cc_ap.v, APMU_CCR);
2086 }
2087}
2088
2089static void get_cur_cpu_op(struct pxa988_cpu_opt *cop)
2090{
2091 union pmua_pllsel pllsel;
2092 union pmua_dm_cc dm_cc_ap;
2093 union pmua_cc cc_cp;
2094 union pmua_dm_cc2 dm_cc2_ap;
2095 unsigned int pll1_pll3_sel;
2096
2097 get_fc_lock();
2098
2099 dm_cc_ap.v = __raw_readl(APMU_CCSR);
2100 dm_cc2_ap.v = __raw_readl(APMU_CC2SR);
2101 cc_cp.v = __raw_readl(APMU_CP_CCR);
2102 cc_cp.b.core_rd_st_clear = 1;
2103 __raw_writel(cc_cp.v, APMU_CP_CCR);
2104 cc_cp.b.core_rd_st_clear = 0;
2105 __raw_writel(cc_cp.v, APMU_CP_CCR);
2106 pllsel.v = __raw_readl(APMU_PLL_SEL_STATUS);
2107 pll1_pll3_sel = __raw_readl(MPMU_PLL3CR);
2108
2109 cop->ap_clk_src = cpu_sel2_srcrate(pllsel.b.apclksel);
2110 cop->ap_clk_sel = pllsel.b.apclksel;
2111 if ((pllsel.b.apclksel == 0x1) && (pll1_pll3_sel & (1 << 18))) {
2112 cop->ap_clk_src = cpu_sel2_srcrate(AP_CLK_SRC_PLL3P);
2113 cop->ap_clk_sel = AP_CLK_SRC_PLL3P;
2114 }
2115 cop->pclk = cop->ap_clk_src / (dm_cc_ap.b.core_clk_div + 1);
2116 if (cop->l2clk) {
2117 cop->l2clk = cop->pclk / (dm_cc_ap.b.l2_clk_div + 1);
2118 cop->pdclk = cop->l2clk / (dm_cc_ap.b.bus_mc_clk_div + 1);
2119 cop->baclk = cop->l2clk / (dm_cc_ap.b.biu_clk_div + 1);
2120 } else {
2121 cop->pdclk = cop->pclk / (dm_cc_ap.b.bus_mc_clk_div + 1);
2122 cop->baclk = cop->pclk / (dm_cc_ap.b.biu_clk_div + 1);
2123 }
2124 if (cop->periphclk) {
2125 if (has_feat_periclk_mult2())
2126 cop->periphclk =
2127 cop->pclk / (dm_cc2_ap.b.peri_clk_div + 1) / 2;
2128 else
2129 cop->periphclk =
2130 cop->pclk / (dm_cc2_ap.b.peri_clk_div + 1) / 4;
2131 }
2132
2133 put_fc_lock();
2134}
2135
2136static void get_cur_ddr_axi_op(struct pxa988_ddr_axi_opt *cop)
2137{
2138 union pmua_pllsel pllsel;
2139 union pmua_dm_cc dm_cc_ap;
2140 union pmua_cc cc_cp;
2141
2142 get_fc_lock();
2143
2144 dm_cc_ap.v = __raw_readl(APMU_CCSR);
2145 cc_cp.v = __raw_readl(APMU_CP_CCR);
2146 cc_cp.b.core_rd_st_clear = 1;
2147 __raw_writel(cc_cp.v, APMU_CP_CCR);
2148 cc_cp.b.core_rd_st_clear = 0;
2149 __raw_writel(cc_cp.v, APMU_CP_CCR);
2150 pllsel.v = __raw_readl(APMU_PLL_SEL_STATUS);
2151
2152 cop->ddr_clk_src = ddr_axi_sel2_srcrate(pllsel.b.ddrclksel);
2153 cop->ddr_clk_sel = pllsel.b.ddrclksel;
2154 cop->axi_clk_src = ddr_axi_sel2_srcrate(pllsel.b.axiclksel);
2155 cop->axi_clk_sel = pllsel.b.axiclksel;
2156 cop->dclk = cop->ddr_clk_src / (dm_cc_ap.b.ddr_clk_div + 1) / 2;
2157 cop->aclk = cop->axi_clk_src / (dm_cc_ap.b.bus_clk_div + 1);
2158
2159 put_fc_lock();
2160}
2161
2162static void wait_for_fc_done(void)
2163{
2164 int timeout = 1000000;
2165 while (!((1 << 1) & __raw_readl(APMU_ISR)) && timeout)
2166 timeout--;
2167 if (timeout <= 0)
2168 printf("AP frequency change timeout! ISR = 0x%x\n",
2169 __raw_readl(APMU_ISR));
2170 __raw_writel(0x0, APMU_ISR);
2171}
2172
2173static void pll1_pll3_switch(enum ap_clk_sel sel)
2174{
2175 unsigned int regval;
2176
2177 if ((sel != AP_CLK_SRC_PLL3P) && (sel != AP_CLK_SRC_PLL1_1248))
2178 return;
2179
2180 regval = __raw_readl(MPMU_PLL3CR);
2181 if (sel == AP_CLK_SRC_PLL1_1248)
2182 regval &= ~(1 << 18);
2183 else
2184 regval |= (1 << 18);
2185 debug_wt_reg(regval, MPMU_PLL3CR);
2186}
2187
2188static void set_ap_clk_sel(struct pxa988_cpu_opt *top)
2189{
2190 union pmum_fccr fccr;
2191 unsigned int value;
2192
2193 /* sel pll1 and pll3 switch bit */
2194 pll1_pll3_switch(top->ap_clk_sel);
2195
2196 fccr.v = __raw_readl(MPMU_FCCR);
2197 fccr.b.mohclksel =
2198 top->ap_clk_sel & AP_SRC_SEL_MASK;
2199 debug_wt_reg(fccr.v, MPMU_FCCR);
2200 value = __raw_readl(MPMU_FCCR);
2201 if (value != fccr.v)
2202 printf("CORE FCCR Write failure: target 0x%X, final value 0x%X\n",
2203 fccr.v, value);
2204}
2205
2206static void set_periph_clk_div(struct pxa988_cpu_opt *top)
2207{
2208 union pmua_cc2 cc_ap2;
2209
2210 cc_ap2.v = __raw_readl(APMU_CC2R);
2211 cc_ap2.b.peri_clk_div = top->periphclk_div;
2212 debug_wt_reg(cc_ap2.v, APMU_CC2R);
2213}
2214
2215static void set_ddr_clk_sel(struct pxa988_ddr_axi_opt *top)
2216{
2217 union pmum_fccr fccr;
2218 unsigned int value;
2219
2220 fccr.v = __raw_readl(MPMU_FCCR);
2221 fccr.b.ddrclksel = top->ddr_clk_sel;
2222 debug_wt_reg(fccr.v, MPMU_FCCR);
2223 value = __raw_readl(MPMU_FCCR);
2224 if (value != fccr.v)
2225 printf("DDR FCCR Write failure: target 0x%x, final value 0x%X\n",
2226 fccr.v, value);
2227}
2228
2229static void set_axi_clk_sel(struct pxa988_ddr_axi_opt *top)
2230{
2231 union pmum_fccr fccr;
2232 unsigned int value;
2233
2234 fccr.v = __raw_readl(MPMU_FCCR);
2235 fccr.b.axiclksel0 = top->axi_clk_sel & 0x1;
2236 fccr.b.axiclksel1 = (top->axi_clk_sel & 0x2) >> 1;
2237 debug_wt_reg(fccr.v, MPMU_FCCR);
2238 value = __raw_readl(MPMU_FCCR);
2239 if (value != fccr.v)
2240 printf("AXI FCCR Write failure: target 0x%x, final value 0x%X\n",
2241 fccr.v, value);
2242}
2243
2244static void set_ddr_tbl_index(unsigned int index)
2245{
2246 unsigned int regval;
2247
2248 index = (index > 0x7) ? 0x7 : index;
2249 regval = __raw_readl(APMU_MC_HW_SLP_TYPE);
2250 regval &= ~(0x1 << 6); /* enable tbl based FC */
2251 regval &= ~(0x7 << 3); /* clear ddr tbl index */
2252 regval |= (index << 3);
2253 debug_wt_reg(regval, APMU_MC_HW_SLP_TYPE);
2254}
2255
2256/*
2257 * Sequence of changing RTC on the fly
2258 * RTC_lowpp means RTC is better for lowPP
2259 * RTC_highpp means RTC is better for highPP
2260 *
2261 * lowPP -> highPP:
2262 * 1) lowPP(RTC_lowpp) works at Vnom_lowPP(RTC_lowpp)
2263 * 2) Voltage increases from Vnom_lowPP(RTC_lowpp) to
2264 * Vnom_highPP(RTC_highpp)
2265 * 3) RTC changes from RTC_lowpp to RTC_highpp, lowPP(RTC_highpp)
2266 * could work at Vnom_highpp(RTC_highpp) as Vnom_highpp(RTC_highpp)
2267 * >= Vnom_lowpp(RTC_highpp)
2268 * 4) Core freq-chg from lowPP(RTC_highpp) to highPP(RTC_highpp)
2269 *
2270 * highPP -> lowPP:
2271 * 1) highPP(RTC_highpp) works at Vnom_highPP(RTC_highpp)
2272 * 2) Core freq-chg from highPP(RTC_highpp) to lowPP(RTC_highpp),
2273 * voltage could meet requirement as Vnom_highPP(RTC_highpp) >=
2274 * Vnom_lowpp(RTC_highpp)
2275 * 3) RTC changes from RTC_highpp to RTC_lowpp. Vnom_lowpp(RTC_lowpp)
2276 * < Vnom_lowpp(RTC_highpp), the voltage is ok
2277 * 4) voltage decreases from Vnom_highPP(RTC_highpp) to
2278 * Vnom_lowPP(RTC_lowpp)
2279 */
2280static void core_fc_seq(struct pxa988_cpu_opt *cop,
2281 struct pxa988_cpu_opt *top)
2282{
2283 union pmua_cc cc_ap, cc_cp;
2284
2285 /*
2286 * add check here to avoid the case default boot up PP
2287 * has different pdclk and paclk definition with PP used
2288 * in production
2289 */
2290 if ((cop->ap_clk_src == top->ap_clk_src) &&
2291 (cop->pclk == top->pclk) &&
2292 (cop->pdclk == top->pdclk) &&
2293 (cop->baclk == top->baclk)) {
2294 printf("current rate = target rate!\n");
2295 return;
2296 }
2297
2298 /* low -> high */
2299 if ((cop->pclk < top->pclk) && (top->l1_rtc != cop->l1_rtc)) {
2300 __raw_writel(top->l1_rtc, CIU_CA9_CPU_CONF_SRAM_0);
2301 __raw_writel(top->l2_rtc, CIU_CA9_CPU_CONF_SRAM_1);
2302 }
2303
2304 /* 0) Pre FC : check CP allow AP FC voting */
2305 cc_cp.v = __raw_readl(APMU_CP_CCR);
2306 if (unlikely(!cc_cp.b.core_allow_spd_chg)) {
2307 printf("%s CP doesn't allow AP FC!\n", __func__);
2308 cc_cp.b.core_allow_spd_chg = 1;
2309 __raw_writel(cc_cp.v, APMU_CP_CCR);
2310 }
2311
2312 /* 1) Pre FC : AP votes allow FC */
2313 cc_ap.v = __raw_readl(APMU_CCR);
2314 cc_ap.b.core_allow_spd_chg = 1;
2315
2316 /* 2) issue core FC */
2317 /* 2.1) set pclk src */
2318 set_ap_clk_sel(top);
2319 /* 2.2) select div for pclk, l2clk, pdclk, baclk */
2320 cc_ap.b.core_clk_div = top->pclk_div;
2321 if (top->l2clk)
2322 cc_ap.b.l2_clk_div = top->l2clk_div;
2323 cc_ap.b.bus_mc_clk_div = top->pdclk_div;
2324 cc_ap.b.biu_clk_div = top->baclk_div;
2325 /* 2.3) set periphclk div */
2326 if (top->periphclk)
2327 set_periph_clk_div(top);
2328
2329 cc_ap.b.core_freq_chg_req = 1;
2330 /* used only for core FC, will NOT trigger fc_sm */
2331 /* cc_ap.b.core_dyn_fc = 1; */
2332
2333 /* 2.4) set div and FC req trigger core FC */
2334 debug_wt_reg(cc_ap.v, APMU_CCR);
2335 wait_for_fc_done();
2336
2337 /* 3) Post FC : AP clear allow FC voting */
2338 cc_ap.v = __raw_readl(APMU_CCR);
2339 cc_ap.b.core_allow_spd_chg = 0;
2340 __raw_writel(cc_ap.v, APMU_CCR);
2341
2342 /* high -> low */
2343 if ((cop->pclk > top->pclk) && (top->l1_rtc != cop->l1_rtc)) {
2344 __raw_writel(top->l1_rtc, CIU_CA9_CPU_CONF_SRAM_0);
2345 __raw_writel(top->l2_rtc, CIU_CA9_CPU_CONF_SRAM_1);
2346 }
2347}
2348
2349static int set_core_freq(struct pxa988_cpu_opt *old, struct pxa988_cpu_opt *new)
2350{
2351 struct pxa988_cpu_opt cop;
2352 int ret = 0;
2353
2354 printf("CORE FC start: %u -> %u\n", old->pclk, new->pclk);
2355 get_fc_lock();
2356
2357 memcpy(&cop, old, sizeof(struct pxa988_cpu_opt));
2358 clk_enable(new->ap_clk_sel);
2359 core_fc_seq(&cop, new);
2360
2361 memcpy(&cop, new, sizeof(struct pxa988_cpu_opt));
2362 get_cur_cpu_op(&cop);
2363 if (unlikely((cop.ap_clk_src != new->ap_clk_src) ||
2364 (cop.pclk != new->pclk) ||
2365 (cop.l2clk != new->l2clk) ||
2366 (cop.pdclk != new->pdclk) ||
2367 (cop.baclk != new->baclk) ||
2368 (cop.periphclk != new->periphclk))) {
2369 printf("unsuccessful frequency change!\n");
2370 printf("psrc pclk l2clk pdclk baclk periphclk\n");
2371 printf("CUR %d %d %d %d %d %d\n", cop.ap_clk_src,
2372 cop.pclk, cop.l2clk, cop.pdclk, cop.baclk,
2373 cop.periphclk);
2374 printf("NEW %d %d %d %d %d %d\n", new->ap_clk_src,
2375 new->pclk, new->l2clk, new->pdclk, new->baclk,
2376 new->periphclk);
2377 ret = -EAGAIN;
2378 clk_disable(new->ap_clk_sel);
2379 goto out;
2380 }
2381
2382 clk_disable(old->ap_clk_sel);
2383out:
2384 put_fc_lock();
2385 printf("CORE FC end: %u -> %u\n", old->pclk, new->pclk);
2386 return ret;
2387}
2388
2389static int pxa988_cpu_setrate(unsigned long rate)
2390{
2391 struct pxa988_cpu_opt *md_new, *md_old;
2392 unsigned int index;
2393 int ret = 0;
2394 struct pxa988_cpu_opt *op_array =
2395 cur_platform_opt->cpu_opt;
2396
2397 if (unlikely(!cur_cpu_op))
2398 cur_cpu_op = &pxa988_cpu_bootop;
2399 md_new = cpu_rate2_op_ptr(rate, &index);
2400 md_old = cur_cpu_op;
2401
2402 /*
2403 * Switching pll1_1248 and pll3p may generate glitch
2404 * step 1),2),3) is neccessary
2405 */
2406 if (((md_old->ap_clk_sel == AP_CLK_SRC_PLL3P) &&
2407 (md_new->ap_clk_sel == AP_CLK_SRC_PLL1_1248)) ||
2408 ((md_old->ap_clk_sel == AP_CLK_SRC_PLL1_1248) &&
2409 (md_new->ap_clk_sel == AP_CLK_SRC_PLL3P))) {
2410 /* 1) use startup op(op0) as a bridge */
2411 ret = set_core_freq(md_old, &op_array[0]);
2412 if (ret)
2413 return ret;
2414 /* 2) switch to op which uses pll1_1248/pll3p */
2415 ret = set_core_freq(&op_array[0], md_new);
2416 } else {
2417 ret = set_core_freq(md_old, md_new);
2418 }
2419
2420 if (ret)
2421 goto out;
2422 cur_cpu_op = md_new;
2423out:
2424 return ret;
2425}
2426
2427static void ddr_fc_seq(struct pxa988_ddr_axi_opt *cop,
2428 struct pxa988_ddr_axi_opt *top)
2429{
2430 union pmua_cc cc_ap, cc_cp;
2431 unsigned int ddr_axi_fc = 0;
2432
2433 /* 0) Pre FC : check CP allow AP FC voting */
2434 cc_cp.v = __raw_readl(APMU_CP_CCR);
2435 if (unlikely(!cc_cp.b.core_allow_spd_chg)) {
2436 printf("%s CP doesn't allow AP FC!\n", __func__);
2437 cc_cp.b.core_allow_spd_chg = 1;
2438 __raw_writel(cc_cp.v, APMU_CP_CCR);
2439 }
2440
2441 /* 1) Pre FC : AP votes allow FC */
2442 cc_ap.v = __raw_readl(APMU_CCR);
2443 cc_ap.b.core_allow_spd_chg = 1;
2444
2445 /* 2) issue DDR FC */
2446 if ((cop->ddr_clk_src != top->ddr_clk_src) ||
2447 (cop->dclk != top->dclk)) {
2448 /* 2.1) set dclk src */
2449 set_ddr_clk_sel(top);
2450 /* 2.2) enable tbl based FC and set DDR tbl num */
2451 set_ddr_tbl_index(top->ddr_tbl_index);
2452 /* 2.3) select div for dclk */
2453 cc_ap.b.ddr_clk_div = top->dclk_div;
2454 /* 2.4) select ddr FC req bit */
2455 cc_ap.b.ddr_freq_chg_req = 1;
2456 ddr_axi_fc = 1;
2457 }
2458
2459 /* 3) set div and FC req bit trigger DDR/AXI FC */
2460 if (ddr_axi_fc) {
2461 debug_wt_reg(cc_ap.v, APMU_CCR);
2462 wait_for_fc_done();
2463 }
2464
2465 /* 4) Post FC : AP clear allow FC voting */
2466 cc_ap.v = __raw_readl(APMU_CCR);
2467 cc_ap.b.core_allow_spd_chg = 0;
2468 __raw_writel(cc_ap.v, APMU_CCR);
2469}
2470
2471static void axi_fc_seq(struct pxa988_ddr_axi_opt *cop,
2472 struct pxa988_ddr_axi_opt *top)
2473{
2474 union pmua_cc cc_ap, cc_cp;
2475 unsigned int ddr_axi_fc = 0;
2476
2477 /* 0) Pre FC : check CP allow AP FC voting */
2478 cc_cp.v = __raw_readl(APMU_CP_CCR);
2479 if (unlikely(!cc_cp.b.core_allow_spd_chg)) {
2480 printf("%s CP doesn't allow AP FC!\n", __func__);
2481 cc_cp.b.core_allow_spd_chg = 1;
2482 __raw_writel(cc_cp.v, APMU_CP_CCR);
2483 }
2484
2485 /* 1) Pre FC : AP votes allow FC */
2486 cc_ap.v = __raw_readl(APMU_CCR);
2487 cc_ap.b.core_allow_spd_chg = 1;
2488
2489 /* 2) issue AXI FC */
2490 if ((cop->axi_clk_src != top->axi_clk_src) ||
2491 (cop->aclk != top->aclk)) {
2492 /* 3.1) set aclk src */
2493 set_axi_clk_sel(top);
2494 /* 3.2) select div for aclk */
2495 cc_ap.b.bus_clk_div = top->aclk_div;
2496 /* 3.3) select axi FC req bit */
2497 cc_ap.b.bus_freq_chg_req = 1;
2498 ddr_axi_fc = 1;
2499 }
2500
2501 /* 3) set div and FC req bit trigger DDR/AXI FC */
2502 if (ddr_axi_fc) {
2503 debug_wt_reg(cc_ap.v, APMU_CCR);
2504 wait_for_fc_done();
2505 }
2506
2507 /* 4) Post FC : AP clear allow FC voting */
2508 cc_ap.v = __raw_readl(APMU_CCR);
2509 cc_ap.b.core_allow_spd_chg = 0;
2510 __raw_writel(cc_ap.v, APMU_CCR);
2511}
2512
2513static int set_ddr_freq(struct pxa988_ddr_axi_opt *old,
2514 struct pxa988_ddr_axi_opt *new)
2515{
2516 struct pxa988_ddr_axi_opt cop;
2517 int ret = 0, errflag = 0;
2518
2519 printf("DDR FC start: DDR %u -> %u\n", old->dclk, new->dclk);
2520 get_fc_lock();
2521
2522 memcpy(&cop, old, sizeof(struct pxa988_ddr_axi_opt));
2523
2524 clk_enable(new->ddr_clk_sel);
2525 ddr_fc_seq(&cop, new);
2526
2527 memcpy(&cop, new, sizeof(struct pxa988_ddr_axi_opt));
2528 get_cur_ddr_axi_op(&cop);
2529 if (unlikely((cop.ddr_clk_src != new->ddr_clk_src) ||
2530 (cop.dclk != new->dclk))) {
2531 clk_disable(new->ddr_clk_sel);
2532 errflag = 1;
2533 }
2534 if (unlikely(errflag)) {
2535 printf("DDR:unsuccessful frequency change!\n");
2536 printf(" dsrc dclk\n");
2537 printf("CUR %d %d\n", cop.ddr_clk_src, cop.dclk);
2538 printf("NEW %d %d\n", new->ddr_clk_src, new->dclk);
2539 ret = -EAGAIN;
2540 goto out;
2541 }
2542
2543 clk_disable(old->ddr_clk_sel);
2544out:
2545 put_fc_lock();
2546 printf("DDR FC end: DDR %u -> %u\n", old->dclk, new->dclk);
2547 return ret;
2548}
2549
2550static int set_axi_freq(struct pxa988_ddr_axi_opt *old,
2551 struct pxa988_ddr_axi_opt *new)
2552{
2553 struct pxa988_ddr_axi_opt cop;
2554 int ret = 0, errflag = 0;
2555
2556 printf("AXI FC start: AXI %u -> %u\n", old->aclk, new->aclk);
2557 get_fc_lock();
2558
2559 memcpy(&cop, old, sizeof(struct pxa988_ddr_axi_opt));
2560 clk_enable(new->axi_clk_sel);
2561 axi_fc_seq(&cop, new);
2562
2563 memcpy(&cop, new, sizeof(struct pxa988_ddr_axi_opt));
2564 get_cur_ddr_axi_op(&cop);
2565 if (unlikely((cop.axi_clk_src != new->axi_clk_src) ||
2566 (cop.aclk != new->aclk))) {
2567 clk_disable(new->axi_clk_sel);
2568 errflag = 1;
2569 }
2570 if (unlikely(errflag)) {
2571 printf("AXI:unsuccessful frequency change!\n");
2572 printf("asrc aclk\n");
2573 printf("CUR %d %d\n", cop.axi_clk_src, cop.aclk);
2574 printf("NEW %d %d\n", new->axi_clk_src, new->aclk);
2575 ret = -EAGAIN;
2576 goto out;
2577 }
2578
2579 clk_disable(old->axi_clk_sel);
2580out:
2581 put_fc_lock();
2582 printf("AXI FC end: AXI %u -> %u\n", old->aclk, new->aclk);
2583 return ret;
2584}
2585
2586static int pxa988_ddr_setrate(unsigned long rate)
2587{
2588 struct pxa988_ddr_axi_opt *md_new, *md_old;
2589 unsigned int index;
2590 int ret = 0;
2591 struct pxa988_ddr_axi_opt *op_array =
2592 cur_platform_opt->ddr_axi_opt;
2593
2594 if (unlikely(!cur_ddr_op))
2595 cur_ddr_op = &pxa988_ddraxi_bootop;
2596 index = ddr_rate2_op_index(rate);
2597 md_new = &op_array[index];
2598 md_old = cur_ddr_op;
2599
2600 ret = set_ddr_freq(md_old, md_new);
2601 if (ret)
2602 goto out;
2603 cur_ddr_op = md_new;
2604out:
2605 return ret;
2606}
2607
2608static int pxa988_axi_setrate(unsigned long rate)
2609{
2610 struct pxa988_ddr_axi_opt *md_new, *md_old;
2611 unsigned int index;
2612 int ret = 0;
2613 struct pxa988_ddr_axi_opt *op_array =
2614 cur_platform_opt->ddr_axi_opt;
2615
2616 if (unlikely(!cur_axi_op))
2617 cur_axi_op = &pxa988_ddraxi_bootop;
2618 index = axi_rate2_op_index(rate);
2619 md_new = &op_array[index];
2620 md_old = cur_axi_op;
2621
2622 ret = set_axi_freq(md_old, md_new);
2623 if (ret)
2624 goto out;
2625 cur_axi_op = md_new;
2626out:
2627 return ret;
2628}
2629
2630/* frequency unit Mhz*/
2631int getopindex(unsigned int corefreq, unsigned int ddrfreq)
2632{
2633 struct operating_point *op_array =
2634 cur_platform_opt->op_array;
2635 unsigned int op_size = cur_platform_opt->com_op_size, i;
2636
2637 for (i = 0; i < op_size; i++)
2638 if ((op_array[i].pclk == corefreq) &&
2639 (op_array[i].dclk == ddrfreq))
2640 return i;
2641 return op_size - 1;
2642}
2643
2644unsigned int get_max_cpurate(void)
2645{
2646 if (cur_platform_opt)
2647 return cur_platform_opt->df_max_cpurate;
2648 return 0;
2649}
2650
2651/*
2652 * This function is called from board level or cmd to
2653 * issue the core, ddr&axi frequency change.
2654 */
2655int setop(int opnum)
2656{
2657 int cur_volt;
2658 int ret = 0;
2659 struct operating_point *op_array =
2660 cur_platform_opt->op_array;
2661 unsigned int op_size = cur_platform_opt->com_op_size;
2662
2663 if (opnum >= op_size) {
2664 printf("opnum out of range!\n");
2665 return -EAGAIN;
2666 }
2667 cur_volt = get_volt();
2668 if (cur_volt <= 0) {
2669 printf("Fail to get voltage!\n");
2670 return -1;
2671 }
2672 if (op_array[opnum].vcore > cur_volt)
2673 ret = set_volt(op_array[opnum].vcore);
2674 if (ret) {
2675 printf("Increase volatge %dmV failed!\n",
2676 op_array[opnum].vcore);
2677 return -1;
2678 }
2679
2680 /* set core frequency */
2681 pxa988_cpu_setrate(op_array[opnum].pclk);
2682
2683 /* set ddr and axi frequency */
2684 pxa988_ddr_setrate(op_array[opnum].dclk);
2685 pxa988_axi_setrate(op_array[opnum].aclk);
2686
2687 if (op_array[opnum].vcore < cur_volt)
2688 ret = set_volt(op_array[opnum].vcore);
2689 if (ret) {
2690 printf("Decrease volatge %dmV failed!\n",
2691 op_array[opnum].vcore);
2692 return -1;
2693 }
2694 return 0;
2695}
2696
2697void __init_op_array(int profile)
2698{
2699 unsigned int i = 0, j = 0;
2700 int max_require;
2701 int *vm_millivolts_tmp;
2702 unsigned int (*freqs_cmb)[VL_MAX];
2703 struct operating_point *op_array =
2704 cur_platform_opt->op_array;
2705 unsigned int op_size = cur_platform_opt->com_op_size;
2706
2707 if (cpu_is_pxa1088_a0()) {
2708 vm_millivolts_tmp = vm_mv_1088a0_svc_1p2G[profile];
2709 freqs_cmb = freqs_cmb_1088a0;
2710 } else if (cpu_is_pxa1088_a1()) {
2711 if (cur_platform_opt->df_max_cpurate > CORE_1P18G)
2712 vm_millivolts_tmp = vm_mv_1088a1_svc_1p25G[profile];
2713 else
2714 vm_millivolts_tmp = vm_mv_1088a1_svc_1p2G[profile];
2715 freqs_cmb = freqs_cmb_1088a1;
2716 } else if (cpu_is_pxa1L88_a0()) {
2717 if (cur_platform_opt->df_max_cpurate > CORE_1P18G)
2718 vm_millivolts_tmp = vm_mv_1L88a0_svc_1p25G[profile];
2719 else
2720 vm_millivolts_tmp = vm_mv_1L88a0_svc[profile];
2721 freqs_cmb = freqs_cmb_1L88;
2722 } else if (cpu_is_pxa1L88_a0c()) {
2723 if (cur_platform_opt->df_max_cpurate > CORE_1P25G)
2724 if (get_foundry() == 2)
2725 vm_millivolts_tmp =
2726 vm_mv_1L88a0c_umc_svc_1p5G[profile];
2727 else
2728 vm_millivolts_tmp =
2729 vm_mv_1L88a0c_svc_1p5G[profile];
2730 else if (cur_platform_opt->df_max_cpurate > CORE_1P18G)
2731 if (get_foundry() == 2)
2732 vm_millivolts_tmp =
2733 vm_mv_1L88a0c_umc_svc_1p25G[profile];
2734 else
2735 vm_millivolts_tmp =
2736 vm_mv_1L88a0c_svc_1p25G[profile];
2737 else
2738 if (get_foundry() == 2)
2739 vm_millivolts_tmp =
2740 vm_mv_1L88a0c_umc_svc_1p2G[profile];
2741 else
2742 vm_millivolts_tmp =
2743 vm_mv_1L88a0c_svc_1p2G[profile];
2744 freqs_cmb = freqs_cmb_1L88;
2745 } else {
2746 vm_millivolts_tmp = vm_mv_1088a0_svc_1p2G[profile];
2747 freqs_cmb = freqs_cmb_1088a0;
2748 }
2749
2750 for (i = 0; i < op_size; i++) {
2751 for (j = 0; j < VL_MAX; j++) {
2752 if (op_array[i].pclk <= freqs_cmb[CORE][j])
2753 break;
2754 }
2755 max_require = vm_millivolts_tmp[j];
2756
2757 for (j = 0; j < VL_MAX; j++) {
2758 if (op_array[i].dclk <= freqs_cmb[DDR_AXI][j])
2759 break;
2760 }
2761 op_array[i].vcore = max(max_require, vm_millivolts_tmp[j]);
2762 }
2763}
2764
2765/*
2766 * This function is called from board/CPU init level to initialize
2767 * the OP table and frequency change related setting
2768 */
2769void pxa988_fc_init(int ddr_mode)
2770{
2771 unsigned int dcg_regval = 0, mc_hw_slp;
2772 int iprofile = get_profile();
2773
2774 __init_platform_opt(ddr_mode);
2775 __init_cpu_opt();
2776 __init_ddr_axi_opt();
2777 __init_fc_setting();
2778
2779 /* enable MCK4 and AXI fabric dynamic clk gating */
2780 dcg_regval = __raw_readl(MC_CONF);
2781 /* disable cp fabric clk gating */
2782 dcg_regval &= ~(1 << 16);
2783 /* enable dclk gating */
2784 dcg_regval &= ~(1 << 19);
2785 if (!has_feat_mck4_axi_clock_gate()) {
2786 dcg_regval |= (1 << 9) | (1 << 18) | /* Seagull */
2787 (1 << 12) | (1 << 27) | /* Fabric #2 */
2788 (1 << 15) | (1 << 20) | (1 << 21) | /* VPU*/
2789 (1 << 17) | (1 << 26); /* Fabric#1 CA9 */
2790 } else {
2791 dcg_regval |= (0xff << 8) | /* MCK4 P0~P7*/
2792 (1 << 17) | (1 << 18) | /* Fabric 0 */
2793 (1 << 20) | (1 << 21) | /* VPU fabric */
2794 (1 << 26) | (1 << 27); /* Fabric 0/1 */
2795 }
2796 __raw_writel(dcg_regval, MC_CONF);
2797 /* enable MCK4 AHB clock */
2798 __raw_writel(0x3, APMU_MCK4_CTRL);
2799
2800 /* Disable dvc dll auto update */
2801 if (has_feat_dvc_auto_dll_update()) {
2802 mc_hw_slp = __raw_readl(APMU_MC_HW_SLP_TYPE);
2803 mc_hw_slp |= (1 << 9);
2804 __raw_writel(mc_hw_slp, APMU_MC_HW_SLP_TYPE);
2805 }
2806 /*
2807 * Some Z2 chips need higher voltage to make system stable.
2808 * And based on current result, 986 Z2 need higher voltage
2809 * than 988 Z2 chip. So, update volt into op_array accordingly.
2810 */
2811 __init_op_array(iprofile);
2812 cur_cpu_op = &pxa988_cpu_bootop;
2813 cur_ddr_op = &pxa988_ddraxi_bootop;
2814 cur_axi_op = &pxa988_ddraxi_bootop;
2815}
2816
2817void show_op(void)
2818{
2819 struct pxa988_cpu_opt cop;
2820 struct pxa988_ddr_axi_opt daop;
2821 unsigned int i;
2822 struct operating_point *op_array =
2823 cur_platform_opt->op_array;
2824 unsigned int op_size = cur_platform_opt->com_op_size;
2825
2826 printf("Current OP:\n");
2827 memcpy(&cop, cur_cpu_op, sizeof(struct pxa988_cpu_opt));
2828 printf("pclk(src:sel) l2clk(src)\tpdclk(src)\tbaclk(src)\tperiphclk(src)\n");
2829 printf("%d(%d:%d)\t%d([%s])\t%d([%s])\t%d([%s])\t%d([%s])\n",
2830 cop.pclk, cop.ap_clk_src,
2831 cop.ap_clk_sel & AP_SRC_SEL_MASK,
2832 cop.l2clk, cop.l2clk ? "pclk" : "NULL",
2833 cop.pdclk, cop.l2clk ? "l2clk" : "pclk",
2834 cop.baclk, cop.l2clk ? "l2clk" : "pclk",
2835 cop.periphclk, cop.periphclk ? "pclk" : "NULL");
2836 memcpy(&daop, cur_ddr_op, sizeof(struct pxa988_ddr_axi_opt));
2837 printf("dclk(src:sel)\n");
2838 printf("%d(%d:%d)\n", daop.dclk, daop.ddr_clk_src, daop.ddr_clk_sel);
2839
2840 memcpy(&daop, cur_axi_op, sizeof(struct pxa988_ddr_axi_opt));
2841 printf("aclk(src:sel)\n");
2842 printf("%d(%d:%d)\n", daop.aclk, daop.axi_clk_src, daop.axi_clk_sel);
2843
2844 printf("\nAll supported OP:\n");
2845 printf("OP\t Core(MHZ)\t DDR(MHZ)\t AXI(MHZ)\t Vcore\n");
2846 for (i = 0; i < op_size; i++) {
2847 if (cur_platform_opt->df_max_cpurate &&
2848 (op_array[i].pclk > cur_platform_opt->df_max_cpurate))
2849 continue;
2850 printf("%d\t %d\t %d\t %d\t %d\t\n", i,
2851 op_array[i].pclk, op_array[i].dclk,
2852 op_array[i].aclk, op_array[i].vcore);
2853 }
2854}
2855
2856int do_op(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
2857{
2858 ulong num;
2859
2860 if (argc == 2) {
2861 num = simple_strtoul(argv[1], NULL, 0);
2862 if (setop(num) < 0)
2863 return -1;
2864 }
2865 if (argc <= 2)
2866 show_op();
2867 return 0;
2868}
2869
2870U_BOOT_CMD(
2871 op, 2, 1, do_op,
2872 "change operating point",
2873 "[ op number ]"
2874);
2875
2876#define PM812_SLAVE_ADDR 0x31
2877#define PM812_VBUCK1_SET0_REG 0x3c /* dvc[1:0] = 0x0 */
2878
2879#define VOL_BASE 600000
2880#define VOL_STEP 12500
2881#define VOL_HIGH 1400000
2882
2883#define PM812_DVC1 43
2884#define PM812_DVC2 44
2885
2886static int set_volt(u32 vol)
2887{
2888 int ret = 0;
2889 struct pmic *p_power;
2890
2891 vol *= 1000;
2892 if ((vol < VOL_BASE) || (vol > VOL_HIGH)) {
2893 printf("out of range when set voltage!\n");
2894 return -1;
2895 }
2896
2897 p_power = pmic_get(MARVELL_PMIC_POWER);
2898 if (!p_power)
2899 return -1;
2900 if (pmic_probe(p_power))
2901 return -1;
2902 ret = marvell88pm_set_buck_vol(p_power, 1, vol);
2903 printf("Set VBUCK1 to %4dmV\n", vol / 1000);
2904
2905 /* always use DVC[1:0] = 0 in uboot */
2906 /* TODO : make sure DVC pins' function is GPIO */
2907 gpio_direction_output(PM812_DVC1, 0);
2908 gpio_direction_output(PM812_DVC2, 0);
2909 return ret;
2910}
2911
2912static int get_volt(void)
2913{
2914 u32 vol = 0;
2915 struct pmic *p_power;
2916
2917 p_power = pmic_get(MARVELL_PMIC_POWER);
2918 if (!p_power)
2919 return -1;
2920 if (pmic_probe(p_power))
2921 return -1;
2922
2923 vol = marvell88pm_get_buck_vol(p_power, 1);
2924 if (vol < 0)
2925 return -1;
2926
2927 return vol / 1000;
2928}
2929
2930int do_setvolt(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
2931{
2932 ulong vol;
2933 int res = -1;
2934 if ((argc < 1) || (argc > 2))
2935 return -1;
2936
2937 if (argc == 1) {
2938 printf("usage: setvolt xxxx(unit mV)\n"
2939 "for Emei 988, xxxx can be 600..1350, step 13 or 25\n"
2940 );
2941 return 0;
2942 }
2943 res = strict_strtoul(argv[1], 0, &vol);
2944 if (res == 0 && set_volt(vol) == 0)
2945 printf("Voltage change was successful\n");
2946 else
2947 printf("Voltage change was unsuccessful\n");
2948
2949 return 0;
2950}
2951
2952U_BOOT_CMD(
2953 setvolt, 6, 1, do_setvolt,
2954 "Setting voltages",
2955 ""
2956);
2957
2958int do_pllops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
2959{
2960 ulong pllx, enable, vco = 0, pll = 0, pllp = 0;
2961 int res = -1;
2962
2963 if (argc != 6) {
2964 printf("usage:\n");
2965 printf("pll 2/3 1 pll2/3vcofreq pll2/3freq pll2p/3pfreq enable pll2/3 and set to XXX MHZ\n");
2966 printf("pll 2/3 1 0 0 0 enable pll2/3 at default frequency\n");
2967 printf("pll 2/3 0 0 0 0 disable pll2/3\n");
2968 return -1;
2969 }
2970
2971 res = strict_strtoul(argv[1], 0, &pllx);
2972 if (res < 0) {
2973 printf("Failed to get pll num\n");
2974 return -res;
2975 }
2976
2977 res = strict_strtoul(argv[2], 0, &enable);
2978 if (res < 0) {
2979 printf("Failed to get enable/disable flag\n");
2980 return -res;
2981 }
2982
2983 res = strict_strtoul(argv[3], 0, &vco);
2984 if (res < 0) {
2985 printf("Failed to get enable/disable flag\n");
2986 return -res;
2987 }
2988
2989 res = strict_strtoul(argv[4], 0, &pll);
2990 if (res < 0) {
2991 printf("Failed to get enable/disable flag\n");
2992 return -res;
2993 }
2994
2995 res = strict_strtoul(argv[5], 0, &pllp);
2996 if (res < 0) {
2997 printf("Failed to get enable/disable flag\n");
2998 return -res;
2999 }
3000
3001 if (enable) {
3002 if (vco && (pllx == 2))
3003 set_pll2_freq(vco, pll, pllp);
3004 else if (!vco && (pllx == 2))
3005 turn_on_pll2();
3006 else if (vco && (pllx == 3))
3007 set_pll3_freq(vco, pll, pllp);
3008 else if (!vco && (pllx == 3))
3009 turn_on_pll3();
3010 } else {
3011 if (pllx == 2)
3012 turn_off_pll2();
3013 else if (pllx == 3)
3014 turn_off_pll3();
3015 }
3016 return 0;
3017}
3018
3019U_BOOT_CMD(
3020 pllops, 6, 1, do_pllops,
3021 "Set PLL2/3 output",
3022 ""
3023);
3024
3025int do_setcpurate(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
3026{
3027 struct pxa988_cpu_opt *cpu_opt;
3028 unsigned int cpu_opt_size = 0, i;
3029 ulong freq;
3030 int res = -1;
3031
3032 cpu_opt = cur_platform_opt->cpu_opt;
3033 cpu_opt_size = cur_platform_opt->cpu_opt_size;
3034
3035 if (argc != 2) {
3036 printf("usage: set core frequency xxxx(unit Mhz)\n");
3037 printf("Supported Core frequency: ");
3038 for (i = 0; i < cpu_opt_size; i++)
3039 printf("%d\t", cpu_opt[i].pclk);
3040 printf("\n");
3041 return -1;
3042 }
3043 res = strict_strtoul(argv[1], 0, &freq);
3044 if ((res == 0) && (pxa988_cpu_setrate(freq) == 0))
3045 printf("Core freq change was successful\n");
3046 else
3047 printf("Core freq change was unsuccessful\n");
3048 return 0;
3049}
3050
3051U_BOOT_CMD(
3052 setcpurate, 6, 1, do_setcpurate,
3053 "Setting core rate",
3054 ""
3055);
3056
3057int do_setddrrate(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
3058{
3059 struct pxa988_ddr_axi_opt *ddr_axi_opt;
3060 unsigned int ddr_axi_opt_size = 0, i;
3061 ulong freq;
3062 int res = -1;
3063
3064 ddr_axi_opt = cur_platform_opt->ddr_axi_opt;
3065 ddr_axi_opt_size = cur_platform_opt->ddr_axi_opt_size;
3066
3067 if (argc != 2) {
3068 printf("usage: set ddr/axi frequency xxxx(unit Mhz)\n");
3069 printf("Supported ddr/axi frequency: ");
3070 for (i = 0; i < ddr_axi_opt_size; i++)
3071 printf("%d/%d\t",
3072 ddr_axi_opt[i].dclk, ddr_axi_opt[i].aclk);
3073 printf("\n");
3074 return -1;
3075 }
3076
3077 res = strict_strtoul(argv[1], 0, &freq);
3078 if ((res == 0) && (pxa988_ddr_setrate(freq) == 0))
3079 printf("DDR freq change was successful\n");
3080 else
3081 printf("DDR freq change was unsuccessful\n");
3082
3083 return 0;
3084}
3085
3086U_BOOT_CMD(
3087 setddrrate, 6, 1, do_setddrrate,
3088 "Setting ddr rate",
3089 ""
3090);
3091
3092int do_setaxirate(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
3093{
3094 struct pxa988_ddr_axi_opt *ddr_axi_opt;
3095 unsigned int ddr_axi_opt_size = 0, i;
3096 ulong freq;
3097 int res = -1;
3098
3099 ddr_axi_opt = cur_platform_opt->ddr_axi_opt;
3100 ddr_axi_opt_size = cur_platform_opt->ddr_axi_opt_size;
3101
3102 if (argc != 2) {
3103 printf("usage: set axi frequency xxxx(unit Mhz)\n");
3104 printf("Supported axi frequency: ");
3105 for (i = 0; i < ddr_axi_opt_size; i++)
3106 printf("%d\t", ddr_axi_opt[i].aclk);
3107 printf("\n");
3108 return -1;
3109 }
3110
3111 res = strict_strtoul(argv[1], 0, &freq);
3112 if ((res == 0) && (pxa988_axi_setrate(freq) == 0))
3113 printf("AXI freq change was successful\n");
3114 else
3115 printf("AXI freq change was unsuccessful\n");
3116
3117 return 0;
3118}
3119
3120U_BOOT_CMD(
3121 setaxirate, 6, 1, do_setaxirate,
3122 "Setting axi rate",
3123 ""
3124);