blob: 8ce4d69d8f1e13e4adf7c9a011bd7c420e0f1f17 [file] [log] [blame]
b.liue9582032025-04-17 19:18:16 +08001From 1b88c6ed26a1aa1d68d1661404e6e939709ff530 Mon Sep 17 00:00:00 2001
2From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
3Date: Thu, 10 Dec 2020 08:21:54 +0100
4Subject: [PATCH 4/4] arm64: dts: broadcom: bcm4908: describe PCIe reset
5 controller
6MIME-Version: 1.0
7Content-Type: text/plain; charset=UTF-8
8Content-Transfer-Encoding: 8bit
9
10This reset controller is a single register in the Broadcom's MISC block.
11
12Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
13Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
14---
15 arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi | 15 +++++++++++++++
16 1 file changed, 15 insertions(+)
17
18--- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi
19+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi
20@@ -177,6 +177,21 @@
21 };
22 };
23
24+ misc@2600 {
25+ compatible = "brcm,misc", "simple-mfd";
26+ reg = <0x2600 0xe4>;
27+
28+ #address-cells = <1>;
29+ #size-cells = <1>;
30+ ranges = <0x00 0x2600 0xe4>;
31+
32+ reset-controller@2644 {
33+ compatible = "brcm,bcm4908-misc-pcie-reset";
34+ reg = <0x44 0x04>;
35+ #reset-cells = <1>;
36+ };
37+ };
38+
39 reboot {
40 compatible = "syscon-reboot";
41 regmap = <&timer>;