blob: b61437a2de226de07215e636a96bbf6eacd2fba6 [file] [log] [blame]
b.liue9582032025-04-17 19:18:16 +08001From ab4dda7a8cb7e55ea3d92fd5e249cf6f5396028c Mon Sep 17 00:00:00 2001
2From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
3Date: Thu, 11 Mar 2021 13:35:20 +0100
4Subject: [PATCH] dt-bindings: net: bcm4908-enet: add optional TX interrupt
5MIME-Version: 1.0
6Content-Type: text/plain; charset=UTF-8
7Content-Transfer-Encoding: 8bit
8
9I discovered that hardware actually supports two interrupts, one per DMA
10channel (RX and TX).
11
12Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
13Signed-off-by: David S. Miller <davem@davemloft.net>
14---
15 .../bindings/net/brcm,bcm4908-enet.yaml | 17 +++++++++++++----
16 1 file changed, 13 insertions(+), 4 deletions(-)
17
18--- a/Documentation/devicetree/bindings/net/brcm,bcm4908-enet.yaml
19+++ b/Documentation/devicetree/bindings/net/brcm,bcm4908-enet.yaml
20@@ -22,10 +22,18 @@ properties:
21 maxItems: 1
22
23 interrupts:
24- description: RX interrupt
25+ minItems: 1
26+ maxItems: 2
27+ items:
28+ - description: RX interrupt
29+ - description: TX interrupt
30
31 interrupt-names:
32- const: rx
33+ minItems: 1
34+ maxItems: 2
35+ items:
36+ - const: rx
37+ - const: tx
38
39 required:
40 - reg
41@@ -43,6 +51,7 @@ examples:
42 compatible = "brcm,bcm4908-enet";
43 reg = <0x80002000 0x1000>;
44
45- interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
46- interrupt-names = "rx";
47+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
48+ <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
49+ interrupt-names = "rx", "tx";
50 };