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192.168.1.100 / T108 / c2023d5d03be91dbb983606f0ec5e9e4ea36c8c2 / . / target / linux / bcm63xx / patches-5.4 / 431-MIPS-BCM63XX-add-nand-rset.patch
blob: 090ffeb43cefeedc9eee28dbb0a0bf23c4708f00 [file] [log] [blame]
b.liue9582032025-04-17 19:18:16 +0800[diff] [blame]1--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
2+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
3@@ -184,7 +184,8 @@ enum bcm63xx_regs_set {
4 RSET_PCMDMAC,
5 RSET_PCMDMAS,
6 RSET_RNG,
7- RSET_MISC
8+ RSET_MISC,
9+ RSET_NAND
10 };
11
12 #define RSET_DSL_LMEM_SIZE (64 * 1024 * 4)
13@@ -262,6 +263,7 @@ enum bcm63xx_regs_set {
14 #define BCM_3368_PCMDMAS_BASE (0xdeadbeef)
15 #define BCM_3368_RNG_BASE (0xdeadbeef)
16 #define BCM_3368_MISC_BASE (0xdeadbeef)
17+#define BCM_3368_NAND_BASE (0xdeadbeef)
18
19 /*
20 * 6318 register sets base address
21@@ -309,6 +311,7 @@ enum bcm63xx_regs_set {
22 #define BCM_6318_PCMDMAS_BASE (0xdeadbeef)
23 #define BCM_6318_RNG_BASE (0xdeadbeef)
24 #define BCM_6318_MISC_BASE (0xb0000280)
25+#define BCM_6318_NAND_BASE (0xdeadbeef)
26 #define BCM_6318_OTP_BASE (0xdeadbeef)
27
28 #define BCM_6318_STRAP_BASE (0xb0000900)
29@@ -359,6 +362,7 @@ enum bcm63xx_regs_set {
30 #define BCM_6328_PCMDMAS_BASE (0xdeadbeef)
31 #define BCM_6328_RNG_BASE (0xdeadbeef)
32 #define BCM_6328_MISC_BASE (0xb0001800)
33+#define BCM_6328_NAND_BASE (0xb0000200)
34 #define BCM_6328_OTP_BASE (0xb0000600)
35
36 /*
37@@ -408,6 +412,7 @@ enum bcm63xx_regs_set {
38 #define BCM_6338_PCMDMAS_BASE (0xdeadbeef)
39 #define BCM_6338_RNG_BASE (0xdeadbeef)
40 #define BCM_6338_MISC_BASE (0xdeadbeef)
41+#define BCM_6338_NAND_BASE (0xdeadbeef)
42
43 /*
44 * 6345 register sets base address
45@@ -456,6 +461,7 @@ enum bcm63xx_regs_set {
46 #define BCM_6345_PCMDMAS_BASE (0xdeadbeef)
47 #define BCM_6345_RNG_BASE (0xdeadbeef)
48 #define BCM_6345_MISC_BASE (0xdeadbeef)
49+#define BCM_6345_NAND_BASE (0xdeadbeef)
50
51 /*
52 * 6348 register sets base address
53@@ -502,6 +508,7 @@ enum bcm63xx_regs_set {
54 #define BCM_6348_PCMDMAS_BASE (0xdeadbeef)
55 #define BCM_6348_RNG_BASE (0xdeadbeef)
56 #define BCM_6348_MISC_BASE (0xdeadbeef)
57+#define BCM_6348_NAND_BASE (0xdeadbeef)
58
59 /*
60 * 6358 register sets base address
61@@ -548,7 +555,7 @@ enum bcm63xx_regs_set {
62 #define BCM_6358_PCMDMAS_BASE (0xfffe1a00)
63 #define BCM_6358_RNG_BASE (0xdeadbeef)
64 #define BCM_6358_MISC_BASE (0xdeadbeef)
65-
66+#define BCM_6358_NAND_BASE (0xdeadbeef)
67
68 /*
69 * 6362 register sets base address
70@@ -596,6 +603,7 @@ enum bcm63xx_regs_set {
71 #define BCM_6362_PCMDMAS_BASE (0xdeadbeef)
72 #define BCM_6362_RNG_BASE (0xdeadbeef)
73 #define BCM_6362_MISC_BASE (0xb0001800)
74+#define BCM_6362_NAND_BASE (0xb0000200)
75
76 #define BCM_6362_NAND_REG_BASE (0xb0000200)
77 #define BCM_6362_NAND_CACHE_BASE (0xb0000600)
78@@ -651,6 +659,7 @@ enum bcm63xx_regs_set {
79 #define BCM_6368_PCMDMAS_BASE (0xb0005c00)
80 #define BCM_6368_RNG_BASE (0xb0004180)
81 #define BCM_6368_MISC_BASE (0xdeadbeef)
82+#define BCM_6368_NAND_BASE (0xb0000200)
83
84 /*
85 * 63268 register sets base address
86@@ -698,6 +707,7 @@ enum bcm63xx_regs_set {
87 #define BCM_63268_PCMDMAS_BASE (0xdeadbeef)
88 #define BCM_63268_RNG_BASE (0xdeadbeef)
89 #define BCM_63268_MISC_BASE (0xb0001800)
90+#define BCM_63268_NAND_BASE (0xb0000200)
91
92 extern const unsigned long *bcm63xx_regs_base;
93
94@@ -743,6 +753,7 @@ extern const unsigned long *bcm63xx_regs
95 [RSET_PCMDMAS] = BCM_## __cpu ##_PCMDMAS_BASE, \
96 [RSET_RNG] = BCM_## __cpu ##_RNG_BASE, \
97 [RSET_MISC] = BCM_## __cpu ##_MISC_BASE, \
98+ [RSET_NAND] = BCM_## __cpu ##_NAND_BASE, \
99
100
101 static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
102--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
103+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
104@@ -111,5 +111,7 @@
105 #define bcm_ddr_writel(v, o) bcm_rset_writel(RSET_DDR, (v), (o))
106 #define bcm_misc_readl(o) bcm_rset_readl(RSET_MISC, (o))
107 #define bcm_misc_writel(v, o) bcm_rset_writel(RSET_MISC, (v), (o))
108+#define bcm_nand_readl(o) bcm_rset_readl(RSET_NAND, (o))
109+#define bcm_nand_writel(v, o) bcm_rset_writel(RSET_NAND, (v), (o))
110
111 #endif /* ! BCM63XX_IO_H_ */
112--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
113+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
114@@ -1688,4 +1688,31 @@
115 #define OTP_USER_BITS_6328_REG(i) (0x20 + (i) * 4)
116 #define OTP_6328_REG3_TP1_DISABLED BIT(9)
117
118+/*************************************************************************
119+ * _REG relative to RSET_NAND
120+ *************************************************************************/
121+
122+#define NAND_CS_SEL_REG 0x14
123+#define NAND_CS_SEL_EBC_CS0_SEL (1 << 0)
124+#define NAND_CS_SEL_EBC_CS1_SEL (1 << 1)
125+#define NAND_CS_SEL_EBC_CS2_SEL (1 << 2)
126+#define NAND_CS_SEL_EBC_CS3_SEL (1 << 3)
127+#define NAND_CS_SEL_EBC_CS4_SEL (1 << 4)
128+#define NAND_CS_SEL_EBC_CS5_SEL (1 << 5)
129+#define NAND_CS_SEL_EBC_CS6_SEL (1 << 6)
130+#define NAND_CS_SEL_EBC_CS7_SEL (1 << 7)
131+#define NAND_CS_SEL_EBI_CS0_USES_NAND (1 << 8)
132+#define NAND_CS_SEL_EBI_CS1_USES_NAND (1 << 9)
133+#define NAND_CS_SEL_EBI_CS2_USES_NAND (1 << 10)
134+#define NAND_CS_SEL_EBI_CS3_USES_NAND (1 << 11)
135+#define NAND_CS_SEL_EBI_CS4_USES_NAND (1 << 12)
136+#define NAND_CS_SEL_EBI_CS5_USES_NAND (1 << 13)
137+#define NAND_CS_SEL_EBI_CS6_USES_NAND (1 << 14)
138+#define NAND_CS_SEL_EBI_CS7_USES_NAND (1 << 15)
139+#define NAND_CS_SEL_WR_PROT_BLK0 (1 << 28)
140+#define NAND_CS_SEL_AUTO_DEV_ID (1 << 30)
141+#define NAND_CS_SEL_CS_LOCK (1 << 31)
142+
143+#define NAND_CS_XOR_REG 0x18
144+
145 #endif /* BCM63XX_REGS_H_ */