| b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 1 | From 5b08c1d567ee8e6af94696b3e549997cbdb2bb80 Mon Sep 17 00:00:00 2001 |
| 2 | From: Jaiganesh Narayanan <njaigane@codeaurora.org> |
| 3 | Date: Thu, 1 Sep 2016 10:40:38 +0530 |
| 4 | Subject: [PATCH] pinctrl: qcom: ipq4019: add open drain support |
| 5 | |
| 6 | Signed-off-by: Jaiganesh Narayanan <njaigane@codeaurora.org> |
| 7 | [ Brian: adapted from from the Chromium OS kernel used on IPQ4019-based |
| 8 | WiFi APs. ] |
| 9 | Signed-off-by: Brian Norris <computersforpeace@gmail.com> |
| 10 | --- |
| 11 | https://lore.kernel.org/linux-gpio/20200703080646.23233-1-computersforpeace@gmail.com/ |
| 12 | |
| 13 | drivers/pinctrl/qcom/pinctrl-ipq4019.c | 1 + |
| 14 | drivers/pinctrl/qcom/pinctrl-msm.c | 13 +++++++++++++ |
| 15 | drivers/pinctrl/qcom/pinctrl-msm.h | 2 ++ |
| 16 | 3 files changed, 16 insertions(+) |
| 17 | |
| 18 | --- a/drivers/pinctrl/qcom/pinctrl-ipq4019.c |
| 19 | +++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c |
| 20 | @@ -254,6 +254,7 @@ DECLARE_QCA_GPIO_PINS(99); |
| 21 | .mux_bit = 2, \ |
| 22 | .pull_bit = 0, \ |
| 23 | .drv_bit = 6, \ |
| 24 | + .od_bit = 12, \ |
| 25 | .oe_bit = 9, \ |
| 26 | .in_bit = 0, \ |
| 27 | .out_bit = 1, \ |
| 28 | --- a/drivers/pinctrl/qcom/pinctrl-msm.c |
| 29 | +++ b/drivers/pinctrl/qcom/pinctrl-msm.c |
| 30 | @@ -225,6 +225,10 @@ static int msm_config_reg(struct msm_pin |
| 31 | *bit = g->pull_bit; |
| 32 | *mask = 3; |
| 33 | break; |
| 34 | + case PIN_CONFIG_DRIVE_OPEN_DRAIN: |
| 35 | + *bit = g->od_bit; |
| 36 | + *mask = 1; |
| 37 | + break; |
| 38 | case PIN_CONFIG_DRIVE_STRENGTH: |
| 39 | *bit = g->drv_bit; |
| 40 | *mask = 7; |
| 41 | @@ -302,6 +306,12 @@ static int msm_config_group_get(struct p |
| 42 | if (!arg) |
| 43 | return -EINVAL; |
| 44 | break; |
| 45 | + case PIN_CONFIG_DRIVE_OPEN_DRAIN: |
| 46 | + /* Pin is not open-drain */ |
| 47 | + if (!arg) |
| 48 | + return -EINVAL; |
| 49 | + arg = 1; |
| 50 | + break; |
| 51 | case PIN_CONFIG_DRIVE_STRENGTH: |
| 52 | arg = msm_regval_to_drive(arg); |
| 53 | break; |
| 54 | @@ -374,6 +384,9 @@ static int msm_config_group_set(struct p |
| 55 | else |
| 56 | arg = MSM_PULL_UP; |
| 57 | break; |
| 58 | + case PIN_CONFIG_DRIVE_OPEN_DRAIN: |
| 59 | + arg = 1; |
| 60 | + break; |
| 61 | case PIN_CONFIG_DRIVE_STRENGTH: |
| 62 | /* Check for invalid values */ |
| 63 | if (arg > 16 || arg < 2 || (arg % 2) != 0) |
| 64 | --- a/drivers/pinctrl/qcom/pinctrl-msm.h |
| 65 | +++ b/drivers/pinctrl/qcom/pinctrl-msm.h |
| 66 | @@ -38,6 +38,7 @@ struct msm_function { |
| 67 | * @mux_bit: Offset in @ctl_reg for the pinmux function selection. |
| 68 | * @pull_bit: Offset in @ctl_reg for the bias configuration. |
| 69 | * @drv_bit: Offset in @ctl_reg for the drive strength configuration. |
| 70 | + * @od_bit: Offset in @ctl_reg for controlling open drain. |
| 71 | * @oe_bit: Offset in @ctl_reg for controlling output enable. |
| 72 | * @in_bit: Offset in @io_reg for the input bit value. |
| 73 | * @out_bit: Offset in @io_reg for the output bit value. |
| 74 | @@ -75,6 +76,7 @@ struct msm_pingroup { |
| 75 | unsigned pull_bit:5; |
| 76 | unsigned drv_bit:5; |
| 77 | |
| 78 | + unsigned od_bit:5; |
| 79 | unsigned oe_bit:5; |
| 80 | unsigned in_bit:5; |
| 81 | unsigned out_bit:5; |