b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 1 | From 480c1f7648fc586db12d6003c717c23667a4fcf0 Mon Sep 17 00:00:00 2001 |
| 2 | From: Ram Chandra Jangir <rjangir@codeaurora.org> |
| 3 | Date: Tue, 28 Mar 2017 22:35:33 +0530 |
| 4 | Subject: [PATCH] clk: qcom: ipq4019: add ess reset |
| 5 | |
| 6 | Added the ESS reset in IPQ4019 GCC. |
| 7 | |
| 8 | Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org> |
| 9 | --- |
| 10 | drivers/clk/qcom/gcc-ipq4019.c | 11 +++++++++++ |
| 11 | include/dt-bindings/clock/qcom,gcc-ipq4019.h | 11 +++++++++++ |
| 12 | 2 files changed, 22 insertions(+) |
| 13 | |
| 14 | --- a/drivers/clk/qcom/gcc-ipq4019.c |
| 15 | +++ b/drivers/clk/qcom/gcc-ipq4019.c |
| 16 | @@ -1736,6 +1736,17 @@ static const struct qcom_reset_map gcc_i |
| 17 | [GCC_TCSR_BCR] = {0x22000, 0}, |
| 18 | [GCC_MPM_BCR] = {0x24000, 0}, |
| 19 | [GCC_SPDM_BCR] = {0x25000, 0}, |
| 20 | + [ESS_MAC1_ARES] = {0x1200C, 0}, |
| 21 | + [ESS_MAC2_ARES] = {0x1200C, 1}, |
| 22 | + [ESS_MAC3_ARES] = {0x1200C, 2}, |
| 23 | + [ESS_MAC4_ARES] = {0x1200C, 3}, |
| 24 | + [ESS_MAC5_ARES] = {0x1200C, 4}, |
| 25 | + [ESS_PSGMII_ARES] = {0x1200C, 5}, |
| 26 | + [ESS_MAC1_CLK_DIS] = {0x1200C, 8}, |
| 27 | + [ESS_MAC2_CLK_DIS] = {0x1200C, 9}, |
| 28 | + [ESS_MAC3_CLK_DIS] = {0x1200C, 10}, |
| 29 | + [ESS_MAC4_CLK_DIS] = {0x1200C, 11}, |
| 30 | + [ESS_MAC5_CLK_DIS] = {0x1200C, 12}, |
| 31 | }; |
| 32 | |
| 33 | static const struct regmap_config gcc_ipq4019_regmap_config = { |
| 34 | --- a/include/dt-bindings/clock/qcom,gcc-ipq4019.h |
| 35 | +++ b/include/dt-bindings/clock/qcom,gcc-ipq4019.h |
| 36 | @@ -165,5 +165,16 @@ |
| 37 | #define GCC_QDSS_BCR 69 |
| 38 | #define GCC_MPM_BCR 70 |
| 39 | #define GCC_SPDM_BCR 71 |
| 40 | +#define ESS_MAC1_ARES 72 |
| 41 | +#define ESS_MAC2_ARES 73 |
| 42 | +#define ESS_MAC3_ARES 74 |
| 43 | +#define ESS_MAC4_ARES 75 |
| 44 | +#define ESS_MAC5_ARES 76 |
| 45 | +#define ESS_PSGMII_ARES 77 |
| 46 | +#define ESS_MAC1_CLK_DIS 78 |
| 47 | +#define ESS_MAC2_CLK_DIS 79 |
| 48 | +#define ESS_MAC3_CLK_DIS 80 |
| 49 | +#define ESS_MAC4_CLK_DIS 81 |
| 50 | +#define ESS_MAC5_CLK_DIS 82 |
| 51 | |
| 52 | #endif |