| b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 1 | --- a/arch/mips/lantiq/xway/sysctrl.c |
| 2 | +++ b/arch/mips/lantiq/xway/sysctrl.c |
| 3 | @@ -436,6 +436,20 @@ static void clkdev_add_clkout(void) |
| 4 | } |
| 5 | } |
| 6 | |
| 7 | +static void set_phy_clock_source(struct device_node *np_cgu) |
| 8 | +{ |
| 9 | + u32 phy_clk_src, ifcc; |
| 10 | + |
| 11 | + if (!np_cgu) |
| 12 | + return; |
| 13 | + |
| 14 | + if (of_property_read_u32(np_cgu, "lantiq,phy-clk-src", &phy_clk_src)) |
| 15 | + return; |
| 16 | + |
| 17 | + ifcc = ltq_cgu_r32(ifccr) & ~(0x1c); |
| 18 | + ltq_cgu_w32(ifcc | (phy_clk_src << 2), ifccr); |
| 19 | +} |
| 20 | + |
| 21 | /* bring up all register ranges that we need for basic system control */ |
| 22 | void __init ltq_soc_init(void) |
| 23 | { |
| 24 | @@ -599,4 +613,6 @@ void __init ltq_soc_init(void) |
| 25 | clkdev_add_pmu("1e100400.serial", NULL, 1, 0, PMU_ASC0); |
| 26 | } |
| 27 | usb_set_clock(); |
| 28 | + |
| 29 | + set_phy_clock_source(np_cgu); |
| 30 | } |