blob: e6c96a052a14aa193d274bf2c53a185d3848d5f5 [file] [log] [blame]
b.liue9582032025-04-17 19:18:16 +08001From 0f90f5d6b3097fd6e7dea3389dc3d8f8894b345c Mon Sep 17 00:00:00 2001
2From: Haiying Wang <Haiying.Wang@freescale.com>
3Date: Wed, 22 Apr 2015 13:09:47 -0400
4Subject: [PATCH] arm64: add support to remap kernel cacheable memory to
5 userspace
6
7Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
8Reviewed-by: Roy Pledge <roy.pledge@freescale.com>
9Reviewed-by: Stuart Yoder <stuart.yoder@freescale.com>
10---
11 arch/arm64/include/asm/pgtable.h | 3 +++
12 1 file changed, 3 insertions(+)
13
14--- a/arch/arm64/include/asm/pgtable.h
15+++ b/arch/arm64/include/asm/pgtable.h
16@@ -428,6 +428,9 @@ static inline pmd_t pmd_mkdevmap(pmd_t p
17 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN)
18 #define pgprot_writecombine(prot) \
19 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN)
20+#define pgprot_cached(prot) \
21+ __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL) | \
22+ PTE_PXN | PTE_UXN)
23 #define pgprot_device(prot) \
24 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN)
25 /*