| b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 1 | From 5f008cb22f60da4e10375f22266c1a4e20b1252e Mon Sep 17 00:00:00 2001 |
| 2 | From: Alex Marginean <alexandru.marginean@nxp.com> |
| 3 | Date: Fri, 20 Sep 2019 18:22:52 +0300 |
| 4 | Subject: [PATCH] drivers: net: phy: aquantia: fix system side protocol |
| 5 | misconfiguration |
| 6 | |
| 7 | Do not set up protocols for speeds that are not supported by FW. Enabling |
| 8 | these protocols leads to link issues on system side. |
| 9 | |
| 10 | Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> |
| 11 | --- |
| 12 | drivers/net/phy/aquantia_main.c | 8 +++++++- |
| 13 | 1 file changed, 7 insertions(+), 1 deletion(-) |
| 14 | |
| 15 | --- a/drivers/net/phy/aquantia_main.c |
| 16 | +++ b/drivers/net/phy/aquantia_main.c |
| 17 | @@ -312,10 +312,16 @@ static int aqr_config_aneg_set_prot(stru |
| 18 | phy_write_mmd(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_GSTART_RATE, |
| 19 | aquantia_syscfg[if_type].start_rate); |
| 20 | |
| 21 | - for (i = 0; i <= aquantia_syscfg[if_type].cnt; i++) |
| 22 | + for (i = 0; i <= aquantia_syscfg[if_type].cnt; i++) { |
| 23 | + u16 reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, |
| 24 | + AQUANTIA_VND1_GSYSCFG_BASE + i); |
| 25 | + if (!reg) |
| 26 | + continue; |
| 27 | + |
| 28 | phy_write_mmd(phydev, MDIO_MMD_VEND1, |
| 29 | AQUANTIA_VND1_GSYSCFG_BASE + i, |
| 30 | aquantia_syscfg[if_type].syscfg); |
| 31 | + } |
| 32 | |
| 33 | /* wake PHY back up */ |
| 34 | phy_write_mmd(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_GLOBAL_SC, 0); |