blob: 0de8278cb63f129ec0ef1be1465838ab9e6cbace [file] [log] [blame]
b.liue9582032025-04-17 19:18:16 +08001From ca49d3e4820704bfc3d2b48f59238d26a584602d Mon Sep 17 00:00:00 2001
2From: Alex Marginean <alexandru.marginean@nxp.com>
3Date: Fri, 20 Sep 2019 19:37:19 +0300
4Subject: [PATCH] drivers: net: phy: aquantia: enable USX AN for USXGMII
5 protocol
6
7Depending on FW defaults USX AN in AQR PHY must be explicitly enabled when
8using USXGMII. Enable it based on interface type.
9
10Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
11---
12 drivers/net/phy/aquantia_main.c | 7 +++++++
13 1 file changed, 7 insertions(+)
14
15--- a/drivers/net/phy/aquantia_main.c
16+++ b/drivers/net/phy/aquantia_main.c
17@@ -33,6 +33,9 @@
18 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII 6
19 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII 10
20
21+#define MDIO_PHYXS_VEND_PROV2 0xC441
22+#define MDIO_PHYXS_VEND_PROV2_USX_AN BIT(3)
23+
24 #define MDIO_AN_VEND_PROV 0xc400
25 #define MDIO_AN_VEND_PROV_1000BASET_FULL BIT(15)
26 #define MDIO_AN_VEND_PROV_1000BASET_HALF BIT(14)
27@@ -323,6 +326,10 @@ static int aqr_config_aneg_set_prot(stru
28 aquantia_syscfg[if_type].syscfg);
29 }
30
31+ if (if_type == PHY_INTERFACE_MODE_USXGMII)
32+ phy_write_mmd(phydev, MDIO_MMD_PHYXS, MDIO_PHYXS_VEND_PROV2,
33+ MDIO_PHYXS_VEND_PROV2_USX_AN);
34+
35 /* wake PHY back up */
36 phy_write_mmd(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_GLOBAL_SC, 0);
37 mdelay(10);