b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0-only |
| 2 | |
| 3 | // TODO: not really used |
| 4 | struct rtl838x_phy_priv { |
| 5 | char *name; |
| 6 | }; |
| 7 | |
| 8 | struct __attribute__ ((__packed__)) part { |
| 9 | uint16_t start; |
| 10 | uint8_t wordsize; |
| 11 | uint8_t words; |
| 12 | }; |
| 13 | |
| 14 | struct __attribute__ ((__packed__)) fw_header { |
| 15 | uint32_t magic; |
| 16 | uint32_t phy; |
| 17 | uint32_t checksum; |
| 18 | uint32_t version; |
| 19 | struct part parts[10]; |
| 20 | }; |
| 21 | |
| 22 | // TODO: fixed path? |
| 23 | #define FIRMWARE_838X_8380_1 "rtl838x_phy/rtl838x_8380.fw" |
| 24 | #define FIRMWARE_838X_8214FC_1 "rtl838x_phy/rtl838x_8214fc.fw" |
| 25 | #define FIRMWARE_838X_8218b_1 "rtl838x_phy/rtl838x_8218b.fw" |
| 26 | |
| 27 | /* External RTL8218B and RTL8214FC IDs are identical */ |
| 28 | #define PHY_ID_RTL8214C 0x001cc942 |
| 29 | #define PHY_ID_RTL8214FC 0x001cc981 |
| 30 | #define PHY_ID_RTL8218B_E 0x001cc981 |
| 31 | #define PHY_ID_RTL8218D 0x001cc983 |
| 32 | #define PHY_ID_RTL8218B_I 0x001cca40 |
| 33 | #define PHY_ID_RTL8226 0x001cc838 |
| 34 | #define PHY_ID_RTL8390_GENERIC 0x001ccab0 |
| 35 | #define PHY_ID_RTL8393_I 0x001c8393 |
| 36 | #define PHY_ID_RTL9300_I 0x70d03106 |
| 37 | |
| 38 | // PHY MMD devices |
| 39 | #define MMD_AN 7 |
| 40 | #define MMD_VEND2 31 |
| 41 | |
| 42 | /* Registers of the internal Serdes of the 8380 */ |
| 43 | #define RTL838X_SDS_MODE_SEL (0x0028) |
| 44 | #define RTL838X_SDS_CFG_REG (0x0034) |
| 45 | #define RTL838X_INT_MODE_CTRL (0x005c) |
| 46 | #define RTL838X_DMY_REG31 (0x3b28) |
| 47 | |
| 48 | #define RTL8380_SDS4_FIB_REG0 (0xF800) |
| 49 | #define RTL838X_SDS4_REG28 (0xef80) |
| 50 | #define RTL838X_SDS4_DUMMY0 (0xef8c) |
| 51 | #define RTL838X_SDS5_EXT_REG6 (0xf18c) |
| 52 | #define RTL838X_SDS4_FIB_REG0 (RTL838X_SDS4_REG28 + 0x880) |
| 53 | #define RTL838X_SDS5_FIB_REG0 (RTL838X_SDS4_REG28 + 0x980) |
| 54 | |
| 55 | /* Registers of the internal SerDes of the RTL8390 */ |
| 56 | #define RTL839X_SDS12_13_XSG0 (0xB800) |
| 57 | |
| 58 | /* Registers of the internal Serdes of the 9300 */ |
| 59 | #define RTL930X_SDS_INDACS_CMD (0x03B0) |
| 60 | #define RTL930X_SDS_INDACS_DATA (0x03B4) |