| b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 1 | From: Gabor Juhos <juhosg@openwrt.org> |
| 2 | Subject: debloat: add kernel config option to disabling common PCI quirks |
| 3 | |
| 4 | Signed-off-by: Gabor Juhos <juhosg@openwrt.org> |
| 5 | --- |
| 6 | drivers/pci/Kconfig | 6 ++++++ |
| 7 | drivers/pci/quirks.c | 6 ++++++ |
| 8 | 2 files changed, 12 insertions(+) |
| 9 | |
| 10 | --- a/drivers/pci/Kconfig |
| 11 | +++ b/drivers/pci/Kconfig |
| 12 | @@ -115,6 +115,13 @@ config XEN_PCIDEV_FRONTEND |
| 13 | The PCI device frontend driver allows the kernel to import arbitrary |
| 14 | PCI devices from a PCI backend to support PCI driver domains. |
| 15 | |
| 16 | +config PCI_DISABLE_COMMON_QUIRKS |
| 17 | + bool "PCI disable common quirks" |
| 18 | + depends on PCI |
| 19 | + help |
| 20 | + If you don't know what to do here, say N. |
| 21 | + |
| 22 | + |
| 23 | config PCI_ATS |
| 24 | bool |
| 25 | |
| 26 | --- a/drivers/pci/quirks.c |
| 27 | +++ b/drivers/pci/quirks.c |
| 28 | @@ -206,6 +206,7 @@ static void quirk_mmio_always_on(struct |
| 29 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID, |
| 30 | PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on); |
| 31 | |
| 32 | +#ifndef CONFIG_PCI_DISABLE_COMMON_QUIRKS |
| 33 | /* |
| 34 | * The Mellanox Tavor device gives false positive parity errors. Mark this |
| 35 | * device with a broken_parity_status to allow PCI scanning code to "skip" |
| 36 | @@ -3323,6 +3324,8 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_I |
| 37 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata); |
| 38 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata); |
| 39 | |
| 40 | +#endif /* !CONFIG_PCI_DISABLE_COMMON_QUIRKS */ |
| 41 | + |
| 42 | /* |
| 43 | * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum. |
| 44 | * To work around this, query the size it should be configured to by the |
| 45 | @@ -3348,6 +3351,8 @@ static void quirk_intel_ntb(struct pci_d |
| 46 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb); |
| 47 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb); |
| 48 | |
| 49 | +#ifndef CONFIG_PCI_DISABLE_COMMON_QUIRKS |
| 50 | + |
| 51 | /* |
| 52 | * Some BIOS implementations leave the Intel GPU interrupts enabled, even |
| 53 | * though no one is handling them (e.g., if the i915 driver is never |
| 54 | @@ -3386,6 +3391,8 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_IN |
| 55 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq); |
| 56 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq); |
| 57 | |
| 58 | +#endif /* !CONFIG_PCI_DISABLE_COMMON_QUIRKS */ |
| 59 | + |
| 60 | /* |
| 61 | * PCI devices which are on Intel chips can skip the 10ms delay |
| 62 | * before entering D3 mode. |