| b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame] | 1 | /dts-v1/; |
| 2 | |
| 3 | / { |
| 4 | #address-cells = <1>; |
| 5 | #size-cells = <1>; |
| 6 | compatible = "brcm,bcm6338"; |
| 7 | |
| 8 | aliases { |
| 9 | pflash = &pflash; |
| 10 | gpio0 = &gpio0; |
| 11 | serial0 = &uart0; |
| 12 | spi0 = &lsspi; |
| 13 | }; |
| 14 | |
| 15 | cpus { |
| 16 | #address-cells = <1>; |
| 17 | #size-cells = <0>; |
| 18 | |
| 19 | cpu@0 { |
| 20 | compatible = "brcm,bmips3300", "mips,mips4Kc"; |
| 21 | device_type = "cpu"; |
| 22 | reg = <0>; |
| 23 | }; |
| 24 | }; |
| 25 | |
| 26 | cpu_intc: interrupt-controller { |
| 27 | #address-cells = <0>; |
| 28 | compatible = "mti,cpu-interrupt-controller"; |
| 29 | |
| 30 | interrupt-controller; |
| 31 | #interrupt-cells = <1>; |
| 32 | }; |
| 33 | |
| 34 | memory { device_type = "memory"; reg = <0 0>; }; |
| 35 | |
| 36 | pflash: nor@1fc00000 { |
| 37 | compatible = "cfi-flash"; |
| 38 | reg = <0x1fc00000 0x400000>; |
| 39 | bank-width = <2>; |
| 40 | #address-cells = <1>; |
| 41 | #size-cells = <1>; |
| 42 | |
| 43 | status = "disabled"; |
| 44 | }; |
| 45 | |
| 46 | ubus@fff00000 { |
| 47 | #address-cells = <1>; |
| 48 | #size-cells = <1>; |
| 49 | ranges; |
| 50 | compatible = "simple-bus"; |
| 51 | interrupt-parent = <&periph_intc>; |
| 52 | |
| 53 | periph_intc: interrupt-controller@fffe000c { |
| 54 | compatible = "brcm,bcm6345-l1-intc"; |
| 55 | reg = <0xfffe000c 0x8>; |
| 56 | |
| 57 | interrupt-controller; |
| 58 | #interrupt-cells = <1>; |
| 59 | |
| 60 | interrupt-parent = <&cpu_intc>; |
| 61 | interrupts = <2>; |
| 62 | }; |
| 63 | |
| 64 | ext_intc: interrupt-controller@fffe0014 { |
| 65 | compatible = "brcm,bcm6345-ext-intc"; |
| 66 | reg = <0xfffe0014 0x4>; |
| 67 | |
| 68 | interrupt-controller; |
| 69 | #interrupt-cells = <2>; |
| 70 | |
| 71 | interrupt-parent = <&cpu_intc>; |
| 72 | interrupts = <3>, <4>, <5>, <6>; |
| 73 | }; |
| 74 | |
| 75 | gpio0: gpio-controller@fffe0404 { |
| 76 | compatible = "brcm,bcm6345-gpio"; |
| 77 | reg = <0xfffe0404 4>, <0xfffe040c 4>; |
| 78 | |
| 79 | gpio-controller; |
| 80 | #gpio-cells = <2>; |
| 81 | |
| 82 | ngpios = <8>; |
| 83 | }; |
| 84 | |
| 85 | uart0: serial@fffe0300 { |
| 86 | compatible = "brcm,bcm6345-uart"; |
| 87 | reg = <0xfffe0300 0x18>; |
| 88 | |
| 89 | interrupt-parent = <&periph_intc>; |
| 90 | interrupts = <2>; |
| 91 | |
| 92 | /* clocks = <&periph_clk>; */ |
| 93 | /* clock-names = "refclk"; */ |
| 94 | |
| 95 | status = "disabled"; |
| 96 | }; |
| 97 | |
| 98 | lsspi: spi@fffe0c00 { |
| 99 | #address-cells = <1>; |
| 100 | #size-cells = <0>; |
| 101 | compatible = "brcm,bcm6348-spi"; |
| 102 | reg = <0xfffe0c00 0x40>; |
| 103 | interrupts = <1>; |
| 104 | /* clocks = <&clkctl 9>; */ |
| 105 | }; |
| 106 | }; |
| 107 | }; |