blob: 5c52bde70d2bd206bb0df3aea4a906a71b7138cc [file] [log] [blame]
b.liue9582032025-04-17 19:18:16 +08001From a1fb69366bb16753f0fba6a891fbef5cdd97cfbe Mon Sep 17 00:00:00 2001
2From: Tim Harvey <tharvey@gateworks.com>
3Date: Wed, 8 Jan 2020 07:44:22 -0800
4Subject: [PATCH 2/4] ARM: dts: imx: Add GW5910 board support
5
6The Gateworks GW5910 is an IMX6 SoC based single board computer with:
7 - IMX6Q or IMX6DL
8 - 32bit DDR3 DRAM
9 - FEC GbE RJ45 front-panel
10 - 1x miniPCIe socket with PCI Gen2, USB2
11 - 1x miniPCIe socket with PCI Gen2, USB2, nanoSIM
12 - 5V to 60V DC input barrel jack
13 - 3axis accelerometer (lis2de12)
14 - GPS (ublox ZOE-M8Q)
15 - bi-color front-panel LED
16 - 256MB NAND boot device
17 - microSD socket (with UHS-I support)
18 - user pushbutton
19 - Gateworks System Controller (hwmon, pushbutton controller, EEPROM)
20 - Dual-Band Wireless MCU (CC1352, UART/I2S interrconnect to IMX6)
21 - WiFi/Bluetooth/BLE module (Sterling-LSW, SDIO/UART interconnect to IMX6)
22 - RS232 transceiver (1x UART with flow-control or 2x UART (build option)
23 - off-board SPI connector (1x chip-select)
24
25Signed-off-by: Tim Harvey <tharvey@gateworks.com>
26Signed-off-by: Robert Jones <rjones@gateworks.com>
27Signed-off-by: Shawn Guo <shawnguo@kernel.org>
28---
29 arch/arm/boot/dts/Makefile | 2 +
30 arch/arm/boot/dts/imx6dl-gw5910.dts | 14 +
31 arch/arm/boot/dts/imx6q-gw5910.dts | 14 +
32 arch/arm/boot/dts/imx6qdl-gw5910.dtsi | 491 ++++++++++++++++++++++++++++++++++
33 4 files changed, 521 insertions(+)
34 create mode 100644 arch/arm/boot/dts/imx6dl-gw5910.dts
35 create mode 100644 arch/arm/boot/dts/imx6q-gw5910.dts
36 create mode 100644 arch/arm/boot/dts/imx6qdl-gw5910.dtsi
37
38--- a/arch/arm/boot/dts/Makefile
39+++ b/arch/arm/boot/dts/Makefile
40@@ -419,6 +419,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
41 imx6dl-gw5903.dtb \
42 imx6dl-gw5904.dtb \
43 imx6dl-gw5907.dtb \
44+ imx6dl-gw5910.dtb \
45 imx6dl-hummingboard.dtb \
46 imx6dl-hummingboard-emmc-som-v15.dtb \
47 imx6dl-hummingboard-som-v15.dtb \
48@@ -491,6 +492,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
49 imx6q-gw5903.dtb \
50 imx6q-gw5904.dtb \
51 imx6q-gw5907.dtb \
52+ imx6q-gw5910.dtb \
53 imx6q-h100.dtb \
54 imx6q-hummingboard.dtb \
55 imx6q-hummingboard-emmc-som-v15.dtb \
56--- /dev/null
57+++ b/arch/arm/boot/dts/imx6dl-gw5910.dts
58@@ -0,0 +1,14 @@
59+// SPDX-License-Identifier: GPL-2.0
60+/*
61+ * Copyright 2019 Gateworks Corporation
62+ */
63+
64+/dts-v1/;
65+
66+#include "imx6dl.dtsi"
67+#include "imx6qdl-gw5910.dtsi"
68+
69+/ {
70+ model = "Gateworks Ventana i.MX6 DualLite/Solo GW5910";
71+ compatible = "gw,imx6dl-gw5910", "gw,ventana", "fsl,imx6dl";
72+};
73--- /dev/null
74+++ b/arch/arm/boot/dts/imx6q-gw5910.dts
75@@ -0,0 +1,14 @@
76+// SPDX-License-Identifier: GPL-2.0
77+/*
78+ * Copyright 2019 Gateworks Corporation
79+ */
80+
81+/dts-v1/;
82+
83+#include "imx6q.dtsi"
84+#include "imx6qdl-gw5910.dtsi"
85+
86+/ {
87+ model = "Gateworks Ventana i.MX6 Dual/Quad GW5910";
88+ compatible = "gw,imx6q-gw5910", "gw,ventana", "fsl,imx6q";
89+};
90--- /dev/null
91+++ b/arch/arm/boot/dts/imx6qdl-gw5910.dtsi
92@@ -0,0 +1,489 @@
93+// SPDX-License-Identifier: GPL-2.0
94+/*
95+ * Copyright 2019 Gateworks Corporation
96+ */
97+
98+#include <dt-bindings/gpio/gpio.h>
99+
100+/ {
101+ /* these are used by bootloader for disabling nodes */
102+ aliases {
103+ led0 = &led0;
104+ led1 = &led1;
105+ led2 = &led2;
106+ };
107+
108+ chosen {
109+ stdout-path = &uart2;
110+ };
111+
112+ memory@10000000 {
113+ device_type = "memory";
114+ reg = <0x10000000 0x20000000>;
115+ };
116+
117+ leds {
118+ compatible = "gpio-leds";
119+ pinctrl-names = "default";
120+ pinctrl-0 = <&pinctrl_gpio_leds>;
121+
122+ led0: user1 {
123+ label = "user1";
124+ gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
125+ default-state = "on";
126+ linux,default-trigger = "heartbeat";
127+ };
128+
129+ led1: user2 {
130+ label = "user2";
131+ gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
132+ };
133+
134+ led2: user3 {
135+ label = "user3";
136+ gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
137+ };
138+ };
139+
140+ pps {
141+ compatible = "pps-gpio";
142+ pinctrl-names = "default";
143+ pinctrl-0 = <&pinctrl_pps>;
144+ gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
145+ status = "okay";
146+ };
147+
148+ reg_3p3v: regulator-3p3v {
149+ compatible = "regulator-fixed";
150+ regulator-name = "3P3V";
151+ regulator-min-microvolt = <3300000>;
152+ regulator-max-microvolt = <3300000>;
153+ regulator-always-on;
154+ };
155+
156+ reg_5p0v: regulator-5p0v {
157+ compatible = "regulator-fixed";
158+ regulator-name = "5P0V";
159+ regulator-min-microvolt = <5000000>;
160+ regulator-max-microvolt = <5000000>;
161+ regulator-always-on;
162+ };
163+
164+ reg_wl: regulator-wl {
165+ pinctrl-names = "default";
166+ pinctrl-0 = <&pinctrl_reg_wl>;
167+ compatible = "regulator-fixed";
168+ regulator-name = "wl";
169+ gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
170+ startup-delay-us = <100>;
171+ enable-active-high;
172+ regulator-min-microvolt = <3300000>;
173+ regulator-max-microvolt = <3300000>;
174+ regulator-always-on;
175+ };
176+
177+ reg_bt: regulator-bt {
178+ pinctrl-names = "default";
179+ pinctrl-0 = <&pinctrl_reg_bt>;
180+ compatible = "regulator-fixed";
181+ regulator-name = "bt";
182+ gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
183+ startup-delay-us = <100>;
184+ enable-active-high;
185+ regulator-min-microvolt = <3300000>;
186+ regulator-max-microvolt = <3300000>;
187+ regulator-always-on;
188+ };
189+};
190+
191+
192+&ecspi3 {
193+ cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>;
194+ pinctrl-names = "default";
195+ pinctrl-0 = <&pinctrl_ecspi3>;
196+ status = "okay";
197+};
198+
199+&fec {
200+ pinctrl-names = "default";
201+ pinctrl-0 = <&pinctrl_enet>;
202+ phy-mode = "rgmii-id";
203+ status = "okay";
204+};
205+
206+&gpmi {
207+ pinctrl-names = "default";
208+ pinctrl-0 = <&pinctrl_gpmi_nand>;
209+ status = "okay";
210+};
211+
212+&i2c1 {
213+ clock-frequency = <100000>;
214+ pinctrl-names = "default";
215+ pinctrl-0 = <&pinctrl_i2c1>;
216+ status = "okay";
217+
218+ gpio@23 {
219+ compatible = "nxp,pca9555";
220+ reg = <0x23>;
221+ gpio-controller;
222+ #gpio-cells = <2>;
223+ };
224+
225+ eeprom@50 {
226+ compatible = "atmel,24c02";
227+ reg = <0x50>;
228+ pagesize = <16>;
229+ };
230+
231+ eeprom@51 {
232+ compatible = "atmel,24c02";
233+ reg = <0x51>;
234+ pagesize = <16>;
235+ };
236+
237+ eeprom@52 {
238+ compatible = "atmel,24c02";
239+ reg = <0x52>;
240+ pagesize = <16>;
241+ };
242+
243+ eeprom@53 {
244+ compatible = "atmel,24c02";
245+ reg = <0x53>;
246+ pagesize = <16>;
247+ };
248+
249+ rtc@68 {
250+ compatible = "dallas,ds1672";
251+ reg = <0x68>;
252+ };
253+};
254+
255+&i2c2 {
256+ clock-frequency = <100000>;
257+ pinctrl-names = "default";
258+ pinctrl-0 = <&pinctrl_i2c2>;
259+ status = "okay";
260+};
261+
262+&i2c3 {
263+ clock-frequency = <100000>;
264+ pinctrl-names = "default";
265+ pinctrl-0 = <&pinctrl_i2c3>;
266+ status = "okay";
267+
268+ accel@19 {
269+ pinctrl-names = "default";
270+ pinctrl-0 = <&pinctrl_accel>;
271+ compatible = "st,lis2de12";
272+ reg = <0x19>;
273+ st,drdy-int-pin = <1>;
274+ interrupt-parent = <&gpio7>;
275+ interrupts = <13 0>;
276+ interrupt-names = "INT1";
277+ };
278+};
279+
280+&pcie {
281+ pinctrl-names = "default";
282+ pinctrl-0 = <&pinctrl_pcie>;
283+ reset-gpio = <&gpio3 20 GPIO_ACTIVE_LOW>;
284+ status = "okay";
285+};
286+
287+&pwm2 {
288+ pinctrl-names = "default";
289+ pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
290+ status = "disabled";
291+};
292+
293+&pwm3 {
294+ pinctrl-names = "default";
295+ pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
296+ status = "disabled";
297+};
298+
299+/* off-board RS232 */
300+&uart1 {
301+ pinctrl-names = "default";
302+ pinctrl-0 = <&pinctrl_uart1>;
303+ status = "okay";
304+};
305+
306+/* serial console */
307+&uart2 {
308+ pinctrl-names = "default";
309+ pinctrl-0 = <&pinctrl_uart2>;
310+ status = "okay";
311+};
312+
313+/* Sterling-LWB Bluetooth */
314+&uart4 {
315+ pinctrl-names = "default";
316+ pinctrl-0 = <&pinctrl_uart4>;
317+ uart-has-rtscts;
318+ status = "okay";
319+};
320+
321+/* GPS */
322+&uart5 {
323+ pinctrl-names = "default";
324+ pinctrl-0 = <&pinctrl_uart5>;
325+ status = "okay";
326+};
327+
328+&usbotg {
329+ vbus-supply = <&reg_5p0v>;
330+ pinctrl-names = "default";
331+ pinctrl-0 = <&pinctrl_usbotg>;
332+ disable-over-current;
333+ status = "okay";
334+};
335+
336+&usbh1 {
337+ status = "okay";
338+};
339+
340+/* Sterling-LWB SDIO WiFi */
341+&usdhc2 {
342+ pinctrl-names = "default";
343+ pinctrl-0 = <&pinctrl_usdhc2>;
344+ vmmc-supply = <&reg_3p3v>;
345+ non-removable;
346+ bus-width = <4>;
347+ status = "okay";
348+};
349+
350+&usdhc3 {
351+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
352+ pinctrl-0 = <&pinctrl_usdhc3>;
353+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
354+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
355+ cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
356+ vmmc-supply = <&reg_3p3v>;
357+ status = "okay";
358+};
359+
360+&wdog1 {
361+ pinctrl-names = "default";
362+ pinctrl-0 = <&pinctrl_wdog>;
363+ fsl,ext-reset-output;
364+};
365+
366+&iomuxc {
367+ pinctrl_accel: accelmuxgrp {
368+ fsl,pins = <
369+ MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b1
370+ >;
371+ };
372+
373+ pinctrl_ecspi3: escpi3grp {
374+ fsl,pins = <
375+ MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
376+ MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
377+ MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
378+ MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x100b1
379+ >;
380+ };
381+
382+ pinctrl_enet: enetgrp {
383+ fsl,pins = <
384+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
385+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
386+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
387+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
388+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
389+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
390+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
391+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
392+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
393+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
394+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
395+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
396+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
397+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
398+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
399+ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
400+ MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0
401+ >;
402+ };
403+
404+ pinctrl_gpio_leds: gpioledsgrp {
405+ fsl,pins = <
406+ MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
407+ MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
408+ MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
409+ >;
410+ };
411+
412+ pinctrl_gpmi_nand: gpminandgrp {
413+ fsl,pins = <
414+ MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
415+ MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
416+ MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
417+ MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
418+ MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
419+ MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
420+ MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
421+ MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
422+ MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
423+ MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
424+ MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
425+ MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
426+ MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
427+ MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
428+ MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
429+ >;
430+ };
431+
432+ pinctrl_i2c1: i2c1grp {
433+ fsl,pins = <
434+ MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
435+ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
436+ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0
437+ >;
438+ };
439+
440+ pinctrl_i2c2: i2c2grp {
441+ fsl,pins = <
442+ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
443+ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
444+ >;
445+ };
446+
447+ pinctrl_i2c3: i2c3grp {
448+ fsl,pins = <
449+ MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
450+ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
451+ >;
452+ };
453+
454+ pinctrl_pcie: pciegrp {
455+ fsl,pins = <
456+ MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b0
457+ >;
458+ };
459+
460+ pinctrl_pps: ppsgrp {
461+ fsl,pins = <
462+ MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x1b0b1
463+ >;
464+ };
465+
466+ pinctrl_pwm2: pwm2grp {
467+ fsl,pins = <
468+ MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
469+ >;
470+ };
471+
472+ pinctrl_pwm3: pwm3grp {
473+ fsl,pins = <
474+ MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
475+ >;
476+ };
477+
478+ pinctrl_reg_bt: regbtgrp {
479+ fsl,pins = <
480+ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b1
481+ >;
482+ };
483+
484+ pinctrl_reg_wl: regwlgrp {
485+ fsl,pins = <
486+ MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b1
487+ >;
488+ };
489+
490+ pinctrl_uart1: uart1grp {
491+ fsl,pins = <
492+ MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
493+ MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
494+ >;
495+ };
496+
497+ pinctrl_uart2: uart2grp {
498+ fsl,pins = <
499+ MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
500+ MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
501+ >;
502+ };
503+
504+ pinctrl_uart4: uart4grp {
505+ fsl,pins = <
506+ MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
507+ MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1
508+ MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1
509+ MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1
510+ >;
511+ };
512+
513+ pinctrl_uart5: uart5grp {
514+ fsl,pins = <
515+ MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
516+ MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
517+ >;
518+ };
519+
520+ pinctrl_usbotg: usbotggrp {
521+ fsl,pins = <
522+ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059
523+ >;
524+ };
525+
526+ pinctrl_usdhc2: usdhc2grp {
527+ fsl,pins = <
528+ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
529+ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
530+ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
531+ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
532+ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
533+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
534+ >;
535+ };
536+
537+ pinctrl_usdhc3: usdhc3grp {
538+ fsl,pins = <
539+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
540+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
541+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
542+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
543+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
544+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
545+ MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */
546+ MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059
547+ >;
548+ };
549+
550+ pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
551+ fsl,pins = <
552+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
553+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x170b9
554+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
555+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
556+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
557+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
558+ MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */
559+ MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9
560+ >;
561+ };
562+
563+ pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
564+ fsl,pins = <
565+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
566+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
567+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
568+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
569+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
570+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
571+ MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
572+ MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
573+ >;
574+ };
575+
576+ pinctrl_wdog: wdoggrp {
577+ fsl,pins = <
578+ MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
579+ >;
580+ };
581+};