blob: da733ff357c6d16505f8237cb30a8da9dc637a4a [file] [log] [blame]
b.liue9582032025-04-17 19:18:16 +08001From 9a820b55817011f53771e6bfebae5fe059f0a534 Mon Sep 17 00:00:00 2001
2From: Robert Jones <rjones@gateworks.com>
3Date: Wed, 8 Jan 2020 07:44:24 -0800
4Subject: [PATCH 4/4] ARM: dts: imx: Add GW5912 board support
5
6The Gateworks GW5912 is an IMX6 SoC based single board computer with:
7 - IMX6Q or IMX6DL
8 - 32bit DDR3 DRAM
9 - GbE RJ45 front-panel
10 - 4x miniPCIe socket with PCI Gen2, USB2
11 - 1x miniPCIe socket with PCI Gen2, USB2, mSATA
12 - 1x miniPCIe socket with PCI Gen2, USB2, mezzanine
13 - 10V to 60V DC input barrel jack
14 - 3axis accelerometer (lis2de12)
15 - GPS (ublox ZOE-M8Q)
16 - bi-color front-panel LED
17 - 256MB NAND boot device
18 - nanoSIM/microSD socket (with UHS-I support)
19 - user pushbutton
20 - Gateworks System Controller (hwmon, pushbutton controller, EEPROM)
21 - CAN Bus transceiver (mcp2562)
22 - RS232 transceiver (1x UART with flow-control or 2x UART (build option)
23 - off-board SPI connector (1x chip-select)
24
25Signed-off-by: Robert Jones <rjones@gateworks.com>
26Reviewed-by: Tim Harvey <tharvey@gateworks.com>
27Signed-off-by: Shawn Guo <shawnguo@kernel.org>
28---
29 arch/arm/boot/dts/Makefile | 2 +
30 arch/arm/boot/dts/imx6dl-gw5912.dts | 13 +
31 arch/arm/boot/dts/imx6q-gw5912.dts | 13 +
32 arch/arm/boot/dts/imx6qdl-gw5912.dtsi | 461 ++++++++++++++++++++++++++++++++++
33 4 files changed, 489 insertions(+)
34 create mode 100644 arch/arm/boot/dts/imx6dl-gw5912.dts
35 create mode 100644 arch/arm/boot/dts/imx6q-gw5912.dts
36 create mode 100644 arch/arm/boot/dts/imx6qdl-gw5912.dtsi
37
38--- a/arch/arm/boot/dts/Makefile
39+++ b/arch/arm/boot/dts/Makefile
40@@ -420,6 +420,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
41 imx6dl-gw5904.dtb \
42 imx6dl-gw5907.dtb \
43 imx6dl-gw5910.dtb \
44+ imx6dl-gw5912.dtb \
45 imx6dl-gw5913.dtb \
46 imx6dl-hummingboard.dtb \
47 imx6dl-hummingboard-emmc-som-v15.dtb \
48@@ -494,6 +495,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
49 imx6q-gw5904.dtb \
50 imx6q-gw5907.dtb \
51 imx6q-gw5910.dtb \
52+ imx6q-gw5912.dtb \
53 imx6q-gw5913.dtb \
54 imx6q-h100.dtb \
55 imx6q-hummingboard.dtb \
56--- /dev/null
57+++ b/arch/arm/boot/dts/imx6dl-gw5912.dts
58@@ -0,0 +1,13 @@
59+// SPDX-License-Identifier: GPL-2.0
60+/*
61+ * Copyright 2019 Gateworks Corporation
62+ */
63+
64+/dts-v1/;
65+#include "imx6dl.dtsi"
66+#include "imx6qdl-gw5912.dtsi"
67+
68+/ {
69+ model = "Gateworks Ventana i.MX6 DualLite/Solo GW5912";
70+ compatible = "gw,imx6dl-gw5912", "gw,ventana", "fsl,imx6dl";
71+};
72--- /dev/null
73+++ b/arch/arm/boot/dts/imx6q-gw5912.dts
74@@ -0,0 +1,13 @@
75+// SPDX-License-Identifier: GPL-2.0
76+/*
77+ * Copyright 2019 Gateworks Corporation
78+ */
79+
80+/dts-v1/;
81+#include "imx6q.dtsi"
82+#include "imx6qdl-gw5912.dtsi"
83+
84+/ {
85+ model = "Gateworks Ventana i.MX6 Dual/Quad GW5912";
86+ compatible = "gw,imx6q-gw5912", "gw,ventana", "fsl,imx6q";
87+};
88--- /dev/null
89+++ b/arch/arm/boot/dts/imx6qdl-gw5912.dtsi
90@@ -0,0 +1,459 @@
91+// SPDX-License-Identifier: GPL-2.0
92+/*
93+ * Copyright 2019 Gateworks Corporation
94+ */
95+
96+#include <dt-bindings/gpio/gpio.h>
97+
98+/ {
99+ /* these are used by bootloader for disabling nodes */
100+ aliases {
101+ led0 = &led0;
102+ led1 = &led1;
103+ led2 = &led2;
104+ nand = &gpmi;
105+ usb0 = &usbh1;
106+ usb1 = &usbotg;
107+ };
108+
109+ chosen {
110+ stdout-path = &uart2;
111+ };
112+
113+ leds {
114+ compatible = "gpio-leds";
115+ pinctrl-names = "default";
116+ pinctrl-0 = <&pinctrl_gpio_leds>;
117+
118+ led0: user1 {
119+ label = "user1";
120+ gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
121+ default-state = "on";
122+ linux,default-trigger = "heartbeat";
123+ };
124+
125+ led1: user2 {
126+ label = "user2";
127+ gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
128+ };
129+
130+ led2: user3 {
131+ label = "user3";
132+ gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
133+ };
134+ };
135+
136+ memory@10000000 {
137+ device_type = "memory";
138+ reg = <0x10000000 0x40000000>;
139+ };
140+
141+ pps {
142+ compatible = "pps-gpio";
143+ pinctrl-names = "default";
144+ pinctrl-0 = <&pinctrl_pps>;
145+ gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
146+ };
147+
148+ reg_3p3v: regulator-3p3v {
149+ compatible = "regulator-fixed";
150+ regulator-name = "3P3V";
151+ regulator-min-microvolt = <3300000>;
152+ regulator-max-microvolt = <3300000>;
153+ regulator-always-on;
154+ };
155+
156+ reg_usb_vbus: regulator-5p0v {
157+ compatible = "regulator-fixed";
158+ regulator-name = "usb_vbus";
159+ regulator-min-microvolt = <5000000>;
160+ regulator-max-microvolt = <5000000>;
161+ regulator-always-on;
162+ };
163+};
164+
165+&can1 {
166+ pinctrl-names = "default";
167+ pinctrl-0 = <&pinctrl_flexcan1>;
168+ status = "okay";
169+};
170+
171+&ecspi2 {
172+ cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
173+ pinctrl-names = "default";
174+ pinctrl-0 = <&pinctrl_ecspi2>;
175+ status = "okay";
176+};
177+
178+&fec {
179+ pinctrl-names = "default";
180+ pinctrl-0 = <&pinctrl_enet>;
181+ phy-mode = "rgmii-id";
182+ status = "okay";
183+};
184+
185+&gpmi {
186+ pinctrl-names = "default";
187+ pinctrl-0 = <&pinctrl_gpmi_nand>;
188+ status = "okay";
189+};
190+
191+&i2c1 {
192+ clock-frequency = <100000>;
193+ pinctrl-names = "default";
194+ pinctrl-0 = <&pinctrl_i2c1>;
195+ status = "okay";
196+
197+ gpio@23 {
198+ compatible = "nxp,pca9555";
199+ reg = <0x23>;
200+ gpio-controller;
201+ #gpio-cells = <2>;
202+ };
203+
204+ eeprom@50 {
205+ compatible = "atmel,24c02";
206+ reg = <0x50>;
207+ pagesize = <16>;
208+ };
209+
210+ eeprom@51 {
211+ compatible = "atmel,24c02";
212+ reg = <0x51>;
213+ pagesize = <16>;
214+ };
215+
216+ eeprom@52 {
217+ compatible = "atmel,24c02";
218+ reg = <0x52>;
219+ pagesize = <16>;
220+ };
221+
222+ eeprom@53 {
223+ compatible = "atmel,24c02";
224+ reg = <0x53>;
225+ pagesize = <16>;
226+ };
227+
228+ rtc@68 {
229+ compatible = "dallas,ds1672";
230+ reg = <0x68>;
231+ };
232+};
233+
234+&i2c2 {
235+ clock-frequency = <100000>;
236+ pinctrl-names = "default";
237+ pinctrl-0 = <&pinctrl_i2c2>;
238+ status = "okay";
239+};
240+
241+&i2c3 {
242+ clock-frequency = <100000>;
243+ pinctrl-names = "default";
244+ pinctrl-0 = <&pinctrl_i2c3>;
245+ status = "okay";
246+
247+ accel@19 {
248+ pinctrl-names = "default";
249+ pinctrl-0 = <&pinctrl_accel>;
250+ compatible = "st,lis2de12";
251+ reg = <0x19>;
252+ st,drdy-int-pin = <1>;
253+ interrupt-parent = <&gpio7>;
254+ interrupts = <13 0>;
255+ interrupt-names = "INT1";
256+ };
257+};
258+
259+&pcie {
260+ pinctrl-names = "default";
261+ pinctrl-0 = <&pinctrl_pcie>;
262+ reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
263+ status = "okay";
264+};
265+
266+&pwm1 {
267+ pinctrl-names = "default";
268+ pinctrl-0 = <&pinctrl_pwm1>; /* MX6_DIO0 */
269+ status = "disabled";
270+};
271+
272+&pwm2 {
273+ pinctrl-names = "default";
274+ pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
275+ status = "disabled";
276+};
277+
278+&pwm3 {
279+ pinctrl-names = "default";
280+ pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
281+ status = "disabled";
282+};
283+
284+&pwm4 {
285+ pinctrl-names = "default";
286+ pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */
287+ status = "disabled";
288+};
289+
290+&uart1 {
291+ pinctrl-names = "default";
292+ pinctrl-0 = <&pinctrl_uart1>;
293+ rts-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>;
294+ status = "okay";
295+};
296+
297+&uart2 {
298+ pinctrl-names = "default";
299+ pinctrl-0 = <&pinctrl_uart2>;
300+ status = "okay";
301+};
302+
303+&uart5 {
304+ pinctrl-names = "default";
305+ pinctrl-0 = <&pinctrl_uart5>;
306+ status = "okay";
307+};
308+
309+&usbotg {
310+ vbus-supply = <&reg_usb_vbus>;
311+ pinctrl-names = "default";
312+ pinctrl-0 = <&pinctrl_usbotg>;
313+ disable-over-current;
314+ dr_mode = "host";
315+ status = "okay";
316+};
317+
318+&usbh1 {
319+ vbus-supply = <&reg_usb_vbus>;
320+ status = "okay";
321+};
322+
323+&usdhc3 {
324+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
325+ pinctrl-0 = <&pinctrl_usdhc3>;
326+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
327+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
328+ cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
329+ vmmc-supply = <&reg_3p3v>;
330+ no-1-8-v; /* firmware will remove if board revision supports */
331+ status = "okay";
332+};
333+
334+&wdog1 {
335+ status = "disabled";
336+};
337+
338+&wdog2 {
339+ pinctrl-names = "default";
340+ pinctrl-0 = <&pinctrl_wdog>;
341+ fsl,ext-reset-output;
342+ status = "okay";
343+};
344+
345+&iomuxc {
346+ pinctrl_accel: accelmuxgrp {
347+ fsl,pins = <
348+ MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b1
349+ >;
350+ };
351+
352+ pinctrl_enet: enetgrp {
353+ fsl,pins = <
354+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
355+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
356+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
357+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
358+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
359+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
360+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
361+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
362+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
363+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
364+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
365+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
366+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
367+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
368+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
369+ >;
370+ };
371+
372+ pinctrl_ecspi2: escpi2grp {
373+ fsl,pins = <
374+ MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
375+ MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
376+ MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1
377+ MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x100b1
378+ >;
379+ };
380+
381+ pinctrl_flexcan1: flexcan1grp {
382+ fsl,pins = <
383+ MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
384+ MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
385+ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0
386+ >;
387+ };
388+
389+ pinctrl_gpio_leds: gpioledsgrp {
390+ fsl,pins = <
391+ MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
392+ MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
393+ MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
394+ >;
395+ };
396+
397+ pinctrl_gpmi_nand: gpminandgrp {
398+ fsl,pins = <
399+ MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
400+ MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
401+ MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
402+ MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
403+ MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
404+ MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
405+ MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
406+ MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
407+ MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
408+ MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
409+ MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
410+ MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
411+ MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
412+ MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
413+ MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
414+ >;
415+ };
416+
417+ pinctrl_i2c1: i2c1grp {
418+ fsl,pins = <
419+ MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
420+ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
421+ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0
422+ >;
423+ };
424+
425+ pinctrl_i2c2: i2c2grp {
426+ fsl,pins = <
427+ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
428+ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
429+ >;
430+ };
431+
432+ pinctrl_i2c3: i2c3grp {
433+ fsl,pins = <
434+ MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
435+ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
436+ >;
437+ };
438+
439+ pinctrl_pcie: pciegrp {
440+ fsl,pins = <
441+ MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0
442+ MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
443+ >;
444+ };
445+
446+ pinctrl_pps: ppsgrp {
447+ fsl,pins = <
448+ MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b1
449+ >;
450+ };
451+
452+ pinctrl_pwm1: pwm1grp {
453+ fsl,pins = <
454+ MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
455+ >;
456+ };
457+
458+ pinctrl_pwm2: pwm2grp {
459+ fsl,pins = <
460+ MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
461+ >;
462+ };
463+
464+ pinctrl_pwm3: pwm3grp {
465+ fsl,pins = <
466+ MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
467+ >;
468+ };
469+
470+ pinctrl_pwm4: pwm4grp {
471+ fsl,pins = <
472+ MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1
473+ >;
474+ };
475+
476+ pinctrl_uart1: uart1grp {
477+ fsl,pins = <
478+ MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
479+ MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
480+ MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x4001b0b1
481+ >;
482+ };
483+
484+ pinctrl_uart2: uart2grp {
485+ fsl,pins = <
486+ MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
487+ MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
488+ MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x4001b0b1
489+ >;
490+ };
491+
492+ pinctrl_uart5: uart5grp {
493+ fsl,pins = <
494+ MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
495+ MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
496+ >;
497+ };
498+
499+ pinctrl_usbotg: usbotggrp {
500+ fsl,pins = <
501+ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059
502+ >;
503+ };
504+
505+ pinctrl_usdhc3: usdhc3grp {
506+ fsl,pins = <
507+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
508+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
509+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
510+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
511+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
512+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
513+ MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */
514+ MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059
515+ >;
516+ };
517+
518+ pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
519+ fsl,pins = <
520+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
521+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
522+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
523+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
524+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
525+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
526+ MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */
527+ MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9
528+ >;
529+ };
530+
531+ pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
532+ fsl,pins = <
533+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
534+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
535+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
536+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
537+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
538+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
539+ MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
540+ MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
541+ >;
542+ };
543+
544+ pinctrl_wdog: wdoggrp {
545+ fsl,pins = <
546+ MX6QDL_PAD_SD1_DAT3__WDOG2_B 0x1b0b0
547+ >;
548+ };
549+};