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192.168.1.100 / T108 / d984209af4c620468a3584fa1f88edd8aacca6b0 / . / marvell / linux / arch / arm / boot / dts / omap3-n900.dts
blob: 4227da71cc62694461e9ed2592c94e5cd37d49bc [file] [log] [blame]
b.liue9582032025-04-17 19:18:16 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright (C) 2013 Pavel Machek <pavel@ucw.cz>
4 * Copyright (C) 2013-2014 Aaro Koskinen <aaro.koskinen@iki.fi>
5 */
6
7/dts-v1/;
8
9#include "omap34xx.dtsi"
10#include <dt-bindings/input/input.h>
11
12/*
13 * Default secure signed bootloader (Nokia X-Loader) does not enable L3 firewall
14 * for omap AES HW crypto support. When linux kernel try to access memory of AES
15 * blocks then kernel receive "Unhandled fault: external abort on non-linefetch"
16 * and crash. Until somebody fix omap-aes.c and omap_hwmod_3xxx_data.c code (no
17 * crash anymore) omap AES support will be disabled for all Nokia N900 devices.
18 * There is "unofficial" version of bootloader which enables AES in L3 firewall
19 * but it is not widely used and to prevent kernel crash rather AES is disabled.
20 * There is also no runtime detection code if AES is disabled in L3 firewall...
21 */
22&aes {
23 status = "disabled";
24};
25
26/ {
27 model = "Nokia N900";
28 compatible = "nokia,omap3-n900", "ti,omap3430", "ti,omap3";
29
30 aliases {
31 i2c0;
32 i2c1 = &i2c1;
33 i2c2 = &i2c2;
34 i2c3 = &i2c3;
35 display0 = &lcd;
36 display1 = &tv;
37 };
38
39 cpus {
40 cpu@0 {
41 cpu0-supply = <&vcc>;
42 };
43 };
44
45 leds {
46 compatible = "gpio-leds";
47 heartbeat {
48 label = "debug::sleep";
49 gpios = <&gpio6 2 GPIO_ACTIVE_HIGH>; /* 162 */
50 linux,default-trigger = "default-on";
51 pinctrl-names = "default";
52 pinctrl-0 = <&debug_leds>;
53 };
54 };
55
56 memory@80000000 {
57 device_type = "memory";
58 reg = <0x80000000 0x10000000>; /* 256 MB */
59 };
60
61 gpio_keys {
62 compatible = "gpio-keys";
63
64 camera_lens_cover {
65 label = "Camera Lens Cover";
66 gpios = <&gpio4 14 GPIO_ACTIVE_LOW>; /* 110 */
67 linux,input-type = <EV_SW>;
68 linux,code = <SW_CAMERA_LENS_COVER>;
69 linux,can-disable;
70 };
71
72 camera_focus {
73 label = "Camera Focus";
74 gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; /* 68 */
75 linux,code = <KEY_CAMERA_FOCUS>;
76 linux,can-disable;
77 };
78
79 camera_capture {
80 label = "Camera Capture";
81 gpios = <&gpio3 5 GPIO_ACTIVE_LOW>; /* 69 */
82 linux,code = <KEY_CAMERA>;
83 linux,can-disable;
84 };
85
86 lock_button {
87 label = "Lock Button";
88 gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; /* 113 */
89 linux,code = <KEY_SCREENLOCK>;
90 linux,can-disable;
91 };
92
93 keypad_slide {
94 label = "Keypad Slide";
95 gpios = <&gpio3 7 GPIO_ACTIVE_LOW>; /* 71 */
96 linux,input-type = <EV_SW>;
97 linux,code = <SW_KEYPAD_SLIDE>;
98 linux,can-disable;
99 };
100
101 proximity_sensor {
102 label = "Proximity Sensor";
103 gpios = <&gpio3 25 GPIO_ACTIVE_HIGH>; /* 89 */
104 linux,input-type = <EV_SW>;
105 linux,code = <SW_FRONT_PROXIMITY>;
106 linux,can-disable;
107 };
108
109 machine_cover {
110 label = "Machine Cover";
111 gpios = <&gpio6 0 GPIO_ACTIVE_LOW>; /* 160 */
112 linux,input-type = <EV_SW>;
113 linux,code = <SW_MACHINE_COVER>;
114 linux,can-disable;
115 };
116 };
117
118 isp1707: isp1707 {
119 compatible = "nxp,isp1707";
120 nxp,enable-gpio = <&gpio3 3 GPIO_ACTIVE_HIGH>;
121 usb-phy = <&usb2_phy>;
122 };
123
124 tv: connector {
125 compatible = "composite-video-connector";
126 label = "tv";
127
128 port {
129 tv_connector_in: endpoint {
130 remote-endpoint = <&venc_out>;
131 };
132 };
133 };
134
135 sound: n900-audio {
136 compatible = "nokia,n900-audio";
137
138 nokia,cpu-dai = <&mcbsp2>;
139 nokia,audio-codec = <&tlv320aic3x>, <&tlv320aic3x_aux>;
140 nokia,headphone-amplifier = <&tpa6130a2>;
141
142 tvout-selection-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; /* 40 */
143 jack-detection-gpios = <&gpio6 17 GPIO_ACTIVE_HIGH>; /* 177 */
144 eci-switch-gpios = <&gpio6 22 GPIO_ACTIVE_HIGH>; /* 182 */
145 speaker-amplifier-gpios = <&twl_gpio 7 GPIO_ACTIVE_HIGH>;
146 };
147
148 battery: n900-battery {
149 compatible = "nokia,n900-battery";
150 io-channels = <&twl_madc 0>, <&twl_madc 4>, <&twl_madc 12>;
151 io-channel-names = "temp", "bsi", "vbat";
152 };
153
154 pwm9: dmtimer-pwm {
155 compatible = "ti,omap-dmtimer-pwm";
156 #pwm-cells = <3>;
157 ti,timers = <&timer9>;
158 ti,clock-source = <0x00>; /* timer_sys_ck */
159 };
160
161 ir: n900-ir {
162 compatible = "nokia,n900-ir";
163 pwms = <&pwm9 0 26316 0>; /* 38000 Hz */
164 };
165
166 rom_rng: rng {
167 compatible = "nokia,n900-rom-rng";
168 clocks = <&rng_ick>;
169 clock-names = "ick";
170 };
171
172 /* controlled (enabled/disabled) directly by bcm2048 and wl1251 */
173 vctcxo: vctcxo {
174 compatible = "fixed-clock";
175 #clock-cells = <0>;
176 clock-frequency = <38400000>;
177 };
178};
179
180&isp {
181 vdds_csib-supply = <&vaux2>;
182
183 pinctrl-names = "default";
184 pinctrl-0 = <&camera_pins>;
185
186 ports {
187 port@1 {
188 reg = <1>;
189
190 csi_isp: endpoint {
191 remote-endpoint = <&csi_cam1>;
192 bus-type = <3>; /* CCP2 */
193 clock-lanes = <1>;
194 data-lanes = <0>;
195 lane-polarity = <0 0>;
196 /* Select strobe = <1> for back camera, <0> for front camera */
197 strobe = <1>;
198 };
199 };
200 };
201};
202
203&omap3_pmx_core {
204 pinctrl-names = "default";
205
206 uart2_pins: pinmux_uart2_pins {
207 pinctrl-single,pins = <
208 OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts */
209 OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts */
210 OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx */
211 OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx */
212 >;
213 };
214
215 uart3_pins: pinmux_uart3_pins {
216 pinctrl-single,pins = <
217 OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx */
218 OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx */
219 >;
220 };
221
222 ethernet_pins: pinmux_ethernet_pins {
223 pinctrl-single,pins = <
224 OMAP3_CORE1_IOPAD(0x20b4, PIN_INPUT_PULLDOWN | MUX_MODE4) /* gpmc_ncs3.gpio_54 */
225 OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE4) /* dss_data16.gpio_86 */
226 OMAP3_CORE1_IOPAD(0x219c, PIN_OUTPUT | MUX_MODE4) /* uart3_rts_sd.gpio_164 */
227 >;
228 };
229
230 gpmc_pins: pinmux_gpmc_pins {
231 pinctrl-single,pins = <
232
233 /* address lines */
234 OMAP3_CORE1_IOPAD(0x207a, PIN_OUTPUT | MUX_MODE0) /* gpmc_a1.gpmc_a1 */
235 OMAP3_CORE1_IOPAD(0x207c, PIN_OUTPUT | MUX_MODE0) /* gpmc_a2.gpmc_a2 */
236 OMAP3_CORE1_IOPAD(0x207e, PIN_OUTPUT | MUX_MODE0) /* gpmc_a3.gpmc_a3 */
237
238 /* data lines, gpmc_d0..d7 not muxable according to TRM */
239 OMAP3_CORE1_IOPAD(0x209e, PIN_INPUT | MUX_MODE0) /* gpmc_d8.gpmc_d8 */
240 OMAP3_CORE1_IOPAD(0x20a0, PIN_INPUT | MUX_MODE0) /* gpmc_d9.gpmc_d9 */
241 OMAP3_CORE1_IOPAD(0x20a2, PIN_INPUT | MUX_MODE0) /* gpmc_d10.gpmc_d10 */
242 OMAP3_CORE1_IOPAD(0x20a4, PIN_INPUT | MUX_MODE0) /* gpmc_d11.gpmc_d11 */
243 OMAP3_CORE1_IOPAD(0x20a6, PIN_INPUT | MUX_MODE0) /* gpmc_d12.gpmc_d12 */
244 OMAP3_CORE1_IOPAD(0x20a8, PIN_INPUT | MUX_MODE0) /* gpmc_d13.gpmc_d13 */
245 OMAP3_CORE1_IOPAD(0x20aa, PIN_INPUT | MUX_MODE0) /* gpmc_d14.gpmc_d14 */
246 OMAP3_CORE1_IOPAD(0x20ac, PIN_INPUT | MUX_MODE0) /* gpmc_d15.gpmc_d15 */
247
248 /*
249 * gpmc_ncs0, gpmc_nadv_ale, gpmc_noe, gpmc_nwe, gpmc_wait0 not muxable
250 * according to TRM. OneNAND seems to require PIN_INPUT on clock.
251 */
252 OMAP3_CORE1_IOPAD(0x20b0, PIN_OUTPUT | MUX_MODE0) /* gpmc_ncs1.gpmc_ncs1 */
253 OMAP3_CORE1_IOPAD(0x20be, PIN_INPUT | MUX_MODE0) /* gpmc_clk.gpmc_clk */
254 >;
255 };
256
257 i2c1_pins: pinmux_i2c1_pins {
258 pinctrl-single,pins = <
259 OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0) /* i2c1_scl */
260 OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda */
261 >;
262 };
263
264 i2c2_pins: pinmux_i2c2_pins {
265 pinctrl-single,pins = <
266 OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0) /* i2c2_scl */
267 OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0) /* i2c2_sda */
268 >;
269 };
270
271 i2c3_pins: pinmux_i2c3_pins {
272 pinctrl-single,pins = <
273 OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl */
274 OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda */
275 >;
276 };
277
278 debug_leds: pinmux_debug_led_pins {
279 pinctrl-single,pins = <
280 OMAP3_CORE1_IOPAD(0x2198, PIN_OUTPUT | MUX_MODE4) /* mcbsp1_clkx.gpio_162 */
281 >;
282 };
283
284 mcspi4_pins: pinmux_mcspi4_pins {
285 pinctrl-single,pins = <
286 OMAP3_CORE1_IOPAD(0x218c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcspi4_clk */
287 OMAP3_CORE1_IOPAD(0x2192, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcspi4_somi */
288 OMAP3_CORE1_IOPAD(0x2190, PIN_OUTPUT | MUX_MODE1) /* mcspi4_simo */
289 OMAP3_CORE1_IOPAD(0x2196, PIN_OUTPUT | MUX_MODE1) /* mcspi4_cs0 */
290 >;
291 };
292
293 mmc1_pins: pinmux_mmc1_pins {
294 pinctrl-single,pins = <
295 OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk */
296 OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd */
297 OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0 */
298 OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1 */
299 OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2 */
300 OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3 */
301 >;
302 };
303
304 mmc2_pins: pinmux_mmc2_pins {
305 pinctrl-single,pins = <
306 OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk */
307 OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd */
308 OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0 */
309 OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1 */
310 OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2 */
311 OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3 */
312 OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat4 */
313 OMAP3_CORE1_IOPAD(0x2166, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat5 */
314 OMAP3_CORE1_IOPAD(0x2168, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat6 */
315 OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat7 */
316 >;
317 };
318
319 acx565akm_pins: pinmux_acx565akm_pins {
320 pinctrl-single,pins = <
321 OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE4) /* RX51_LCD_RESET_GPIO */
322 >;
323 };
324
325 dss_sdi_pins: pinmux_dss_sdi_pins {
326 pinctrl-single,pins = <
327 OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE1) /* dss_data10.sdi_dat1n */
328 OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE1) /* dss_data11.sdi_dat1p */
329 OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE1) /* dss_data12.sdi_dat2n */
330 OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE1) /* dss_data13.sdi_dat2p */
331
332 OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE1) /* dss_data22.sdi_clkp */
333 OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE1) /* dss_data23.sdi_clkn */
334 >;
335 };
336
337 wl1251_pins: pinmux_wl1251 {
338 pinctrl-single,pins = <
339 OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE4) /* gpio 87 => wl1251 enable */
340 OMAP3_CORE1_IOPAD(0x208a, PIN_INPUT | MUX_MODE4) /* gpio 42 => wl1251 irq */
341 >;
342 };
343
344 ssi_pins: pinmux_ssi {
345 pinctrl-single,pins = <
346 OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT_PULLUP | MUX_MODE1) /* ssi1_rdy_tx */
347 OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE1) /* ssi1_flag_tx */
348 OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE4) /* ssi1_wake_tx (cawake) */
349 OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE1) /* ssi1_dat_tx */
350 OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT | MUX_MODE1) /* ssi1_dat_rx */
351 OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE1) /* ssi1_flag_rx */
352 OMAP3_CORE1_IOPAD(0x2188, PIN_OUTPUT | MUX_MODE1) /* ssi1_rdy_rx */
353 OMAP3_CORE1_IOPAD(0x218a, PIN_OUTPUT | MUX_MODE1) /* ssi1_wake */
354 >;
355 };
356
357 modem_pins: pinmux_modem {
358 pinctrl-single,pins = <
359 OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE4) /* gpio 70 => cmt_apeslpx */
360 OMAP3_CORE1_IOPAD(0x20e0, PIN_INPUT | MUX_MODE4) /* gpio 72 => ape_rst_rq */
361 OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE4) /* gpio 73 => cmt_rst_rq */
362 OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE4) /* gpio 74 => cmt_en */
363 OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE4) /* gpio 75 => cmt_rst */
364 OMAP3_CORE1_IOPAD(0x218e, PIN_OUTPUT | MUX_MODE4) /* gpio 157 => cmt_bsi */
365 >;
366 };
367
368 camera_pins: pinmux_camera {
369 pinctrl-single,pins = <
370 OMAP3_CORE1_IOPAD(0x210c, PIN_OUTPUT | MUX_MODE7) /* cam_hs */
371 OMAP3_CORE1_IOPAD(0x210e, PIN_OUTPUT | MUX_MODE7) /* cam_vs */
372 OMAP3_CORE1_IOPAD(0x2110, PIN_OUTPUT | MUX_MODE0) /* cam_xclka */
373 OMAP3_CORE1_IOPAD(0x211e, PIN_OUTPUT | MUX_MODE7) /* cam_d4 */
374 OMAP3_CORE1_IOPAD(0x2122, PIN_INPUT | MUX_MODE0) /* cam_d6 */
375 OMAP3_CORE1_IOPAD(0x2124, PIN_INPUT | MUX_MODE0) /* cam_d7 */
376 OMAP3_CORE1_IOPAD(0x2126, PIN_INPUT | MUX_MODE0) /* cam_d8 */
377 OMAP3_CORE1_IOPAD(0x2128, PIN_INPUT | MUX_MODE0) /* cam_d9 */
378 OMAP3_CORE1_IOPAD(0x212a, PIN_OUTPUT | MUX_MODE7) /* cam_d10 */
379 OMAP3_CORE1_IOPAD(0x212e, PIN_OUTPUT | MUX_MODE7) /* cam_xclkb */
380 OMAP3_CORE1_IOPAD(0x2132, PIN_OUTPUT | MUX_MODE0) /* cam_strobe */
381 >;
382 };
383};
384
385&i2c1 {
386 pinctrl-names = "default";
387 pinctrl-0 = <&i2c1_pins>;
388
389 clock-frequency = <2200000>;
390
391 twl: twl@48 {
392 reg = <0x48>;
393 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
394 interrupt-parent = <&intc>;
395 };
396};
397
398#include "twl4030.dtsi"
399#include "twl4030_omap3.dtsi"
400
401&vaux1 {
402 regulator-name = "V28";
403 regulator-min-microvolt = <2800000>;
404 regulator-max-microvolt = <2800000>;
405 regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
406 regulator-always-on; /* due to battery cover sensor */
407};
408
409&vaux2 {
410 regulator-name = "VCSI";
411 regulator-min-microvolt = <1800000>;
412 regulator-max-microvolt = <1800000>;
413 regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
414};
415
416&vaux3 {
417 regulator-name = "VMMC2_30";
418 regulator-min-microvolt = <2800000>;
419 regulator-max-microvolt = <3000000>;
420 regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
421};
422
423&vaux4 {
424 regulator-name = "VCAM_ANA_28";
425 regulator-min-microvolt = <2800000>;
426 regulator-max-microvolt = <2800000>;
427 regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
428};
429
430&vmmc1 {
431 regulator-name = "VMMC1";
432 regulator-min-microvolt = <1850000>;
433 regulator-max-microvolt = <3150000>;
434 regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
435};
436
437&vmmc2 {
438 regulator-name = "V28_A";
439 regulator-min-microvolt = <2800000>;
440 regulator-max-microvolt = <3000000>;
441 regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
442 regulator-always-on; /* due VIO leak to AIC34 VDDs */
443};
444
445&vpll1 {
446 regulator-name = "VPLL";
447 regulator-min-microvolt = <1800000>;
448 regulator-max-microvolt = <1800000>;
449 regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
450 regulator-always-on;
451};
452
453&vpll2 {
454 regulator-name = "VSDI_CSI";
455 regulator-min-microvolt = <1800000>;
456 regulator-max-microvolt = <1800000>;
457 regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
458 regulator-always-on;
459};
460
461&vsim {
462 regulator-name = "VMMC2_IO_18";
463 regulator-min-microvolt = <1800000>;
464 regulator-max-microvolt = <1800000>;
465 regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */
466};
467
468&vio {
469 regulator-name = "VIO";
470 regulator-min-microvolt = <1800000>;
471 regulator-max-microvolt = <1800000>;
472};
473
474&vintana1 {
475 regulator-name = "VINTANA1";
476 /* fixed to 1500000 */
477 regulator-always-on;
478};
479
480&vintana2 {
481 regulator-name = "VINTANA2";
482 regulator-min-microvolt = <2750000>;
483 regulator-max-microvolt = <2750000>;
484 regulator-always-on;
485};
486
487&vintdig {
488 regulator-name = "VINTDIG";
489 /* fixed to 1500000 */
490 regulator-always-on;
491};
492
493&twl {
494 twl_audio: audio {
495 compatible = "ti,twl4030-audio";
496 ti,enable-vibra = <1>;
497 };
498
499 twl_power: power {
500 compatible = "ti,twl4030-power-n900", "ti,twl4030-power-idle-osc-off";
501 ti,use_poweroff;
502 };
503};
504
505&twl_keypad {
506 linux,keymap = < MATRIX_KEY(0x00, 0x00, KEY_Q)
507 MATRIX_KEY(0x00, 0x01, KEY_O)
508 MATRIX_KEY(0x00, 0x02, KEY_P)
509 MATRIX_KEY(0x00, 0x03, KEY_COMMA)
510 MATRIX_KEY(0x00, 0x04, KEY_BACKSPACE)
511 MATRIX_KEY(0x00, 0x06, KEY_A)
512 MATRIX_KEY(0x00, 0x07, KEY_S)
513
514 MATRIX_KEY(0x01, 0x00, KEY_W)
515 MATRIX_KEY(0x01, 0x01, KEY_D)
516 MATRIX_KEY(0x01, 0x02, KEY_F)
517 MATRIX_KEY(0x01, 0x03, KEY_G)
518 MATRIX_KEY(0x01, 0x04, KEY_H)
519 MATRIX_KEY(0x01, 0x05, KEY_J)
520 MATRIX_KEY(0x01, 0x06, KEY_K)
521 MATRIX_KEY(0x01, 0x07, KEY_L)
522
523 MATRIX_KEY(0x02, 0x00, KEY_E)
524 MATRIX_KEY(0x02, 0x01, KEY_DOT)
525 MATRIX_KEY(0x02, 0x02, KEY_UP)
526 MATRIX_KEY(0x02, 0x03, KEY_ENTER)
527 MATRIX_KEY(0x02, 0x05, KEY_Z)
528 MATRIX_KEY(0x02, 0x06, KEY_X)
529 MATRIX_KEY(0x02, 0x07, KEY_C)
530 MATRIX_KEY(0x02, 0x08, KEY_F9)
531
532 MATRIX_KEY(0x03, 0x00, KEY_R)
533 MATRIX_KEY(0x03, 0x01, KEY_V)
534 MATRIX_KEY(0x03, 0x02, KEY_B)
535 MATRIX_KEY(0x03, 0x03, KEY_N)
536 MATRIX_KEY(0x03, 0x04, KEY_M)
537 MATRIX_KEY(0x03, 0x05, KEY_SPACE)
538 MATRIX_KEY(0x03, 0x06, KEY_SPACE)
539 MATRIX_KEY(0x03, 0x07, KEY_LEFT)
540
541 MATRIX_KEY(0x04, 0x00, KEY_T)
542 MATRIX_KEY(0x04, 0x01, KEY_DOWN)
543 MATRIX_KEY(0x04, 0x02, KEY_RIGHT)
544 MATRIX_KEY(0x04, 0x04, KEY_LEFTCTRL)
545 MATRIX_KEY(0x04, 0x05, KEY_RIGHTALT)
546 MATRIX_KEY(0x04, 0x06, KEY_LEFTSHIFT)
547 MATRIX_KEY(0x04, 0x08, KEY_F10)
548
549 MATRIX_KEY(0x05, 0x00, KEY_Y)
550 MATRIX_KEY(0x05, 0x08, KEY_F11)
551
552 MATRIX_KEY(0x06, 0x00, KEY_U)
553
554 MATRIX_KEY(0x07, 0x00, KEY_I)
555 MATRIX_KEY(0x07, 0x01, KEY_F7)
556 MATRIX_KEY(0x07, 0x02, KEY_F8)
557 >;
558};
559
560&twl_gpio {
561 ti,pullups = <0x0>;
562 ti,pulldowns = <0x03ff3f>; /* BIT(0..5) | BIT(8..17) */
563};
564
565&i2c2 {
566 pinctrl-names = "default";
567 pinctrl-0 = <&i2c2_pins>;
568
569 clock-frequency = <100000>;
570
571 tlv320aic3x: tlv320aic3x@18 {
572 compatible = "ti,tlv320aic3x";
573 reg = <0x18>;
574 reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; /* 60 */
575 ai3x-gpio-func = <
576 0 /* AIC3X_GPIO1_FUNC_DISABLED */
577 5 /* AIC3X_GPIO2_FUNC_DIGITAL_MIC_INPUT */
578 >;
579
580 AVDD-supply = <&vmmc2>;
581 DRVDD-supply = <&vmmc2>;
582 IOVDD-supply = <&vio>;
583 DVDD-supply = <&vio>;
584
585 ai3x-micbias-vg = <1>;
586 };
587
588 tlv320aic3x_aux: tlv320aic3x@19 {
589 compatible = "ti,tlv320aic3x";
590 reg = <0x19>;
591 reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; /* 60 */
592
593 AVDD-supply = <&vmmc2>;
594 DRVDD-supply = <&vmmc2>;
595 IOVDD-supply = <&vio>;
596 DVDD-supply = <&vio>;
597
598 ai3x-micbias-vg = <2>;
599 };
600
601 tsl2563: tsl2563@29 {
602 compatible = "amstaos,tsl2563";
603 reg = <0x29>;
604
605 amstaos,cover-comp-gain = <16>;
606 };
607
608 adp1653: led-controller@30 {
609 compatible = "adi,adp1653";
610 reg = <0x30>;
611 enable-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; /* 88 */
612
613 flash {
614 flash-timeout-us = <500000>;
615 flash-max-microamp = <320000>;
616 led-max-microamp = <50000>;
617 };
618 indicator {
619 led-max-microamp = <17500>;
620 };
621 };
622
623 lp5523: lp5523@32 {
624 compatible = "national,lp5523";
625 reg = <0x32>;
626 clock-mode = /bits/ 8 <0>; /* LP55XX_CLOCK_AUTO */
627 enable-gpio = <&gpio2 9 GPIO_ACTIVE_HIGH>; /* 41 */
628
629 chan0 {
630 chan-name = "lp5523:kb1";
631 led-cur = /bits/ 8 <50>;
632 max-cur = /bits/ 8 <100>;
633 };
634
635 chan1 {
636 chan-name = "lp5523:kb2";
637 led-cur = /bits/ 8 <50>;
638 max-cur = /bits/ 8 <100>;
639 };
640
641 chan2 {
642 chan-name = "lp5523:kb3";
643 led-cur = /bits/ 8 <50>;
644 max-cur = /bits/ 8 <100>;
645 };
646
647 chan3 {
648 chan-name = "lp5523:kb4";
649 led-cur = /bits/ 8 <50>;
650 max-cur = /bits/ 8 <100>;
651 };
652
653 chan4 {
654 chan-name = "lp5523:b";
655 led-cur = /bits/ 8 <50>;
656 max-cur = /bits/ 8 <100>;
657 };
658
659 chan5 {
660 chan-name = "lp5523:g";
661 led-cur = /bits/ 8 <50>;
662 max-cur = /bits/ 8 <100>;
663 };
664
665 chan6 {
666 chan-name = "lp5523:r";
667 led-cur = /bits/ 8 <50>;
668 max-cur = /bits/ 8 <100>;
669 };
670
671 chan7 {
672 chan-name = "lp5523:kb5";
673 led-cur = /bits/ 8 <50>;
674 max-cur = /bits/ 8 <100>;
675 };
676
677 chan8 {
678 chan-name = "lp5523:kb6";
679 led-cur = /bits/ 8 <50>;
680 max-cur = /bits/ 8 <100>;
681 };
682 };
683
684 bq27200: bq27200@55 {
685 compatible = "ti,bq27200";
686 reg = <0x55>;
687 power-supplies = <&bq24150a>;
688 };
689
690 /* Stereo headphone amplifier */
691 tpa6130a2: tpa6130a2@60 {
692 compatible = "ti,tpa6130a2";
693 reg = <0x60>;
694
695 Vdd-supply = <&vmmc2>;
696
697 power-gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>; /* 98 */
698 };
699
700 si4713: si4713@63 {
701 compatible = "silabs,si4713";
702 reg = <0x63>;
703
704 interrupts-extended = <&gpio2 21 IRQ_TYPE_EDGE_FALLING>; /* 53 */
705 reset-gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; /* 163 */
706 vio-supply = <&vio>;
707 vdd-supply = <&vaux1>;
708 };
709
710 bq24150a: bq24150a@6b {
711 compatible = "ti,bq24150a";
712 reg = <0x6b>;
713
714 ti,current-limit = <100>;
715 ti,weak-battery-voltage = <3400>;
716 ti,battery-regulation-voltage = <4200>;
717 ti,charge-current = <650>;
718 ti,termination-current = <100>;
719 ti,resistor-sense = <68>;
720
721 ti,usb-charger-detection = <&isp1707>;
722 };
723};
724
725&i2c3 {
726 pinctrl-names = "default";
727 pinctrl-0 = <&i2c3_pins>;
728
729 clock-frequency = <400000>;
730
731 lis302dl: lis3lv02d@1d {
732 compatible = "st,lis3lv02d";
733 reg = <0x1d>;
734
735 Vdd-supply = <&vaux1>;
736 Vdd_IO-supply = <&vio>;
737
738 interrupt-parent = <&gpio6>;
739 interrupts = <21 20>; /* 181 and 180 */
740
741 /* click flags */
742 st,click-single-x;
743 st,click-single-y;
744 st,click-single-z;
745
746 /* Limits are 0.5g * value */
747 st,click-threshold-x = <8>;
748 st,click-threshold-y = <8>;
749 st,click-threshold-z = <10>;
750
751 /* Click must be longer than time limit */
752 st,click-time-limit = <9>;
753
754 /* Kind of debounce filter */
755 st,click-latency = <50>;
756
757 /* Interrupt line 2 for click detection */
758 st,irq2-click;
759
760 st,wakeup-x-hi;
761 st,wakeup-y-hi;
762 st,wakeup-threshold = <(800/18)>; /* millig-value / 18 to get HW values */
763
764 st,wakeup2-z-hi;
765 st,wakeup2-threshold = <(900/18)>; /* millig-value / 18 to get HW values */
766
767 st,hipass1-disable;
768 st,hipass2-disable;
769
770 st,axis-x = <1>; /* LIS3_DEV_X */
771 st,axis-y = <(-2)>; /* LIS3_INV_DEV_Y */
772 st,axis-z = <(-3)>; /* LIS3_INV_DEV_Z */
773
774 st,min-limit-x = <(-32)>;
775 st,min-limit-y = <3>;
776 st,min-limit-z = <3>;
777
778 st,max-limit-x = <(-3)>;
779 st,max-limit-y = <32>;
780 st,max-limit-z = <32>;
781 };
782
783 cam1: camera@3e {
784 compatible = "toshiba,et8ek8";
785 reg = <0x3e>;
786
787 vana-supply = <&vaux4>;
788
789 clocks = <&isp 0>;
790 clock-names = "extclk";
791 clock-frequency = <9600000>;
792
793 reset-gpio = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* 102 */
794
795 lens-focus = <&ad5820>;
796
797 port {
798 csi_cam1: endpoint {
799 bus-type = <3>; /* CCP2 */
800 strobe = <1>;
801 clock-inv = <0>;
802 crc = <1>;
803
804 remote-endpoint = <&csi_isp>;
805 };
806 };
807 };
808
809 /* D/A converter for auto-focus */
810 ad5820: dac@c {
811 compatible = "adi,ad5820";
812 reg = <0x0c>;
813
814 VANA-supply = <&vaux4>;
815
816 #io-channel-cells = <0>;
817 };
818};
819
820&mmc1 {
821 pinctrl-names = "default";
822 pinctrl-0 = <&mmc1_pins>;
823 vmmc-supply = <&vmmc1>;
824 bus-width = <4>;
825};
826
827/* most boards use vaux3, only some old versions use vmmc2 instead */
828&mmc2 {
829 pinctrl-names = "default";
830 pinctrl-0 = <&mmc2_pins>;
831 vmmc-supply = <&vaux3>;
832 vqmmc-supply = <&vsim>;
833 bus-width = <8>;
834 non-removable;
835 no-sdio;
836 no-sd;
837};
838
839&mmc3 {
840 status = "disabled";
841};
842
843&gpmc {
844 ranges = <0 0 0x01000000 0x01000000>, /* 16 MB for OneNAND */
845 <1 0 0x02000000 0x01000000>; /* 16 MB for smc91c96 */
846 pinctrl-names = "default";
847 pinctrl-0 = <&gpmc_pins>;
848
849 /* sys_ndmareq1 could be used by the driver, not as gpio65 though */
850 onenand@0,0 {
851 #address-cells = <1>;
852 #size-cells = <1>;
853 compatible = "ti,omap2-onenand";
854 reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */
855
856 /*
857 * These timings are based on CONFIG_OMAP_GPMC_DEBUG=y reported
858 * bootloader set values when booted with v5.1
859 * (OneNAND Manufacturer: Samsung):
860 *
861 * cs0 GPMC_CS_CONFIG1: 0xfb001202
862 * cs0 GPMC_CS_CONFIG2: 0x00111100
863 * cs0 GPMC_CS_CONFIG3: 0x00020200
864 * cs0 GPMC_CS_CONFIG4: 0x11001102
865 * cs0 GPMC_CS_CONFIG5: 0x03101616
866 * cs0 GPMC_CS_CONFIG6: 0x90060000
867 */
868 gpmc,sync-read;
869 gpmc,sync-write;
870 gpmc,burst-length = <16>;
871 gpmc,burst-read;
872 gpmc,burst-wrap;
873 gpmc,burst-write;
874 gpmc,device-width = <2>;
875 gpmc,mux-add-data = <2>;
876 gpmc,cs-on-ns = <0>;
877 gpmc,cs-rd-off-ns = <102>;
878 gpmc,cs-wr-off-ns = <102>;
879 gpmc,adv-on-ns = <0>;
880 gpmc,adv-rd-off-ns = <12>;
881 gpmc,adv-wr-off-ns = <12>;
882 gpmc,oe-on-ns = <12>;
883 gpmc,oe-off-ns = <102>;
884 gpmc,we-on-ns = <0>;
885 gpmc,we-off-ns = <102>;
886 gpmc,rd-cycle-ns = <132>;
887 gpmc,wr-cycle-ns = <132>;
888 gpmc,access-ns = <96>;
889 gpmc,page-burst-access-ns = <18>;
890 gpmc,bus-turnaround-ns = <0>;
891 gpmc,cycle2cycle-delay-ns = <0>;
892 gpmc,wait-monitoring-ns = <0>;
893 gpmc,clk-activation-ns = <6>;
894 gpmc,wr-data-mux-bus-ns = <36>;
895 gpmc,wr-access-ns = <96>;
896 gpmc,sync-clk-ps = <15000>;
897
898 /*
899 * MTD partition table corresponding to Nokia's
900 * Maemo 5 (Fremantle) release.
901 */
902 partition@0 {
903 label = "bootloader";
904 reg = <0x00000000 0x00020000>;
905 read-only;
906 };
907 partition@1 {
908 label = "config";
909 reg = <0x00020000 0x00060000>;
910 };
911 partition@2 {
912 label = "log";
913 reg = <0x00080000 0x00040000>;
914 };
915 partition@3 {
916 label = "kernel";
917 reg = <0x000c0000 0x00200000>;
918 };
919 partition@4 {
920 label = "initfs";
921 reg = <0x002c0000 0x00200000>;
922 };
923 partition@5 {
924 label = "rootfs";
925 reg = <0x004c0000 0x0fb40000>;
926 };
927 };
928
929 /* Ethernet is on some early development boards and qemu */
930 ethernet@gpmc {
931 compatible = "smsc,lan91c94";
932 interrupt-parent = <&gpio2>;
933 interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; /* gpio54 */
934 reg = <1 0 0xf>; /* 16 byte IO range */
935 bank-width = <2>;
936 pinctrl-names = "default";
937 pinctrl-0 = <&ethernet_pins>;
938 power-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; /* gpio86 */
939 reset-gpios = <&gpio6 4 GPIO_ACTIVE_HIGH>; /* gpio164 */
940 gpmc,device-width = <2>;
941 gpmc,sync-clk-ps = <0>;
942 gpmc,cs-on-ns = <0>;
943 gpmc,cs-rd-off-ns = <48>;
944 gpmc,cs-wr-off-ns = <24>;
945 gpmc,adv-on-ns = <0>;
946 gpmc,adv-rd-off-ns = <0>;
947 gpmc,adv-wr-off-ns = <0>;
948 gpmc,we-on-ns = <12>;
949 gpmc,we-off-ns = <18>;
950 gpmc,oe-on-ns = <12>;
951 gpmc,oe-off-ns = <48>;
952 gpmc,page-burst-access-ns = <0>;
953 gpmc,access-ns = <42>;
954 gpmc,rd-cycle-ns = <180>;
955 gpmc,wr-cycle-ns = <180>;
956 gpmc,bus-turnaround-ns = <0>;
957 gpmc,cycle2cycle-delay-ns = <0>;
958 gpmc,wait-monitoring-ns = <0>;
959 gpmc,clk-activation-ns = <0>;
960 gpmc,wr-access-ns = <0>;
961 gpmc,wr-data-mux-bus-ns = <12>;
962 };
963};
964
965&mcspi1 {
966 /*
967 * For some reason, touchscreen is necessary for screen to work at
968 * all on real hw. It works well without it on emulator.
969 *
970 * Also... order in the device tree actually matters here.
971 */
972 tsc2005@0 {
973 compatible = "ti,tsc2005";
974 spi-max-frequency = <6000000>;
975 reg = <0>;
976
977 vio-supply = <&vio>;
978
979 reset-gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; /* 104 */
980 interrupts-extended = <&gpio4 4 IRQ_TYPE_EDGE_RISING>; /* 100 */
981
982 touchscreen-fuzz-x = <4>;
983 touchscreen-fuzz-y = <7>;
984 touchscreen-fuzz-pressure = <2>;
985 touchscreen-size-x = <4096>;
986 touchscreen-size-y = <4096>;
987 touchscreen-max-pressure = <2048>;
988
989 ti,x-plate-ohms = <280>;
990 ti,esd-recovery-timeout-ms = <8000>;
991 };
992
993 lcd: acx565akm@2 {
994 compatible = "sony,acx565akm";
995 spi-max-frequency = <6000000>;
996 reg = <2>;
997
998 pinctrl-names = "default";
999 pinctrl-0 = <&acx565akm_pins>;
1000
1001 label = "lcd";
1002 reset-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>; /* 90 */
1003
1004 port {
1005 lcd_in: endpoint {
1006 remote-endpoint = <&sdi_out>;
1007 };
1008 };
1009 };
1010};
1011
1012&mcspi4 {
1013 pinctrl-names = "default";
1014 pinctrl-0 = <&mcspi4_pins>;
1015
1016 wl1251@0 {
1017 pinctrl-names = "default";
1018 pinctrl-0 = <&wl1251_pins>;
1019
1020 vio-supply = <&vio>;
1021
1022 compatible = "ti,wl1251";
1023 reg = <0>;
1024 spi-max-frequency = <48000000>;
1025
1026 spi-cpol;
1027 spi-cpha;
1028
1029 ti,power-gpio = <&gpio3 23 GPIO_ACTIVE_HIGH>; /* 87 */
1030
1031 interrupt-parent = <&gpio2>;
1032 interrupts = <10 IRQ_TYPE_NONE>; /* gpio line 42 */
1033
1034 clocks = <&vctcxo>;
1035 };
1036};
1037
1038&usb_otg_hs {
1039 interface-type = <0>;
1040 usb-phy = <&usb2_phy>;
1041 phys = <&usb2_phy>;
1042 phy-names = "usb2-phy";
1043 mode = <2>;
1044 power = <50>;
1045};
1046
1047&uart1 {
1048 status = "disabled";
1049};
1050
1051&uart2 {
1052 pinctrl-names = "default";
1053 pinctrl-0 = <&uart2_pins>;
1054
1055 bcm2048: bluetooth {
1056 compatible = "brcm,bcm2048-nokia", "nokia,h4p-bluetooth";
1057 reset-gpios = <&gpio3 27 GPIO_ACTIVE_LOW>; /* 91 */
1058 host-wakeup-gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; /* 101 */
1059 bluetooth-wakeup-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; /* 37 */
1060 clocks = <&vctcxo>;
1061 clock-names = "sysclk";
1062 };
1063};
1064
1065&uart3 {
1066 interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>;
1067 pinctrl-names = "default";
1068 pinctrl-0 = <&uart3_pins>;
1069};
1070
1071&dss {
1072 status = "ok";
1073
1074 pinctrl-names = "default";
1075 pinctrl-0 = <&dss_sdi_pins>;
1076
1077 vdds_sdi-supply = <&vaux1>;
1078
1079 ports {
1080 #address-cells = <1>;
1081 #size-cells = <0>;
1082
1083 port@1 {
1084 reg = <1>;
1085
1086 sdi_out: endpoint {
1087 remote-endpoint = <&lcd_in>;
1088 datapairs = <2>;
1089 };
1090 };
1091 };
1092};
1093
1094&venc {
1095 status = "ok";
1096
1097 vdda-supply = <&vdac>;
1098
1099 port {
1100 venc_out: endpoint {
1101 remote-endpoint = <&tv_connector_in>;
1102 ti,channels = <1>;
1103 };
1104 };
1105};
1106
1107&mcbsp2 {
1108 status = "ok";
1109};
1110
1111&ssi_port1 {
1112 pinctrl-names = "default";
1113 pinctrl-0 = <&ssi_pins>;
1114
1115 ti,ssi-cawake-gpio = <&gpio5 23 GPIO_ACTIVE_HIGH>; /* 151 */
1116
1117 modem: hsi-client {
1118 compatible = "nokia,n900-modem";
1119
1120 pinctrl-names = "default";
1121 pinctrl-0 = <&modem_pins>;
1122
1123 hsi-channel-ids = <0>, <1>, <2>, <3>;
1124 hsi-channel-names = "mcsaab-control",
1125 "speech-control",
1126 "speech-data",
1127 "mcsaab-data";
1128 hsi-speed-kbps = <55000>;
1129 hsi-mode = "frame";
1130 hsi-flow = "synchronized";
1131 hsi-arb-mode = "round-robin";
1132
1133 interrupts-extended = <&gpio3 8 IRQ_TYPE_EDGE_FALLING>; /* 72 */
1134
1135 gpios = <&gpio3 6 GPIO_ACTIVE_HIGH>, /* 70 */
1136 <&gpio3 9 GPIO_ACTIVE_HIGH>, /* 73 */
1137 <&gpio3 10 GPIO_ACTIVE_HIGH>, /* 74 */
1138 <&gpio3 11 GPIO_ACTIVE_HIGH>, /* 75 */
1139 <&gpio5 29 GPIO_ACTIVE_HIGH>; /* 157 */
1140 gpio-names = "cmt_apeslpx",
1141 "cmt_rst_rq",
1142 "cmt_en",
1143 "cmt_rst",
1144 "cmt_bsi";
1145 };
1146};
1147
1148&ssi_port2 {
1149 status = "disabled";
1150};