| b.liu | e958203 | 2025-04-17 19:18:16 +0800 | [diff] [blame^] | 1 | * Atmel I2S controller | 
 | 2 |  | 
 | 3 | Required properties: | 
 | 4 | - compatible:     Should be "atmel,sama5d2-i2s". | 
 | 5 | - reg:            Should be the physical base address of the controller and the | 
 | 6 |                   length of memory mapped region. | 
 | 7 | - interrupts:     Should contain the interrupt for the controller. | 
 | 8 | - dmas:           Should be one per channel name listed in the dma-names property, | 
 | 9 |                   as described in atmel-dma.txt and dma.txt files. | 
 | 10 | - dma-names:      Two dmas have to be defined, "tx" and "rx". | 
 | 11 |                   This IP also supports one shared channel for both rx and tx; | 
 | 12 |                   if this mode is used, one "rx-tx" name must be used. | 
 | 13 | - clocks:         Must contain an entry for each entry in clock-names. | 
 | 14 |                   Please refer to clock-bindings.txt. | 
 | 15 | - clock-names:    Should be one of each entry matching the clocks phandles list: | 
 | 16 |                   - "pclk" (peripheral clock) Required. | 
 | 17 |                   - "gclk" (generated clock) Optional (1). | 
 | 18 |                   - "muxclk" (I2S mux clock) Optional (1). | 
 | 19 |  | 
 | 20 | Optional properties: | 
 | 21 | - pinctrl-0:      Should specify pin control groups used for this controller. | 
 | 22 | - princtrl-names: Should contain only one value - "default". | 
 | 23 |  | 
 | 24 |  | 
 | 25 | (1) : Only the peripheral clock is required. The generated clock and the I2S | 
 | 26 |       mux clock are optional and should only be set together, when Master Mode | 
 | 27 |       is required. | 
 | 28 |  | 
 | 29 | Example: | 
 | 30 |  | 
 | 31 | 	i2s@f8050000 { | 
 | 32 | 		compatible = "atmel,sama5d2-i2s"; | 
 | 33 | 		reg = <0xf8050000 0x300>; | 
 | 34 | 		interrupts = <54 IRQ_TYPE_LEVEL_HIGH 7>; | 
 | 35 | 		dmas = <&dma0 | 
 | 36 | 			(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | | 
 | 37 | 			 AT91_XDMAC_DT_PERID(31))>, | 
 | 38 | 		       <&dma0 | 
 | 39 | 			(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | | 
 | 40 | 			 AT91_XDMAC_DT_PERID(32))>; | 
 | 41 | 		dma-names = "tx", "rx"; | 
 | 42 | 		clocks = <&i2s0_clk>, <&i2s0_gclk>, <&i2s0muxck>; | 
 | 43 | 		clock-names = "pclk", "gclk", "muxclk"; | 
 | 44 | 		pinctrl-names = "default"; | 
 | 45 | 		pinctrl-0 = <&pinctrl_i2s0_default>; | 
 | 46 | 	}; |